SU1388856A1 - Device for extracting a square root - Google Patents

Abstract

The invention relates to computing and can be used in digital functionaries-pK ppjfH VvV-vvv. , -t oi-f tf-fi lgz l-Z o2-t f- / n 2-t 2 2 transducers and digital measuring devices for information processing - represented by a number-pulse code. The purpose of the invention is to increase the speed of the device. Introduction of a device containing a counter 5, a group of 4 elements AND, elements OR 1,2, a controlled counter 3 and a local control unit 6 with appropriate connections into the composition allows to significantly reduce the pulse flow in the positive feedback circuit. At the same time, each pulse arriving at the information input of the device corresponds to no more than one pulse in the positive feedback circuit. 3 dw., 2 tabl. i cl 20 2 ut-H

Description

1

The device relates to computing technology and can be used in digital function transducers and digital measuring devices for processing information represented by a number-pulse code.

The purpose of the invention is to increase the speed of the device.

Fig. 1 shows a block diagram of a device for extracting a square root; in fig. 2 and 3 are embodiments of a controlled counter and local control unit, respectively.

The device (Fig. 1) contains the first 1 and second 2 OR elements, the control counter 3, the group 4 of elements AND, the counter 5 and the local control block 6.

The controllable counter 3 (Fig. 2) includes the elements And 7 ", ,, counting triggers 8, - 8 and the elements ШШ 9, - 9" ...

The local control unit 6 (Fig. 3) contains the elements OR 10 ,. and elements EXCLUSIVE OR 11, -11 „,. The total number of bits of the controlled counter 3 is equal to ha ,,, and the counter 5 - m – 1.

The device works as follows.

Before you start, the signal applied to the installation: (device input

The unit transfers counters 3 and 5 to the zero initial state. The output signals of the control circuit 6 are uniquely determined by the number contained in the counter 5. In this case, the level 1 is present at each moment of time only on one of its outputs, depending on whether. How many zeros are contained in the higher bits of counter 5.

The correspondence between the input and output signals of the control block b is given in Table. one"

In tab. 1 the following notation is accepted: b, b ,, ..., bn ,, ,, b, the values of the digits of the number contained in the counter 5; c, s., s.-.- c. X is an indifferent bit value.

According to the table. 1 in the initial state of the device, the unit is present at the output of control unit 6,

0

five

0

five

ABOUT

five

0 5

° 5

which is connected to the element And 7 controlled counter 3, i.e. c, 1. Consequently, the first pulse arriving at the information input of the device passes through the elements AND 7 and OR 9 of the controlled counter 3 and writes the unit to the counter 5. In accordance with the bit weights of counters 3 and 5 shown in FIG. 1, the conversion result recorded in them after the arrival of the first input pulse is. After that, level 1 appears at the next output of control unit 6, i.e. c. The second impulse, received at the information input of the device, passes through the elements AND and OR 9t-d of the controlled counter 3 and enters the counting input of the trigger 8 ,. Thus, with 1, the controlled counter 3 operates in the two-bit counter mode. In the future, each change per unit number of zeros contained in the higher bits of counter 5 results in the appearance of level 1 at the next output of control unit 6 and, consequently, control counter 3 is switched to the operation mode with an increase of its number by one bits

In the general case with,,

L „-rO H, ° 5 ™ where S takes any value from the range O, 1,2, ... 5m-2. When in controllable counter 3, element 7 is open. Consequently, the pulses arriving at the input of the counter 3 pass through the elements AND ,, and OR the counting input of the trigger,. Thus, with с 1, the triggers s 8.5 8.54, 8 ". ,, 8, included in the controlled counter 3, i.e. It operates in a (5 + 2) -disk binary counter mode.

Managed counter 3, a group of 4 elements And, counter 5 and an element OR 2 constitute a binary multiplier. When a binary multiplier is used, S + 2 most significant bits of counter 3 and S + 1 low bits of counter 5 are involved. The number contained in these bits of counters 3 and 5 is denoted by NH and represent it as

S + 1

3 2 +

.

Yi

1 -S-2

where a.

.., and I are the digits of the number contained in the counter 3.

In accordance with the bit weights shown in FIG. 1, the conversion result of Np, recorded in counters 3 and 5, is equal to

(2)

Consider the operation of the device in the range

, 25 + 3

  , (3)

corresponding to c 1.

Taking into account that the control inputs of the group of 4 elements and the inverse code of the number contained in the account

5, increment of the number of impulses

cos (f, received at the input of the binary multiplier (i.e., at the output of the element OR 2) in the range (3), can be determined from the equation

dcf, (4)

 the total number of bits of counters 3 and 5, participating in the work of the binary multiplier with

 one;

increment the number of pulses IJ received at the input of counter 3 in the range (3)

According to the accepted notation, you can write

N

but

2 +

1388856

At the starting point of the range (3)

N.,

,

and

0. When N 2

IS g

ten

from equation (2) we obtain, Since the range (3) is defined in general, i.e. with, 1,2, ..., t-2 we have a number of subranges, which overlap in the aggregate the whole range of the device operation, then, without breaking the generality of the presentation, we can conclude that the number corresponds to the number X NP 2. Having integrated the given limits differential equation (8),

will get

 but

one

2S + 1, 25

+ y) dy 2

l

3

(9)

20

. (ten)

2 y

4S44 -2.S + 4

2 -2,

(YU

Positive square root

(11) equals

-25 equations

„S

Have

.

 2 47 - 2

2S + a

(12)

(6) and (12) after 30

35

40

stand by

45

From equations (2), blowing

NP 4. (13)

Equation (13) is valid for all S 0,1, 2 ,. .., t-2 and, therefore, in the entire range of operation of the device in question.

In tab. Figure 2 shows an example of the operation of the device for extracting the square root at. Here y denotes the total number of pulses transmitted through the element OR 1, and Cf - o6Dtee the number of pulses at the output of the element OR 2. In the last column, Table. 2 shows the absolute error values of the device defined by the equation

Np-4.

(14)

The increment d y is determined by the sum Jy dx + c) cf,, (7)

where dx is the increment of the number of pulses X arriving at the information input of the device.

From equations (4) - (7) follows

(2 -by) dy

. (eight)

Determine the result of the NP conversion as a function of the number of input pulses X,

The essential difference between the proposed device and the device of the prototype is that each pulse received at its information input can cause no more than one pulse in the positive feedback circuit, closed through the elements OR 1 and 2.

Claims (1)

Invention Formula A square root extractor comprising a counter, a group of AND elements, two OR elements, 513888566 the first and second inputs of the first of the co- that, in order to improve speed, control outputs were entered into it, except for the low-order bit, a controlled counter, the counting input of which is connected to the output of the first IZH element, and the overflow output to the counting input of the counter, nominal control inputs, the control inputs of the controlled counter are connected to the outputs of the local control unit, the inputs of which are connected to direct A linear counter and a local Q-input block of the controlled counter are connected to the installation input of the device, the control input of the AND group element, the signal input of which is connected to the forward high-order output by the counter outputs of the counter, inverse, r, equal The counter, connected to the other bit outputs other than the high-end input 1 of the device, the outputs of the counter-discharge, which are connected to the pack, and the controlled counter are equal inputs of the AND elements of the group, outputs of the device. Table 1 tgb, b „ ... b, b, signal inputs of the elements of which are connected to direct discharge with the outputs, except for the low-order bit, of the controlled counter, the counting input of which is connected to the output of the first IZH element, and the overflow output - to the counting input of the counter, whose installation input and one t 01-2 -d table 2 O -0.1642 +0,0179 1388856 8 Continued table. . et Ct