SU1415430A1 - Binary-signal digital filter - Google Patents

Description

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The invention relates to radio engineering, in particular, to data transmission devices, and can be used in receiving units of information exchange systems to improve noise immunity.

The purpose of the invention is to improve the noise immunity of a digital two-way filter.

The drawing shows a structural electrical circuit of a digital signal filter of a military signal.

Digital binary signal filter contains the element OR NOT 1, the element LI 2, the reversible counter 3, the first element AND 4, the inverter 5, the second element AND 6 and short-trigger 7.

Digital binary signal filter works as follows.

In the initial state, when there is no input signal at the output of the BL-1 element, there is a high potential, which through the OR 2 element affects the transfer input of the reversible counter 3, prohibiting its operation in the counting mode. The clock input of the Eversive counter 3 receives clock pulses, a high Potential is present at the outputs of the counter pulses, the output of the first element and 4 is low potential, the output of inverter 5 is low potential, at the output of the second element I 6 is low potential, The RS-trnger 7 is in the zero state, at its output is a low potential.

When a binary potential signal appears at the input of a digital filter of a logical unit, a low potential occurs at the output of the OR-NOT 1 element, which through the OR 2 element enters the transfer input of the reversible counter 3, allowing it to work in the counting mode, in this case in addition mode clock pulses, By the first clock pulse mode,. the addition at all outputs of the reversible counter 3 is set to a low potential and then the number of clock ones accumulates. pulses to the value when the low-order bits of the reversible counter 3 are set to a high potential state. The presence of a signal of a logical unit at the input of a digital binary signal filter and a high voltage potential on the n bits of the reversible counter 3 leads to the appearance of a high potential.

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at the S-input of the trigger 7, which switches to the one state, transmitting the value of a logical unit to the output of the digital binary signal filter. The arrival of a noise or a burst of the “Loss of impulse” type at this moment leads only to a temporary change in the combination on the first section of the reversible counter 3, and the output signal remains unchanged. The presence of a logical unit signal at the input of a digital binary signal filter and a high potential at the n bits of the reversible counter 3 leads to the appearance of a high potential at the outputs of the first 4 and second 6 AND elements, the OR 2 element, at the transfer input of the reversible counter 3, which blocks the account clock pulses in the direction of addition.

If the potential of the signal at the input of the digital Binary Filter changes from a logical unit to a logical zero, the reversible counter 3 is switched to the subtraction mode, and a low potential occurs at the output of the first element And 4, remove the clock counting lock by the reversing counter 3. in the clock subtraction mode, the reversible counter 3 calculates to a position in which all bits are in the state of logical zero and, on the next clock pulse, all bits of the reversible counter 3 turn out to be in the Research Institute of the log nical units. The appearance of a logical unit at the output (iH-l) -ro of the discharge of the reversing counter 3 switches the zero state of the short-circuit trigger 7,

At the first input of the element OR-NOT) a low potential appears, and at its output a high potential, which through the element OR 2 acts on the transfer input of the reversible counter 3, blocks the counting of clock pulses in the subtraction mode. When a binary signal again appears at the input of a digital filter of a potential of a logical unit, its operation is repeated,

A digital binary signal filter does not allow single-noise interferences with a duration less than At (where zJt is the period of the clock pulses, n is the number of binary bits of the reversible counter 3, as well as short-term noise packets

False impulse or loss of impulse, the total duration of which at any interval of duration 1 (G is the duration of the elementary parcel (bit) of the binary signal) does not exceed the same value.

Claims (1)

Invention Formula A digital binary signal filter containing a reversible counter, the output of the i-ro bit of which, where i 1, 2, ... n, is connected to the i-th input of the first element AND, (n + 1) -th input of which is connected to the input control the counting direction of the reversible counter and is the input of a digital binary signal filter, the clock inputs of which is the clock input of the reversible counter, and the inverter, the output of which is connected via serial 0 five 0 the second And element and the IGP element with the transfer input of the reversible counter are included, characterized in that, in order to improve noise immunity, an OR-NOT element and an RS flip-flop are introduced, the installation input into the unit of which is connected to the output of the second And element, the RS-flip-flop output The output of the digital filter is a binary signal, and the input of setting the RS flip-flop to zero is connected to the output of the (n +) - th digit of the reversible counter and the input of the inverter, the output of which is connected to the first input of the OR-NOT element, whose second input connected to the entrance control directing down counter counting, an output of OR-NO element is connected to the second input of the OR gate and the output of the first AND element is connected to the second input of the second AND gate,