SU1403357A1 - Digital time discriminator - Google Patents

Abstract

The invention relates to measuring devices for tracking a mid-gate gate for the time position of a pulse signal. The digital time discriminator (CVD) contains N-bit counters 1.2, bitwise accumulator 3, controlled generator of 4 pulses, element NOT 5, block N-1 of elements 2И-OR 7-1, ..., 7- ( Nl), delay unit 6, memory 8, input 10 and output 11 of the bus. CVP has improved resistance to fire. 2 Il.

Description

(L

FIG. one

The invention relates to a pulse technique, in particular, to measuring f devices of the tracking system of the middle of the strobe pulse for the temporal position of the pulse signal.

The purpose of the invention is to improve noise immunity.

FIG. 1 shows a digital time discriminator circuit; in fig. 2 - timing diagrams for the operation of the device.

The digital time discriminator I contains the first N-bit counter 1 pulses, the second counter 2 pulses, the serial adder 3, the controlled pulse generator 4, the HE element 5, the delay unit 6, the N-1 block of elements 2I-OR 7-1, ..., 7- (N-1) storage device 8, the first, SECOND bus 9 (w-gate strobe pulses), the second input bus 10 (bus normalized signal), the output bus 11, at. this second counter 2 is made on; N-1 bits, the input of the controlled gene: rator 4 is connected to the input of the element HE 5 and to the first input bus 9, the output to the counting input of the first and second counters 1 and 2, the inputs of the initial installation of which are connected to the output of the element HE 5, first entrances of the first; elements AND a block of elements 2I-OR i 7-1, ..., 7- (M-1) are connected to the direct I input N-ro bit of counter 1, the second inputs to the direct inputs corresponding to N- 1 bits of the counter 1, the first inputs of the second elements AND the block of elements 2И-OR 7-1, ..., 7- (М-1) - with the inverse output N-ro of the discharge of the counter 1 and the NM input of the first group

40

the inputs of the bit adder 3, the second inputs of the second And elements - with the direct outputs correspond to} N-1 bits of the counter 2, and the third inputs

all elements And are connected to the second d input bus 10 and the input of block 6 for x-holders, the outputs of the elements OR of the block of elements 2И -И1И 7-1 ,. . . , 7- (М-1) are connected to the corresponding N-1 inputs of the first group of inputs of bitwise adder 3, the outputs of which are connected respectively to the information inputs of the storage device 8, the recording resolution of which is connected to the output of the delay unit 6, and the outputs of the storage device 8 connected to the second group of inputs of the parallel adder 3 and to the output bus and.

The discriminator works as follows.

A strobe pulse (s) arriving at the input bus 9, in terms of duration and position corresponding to the controlled time interval, is started by a controlled generator 4. The bus 10 receives a pulse normalized signal (HC) gated by the SI signal, limited by duration and formed on the leading edge. The controlled oscillator 4 generates clock pulses, the temporary position of which is rigidly connected with the beginning of the SI, and the number that in the SI interval determines the SI capacity in tax. As generator 3, devices can be used based, for example, on an external-start clock generator circuit or based on a coincidence circuit signal signal generator based on a clock signal generator.

In the absence of the SI, the element DOES NOT set on the first counter a number equal to

2nd

01

(one)

where is xqi m

- initial installation of the first counter 1;

- counter conversion factor 1;

M - SI capacity in cycles. On the second counter 2, a number is set to

X

og

(2)

0

where X 02 - the initial installation of the counter 2.

When the SR appears, the first and second counters 1 and 2 start counting the so-called impulses, the operation in the addition mode. The number recorded on the M-bit bottom of the binary counter 1 is associated with the state of the counter bits by the ratio

M- (

about 1n-2

X a / 2. + ... + a 2 + a „2

(3)

where X is the number recorded in the counter;

aj is the state of the i-th digit of the counter

a; e (O.,) :;

i e (1, ..., N).

When the position of the NA, the front of which is late relative to

3140

the number of clock pulses will be located between the beginning of the SI and the leading front of the NS

n () + h. 1, (4)

where § is positive

mismatch;

n (S) is the number of clock cycles located between the beginning of the SI and the leading edge of the NN with a positive mismatch.

In this case, the number 1 will be written on the counter 1

X (&)

01

n (j)

g ..

where X, () is the number recorded on the first counter with a positive mismatch, which, according to (3), corresponds to the state in which in the lower N-1 bits of the first counter the positive mismatch will be recorded, and the major will be N th bit will be in the on state, i.e.

X ,, n. ()

(6)

X

, k-1

the number recorded on the N-1 bits of the first counter with a positive mismatch

 N

(7)

In this case, the block of elements 7-1, ..., 7- (Nl) connects to the first group (N-1) of the inputs of the adder 3 outputs of the fallen (N-1) bits of the first counter 1, on which at the moment the occurrence of the NA will be recorded value of positive mismatch (b).

At the N-OM input of the first group of inputs of the adder 3, there is a zero value (7) determined by the state of the inverse output N-ro of the first counter 1, which will correspond to the positive error sign.

When the position of the NA, the front of which anticipates the middle of the SI by the value of the negative mismatch, between the beginning of the SI and the leading edge of the NA will be the number of ticks

p (p j-j

(eight)

Where

- the magnitude of the negative mismatch.

In this case, the first counter will contain the number

X, (Y) X „hp (y) -y-1, (9)

where X (Y) is the number recorded on the first counter with a negative mismatch, which according to (3) corresponds to the state in which the most significant Nth digit of counter I will be in the off state

 ABOUT,

20 25 and on the second counter but the number

(10) 2 will be recorded

Kl-t

Xa (j) (j) 2 -J, (11)

where X (Y) is the number recorded on the second counter with a negative mismatch, which, according to (3), corresponds to the state in which the number (P) will be recorded on the N-1 bits of the second counter 2

2, k-1

(J)

2. (12)

five

0 5

0

five

where X (| f) is the number recorded on the N-1 bits of the second counter with a negative mismatch.

In this case, the block of elements

7-17- (N-l) connect to the first

group (N-I) of the inputs of the adder 3, outputs N-1 of the bits of the second counter 2, on which the value (12) will be fixed at the time of the appearance of the NN. At the N-OM input of the first group of inputs of the adder 3, there is a unit value (U) determined by the state of the inverse output N-ro of the first counter 1 and the corresponding negative error sign.

The number (12) recorded on the second counter 2 in case of negative mismatching is an addition to,. the number (6) recorded on the first counter 1 with a positive mismatch.

Indeed, with equal values of positive and negative mismatch

 U, of)

The numbers (l2) and (6) have the property

X., N-, () H “-. (J) (14)

As follows from (3) for the lower bits of the binary counter, there is the following relation byByroT;

X

., but,. + ... + a „.,, (15)

hye X fj, is the number recorded on the N-I bits of the counter;

X1

HN-1

a, 2% + ... + a, 2% (16) t5

 Hz, - the reverse number written

H.1 N-1 bit counter;

a is the inverse of i-ro bit

g: etchik;

xl-.Aon x. ,,,; (17)

gle, - additional number, addition; from (15), (16), (17) it follows that the lower N-I bits of the counter, the sum of the number (15) and the addition (17) is equal to,

- (18)

X and, +,

Additional

 2

From relations (14) and (18) it follows that the number (12) is an addition to the number (b). If there is s SI and tpylca signal and several pulses into interference, the numbers taken from the top of counter 1 with positive distractions are summed by the sum of pei 3 with the numbers taken from the second from et 2 with negative races; x, at the moments of arrival of input W1, Adder 3 produces a summation of Hiie numbers in an additional course, taking into account the sign of numbers. At the same time, the pulse signal is delayed by the delay unit 6 at the time of the operation of the adder 3. The input to the recording space (V) of the storage device 8, the signal from the output of the power supply unit 6 accumulates the error values by entering the result of the summation into the memory 8. At the same time , the value emitted by the storage device 8 after the termination of the SR will be numerically equal to the distance from the middle of the SR to the front front NS and the sum of the mismatches of all interfering signals that coincide with the strobe. With impulse noise.

o

five

0

five

0

five

0 d

0

five

evenly distributed over time, the sum of the mismatch of the interference signals tends to a zero value, since the summation is performed taking into account the sign of the deviation.

Claims (1)

In this case, on the bus 11, the value of the HC mismatch, expressed in cycles, outputted in the additional code, extracted from the signals of the impulse noise, appears. Invention Formula The digital time discriminator containing the first N-bit and second counters, the bit accumulator, is different. In order to increase noise immunity, S is a controlled pulse generator, an NOT element, an N-1 block of 2I-OR elements, a delay block, a memory device, and a second counter on N-1 bits, with the input the controlled generator is connected to the input of the element NOT and to the first input bus, the output to the counting input of the first and second counters, the inputs of the initial installation of which are connected to the output of the element NOT, the first inputs of the first elements AND the block of elements 2I-OR are connected to the right output N-ro bit yes first count ik, the second inputs of the first elements AND with the direct outputs of the corresponding (N-1) X bits of the first counter, the first inputs of the second elements AND of the block of elements 2И-OR with the inverse output N of the first discharge of the first counter and the NM input of the first group the inputs of the one-bit adder, the second inputs of the second And elements - with the direct outputs of the corresponding (Nl) -x bits of the second counter, and the third inputs of all And elements are connected to the second input bus and the input of the delay block, the outputs of the OR elements of the 2I- element block IPI connect to the corresponding (M-1) -th inputs the first group of inputs of the bit adder, the outputs of which are connected respectively to the information inputs of the storage device, the input resolution of the record of which is connected to the output of the delay unit, and the outputs of the memory device are connected to the second group of inputs of the bit accumulator, and to the output bus. X. . four W and M i l M f / 0 Fiyo