SU1160562A1 - Forward-backward counter - Google Patents

Description

The invention relates to a pulse technique and can be used in the design of reversible counters, digital computing devices with a binary number system. , five

Known reversible pulse counter containing the input bus and P + 1 bits, each of which contains three ternary elements [1D.

The disadvantage of such a device 10 is a relatively low speed, since 1) +1 bit number with AND numeric discharges is formed during 207 + 1) phase of the clock supply.

Known reversible pulse counter, containing the input bus and H bits, each of which contains six ternary elements, the first summing input of the first ternary element is connected to the first 20 summing input of the second ternary element, the output of which is connected to the first and second subtractive inputs of the third ternary element and with the first summing input of the fourth and third ternary element, the first subtractive input of which is connected to the output of the first ternary element and with the first and second summing inputs of the third trio element, whose output is connected to the first summing inputs of the fifth and sixth ternary elements, the outputs of which are connected respectively to the first subtractive inputs of the first and second ternary elements, in each digit except the first, the first summing input of the first ternary element is connected to the output of the fourth ternary element the previous discharge-yes, the first summing input of the first ternary element of the first discharge is connected to the input bus; in each discharge, the outputs of the fifth and sixth ternary elements are connected in accordance with the second summing and subtracting inputs of the fourth ternary element, the output of which is connected to the second summing inputs of the fifth and sixth ternary elements {2}.

The well-known counter has a limited scope due to the use in it of an uncommon ternary number system and low reliability, since each digit contains sixteen inter-element connections.

"The purpose of the invention is to expand the scope by using a binary-symmetric code and increase the reliability of the counter.

This goal is achieved by the fact that in a reversible pulse counter containing the input bus and and discharges, each of which contains six ternary elements, the first summing input of the first ternary element is connected to the first summing input of the second ternary element, the output of which is connected to the first and second subtractive inputs the third ternary element and the first summing input of the fourth ternary element, the first subtractive input of which is connected to the output of the first ternary element and the first and the second summing mi inputs of the third ternary element, the output of which is connected to the first summing inputs of the fifth and sixth ternary elements, the outputs of which are connected respectively to the first subtractive inputs of the first and second ternary elements, in each category, except the first, the first summing input of the first ternary element is connected to the fourth output ternary element of the previous discharge, the first summing input of the first ternary element of the first discharge is connected to the input bus, in each discharge the first summing input of the first ternary element is connected to the second summing and subtracting inputs of the fourth ternary element.

FIG. 1 shows a diagram of a reverse two-digit pulse counter; in fig. 2 - timing diagram of the counter with the legend. '

The counter (Fig. 1) contains ternary elements 1-6 of the first discharge, ternary elements 7-12 of the second discharge, the input bus 13.

. The first summing inputs of the ternary elements 1 and 7 are connected respectively to the first summing inputs of the ternary elements 2 and 8, the outputs of which are connected to the first subtractive inputs of the ternary elements 3 and 9, to the second subtractive inputs of the ternary elements 3 and 9 and,. e the first summing inputs of elements 4 and 10, the first subtractive inputs of which are connected respectively 3 1160562 4

io with the outputs of ternary elements 1 and 7, with the first summing inputs of the ternary elements 3 and 9, and with the second summing inputs of the ternary elements 3 and 9, the outputs of which are connected to the first summing inputs of the ternary elements 5 and 11 and with the first the summing inputs of ternary elements 6 and 12, the outputs of which are connected respectively to the first subtractive inputs of the ternary elements 2 and 8; the outputs of the ternary elements 5 and 11 are connected, respectively, with the first subtractive inputs of the ternary. elements 1 and 7; input bus 13 15

connected to the first summing input of the ternary element 1 and to the second summing and subtracting inputs of the ternary element 4, the output of which is connected to the first summing input 20 of the ternary element 7 and to the second summing and subtractive inputs of the ternary element 10.

FIG. 2 denotes: time diagrams 14-16, respectively, of the first, second and third phases of the clock supply; timing diagram of 17 pulses on bus 13; timing diagram 1.8-29 pulses, respectively, at the outputs of the elements 1 - 12. 30

The system of clock power, the counter three-phase. A first phase clock pulse received positive and negative pulses on the bus 13, and element ₃₅ is read informatsiyas cops 5-8; clock pulses of the second and third phases, respectively, read information from the elements 1,2, 9, 10 and 3, 4, 11, 12.

Each subsequent discharge of the addendum ₄₀ (deductible) enters the bus 13 through three phases (one clock cycle) of transmitting information on the counter elements.

The counter is made on ternary elements that perform the operations described by the table. It should be noted that the first and second summing inputs (the first and second subtractive inputs) are equivalent to each other,

On elements 1 (7), 3 (9) and 5 (11), pulses of state “+1” are formed, and on elements 2 (8), 3 (9) and 6 (12) pulses of state “-1” of the first (second) a) discharge counter. At element 4 (10), a transfer pulse of the first (second) discharge is formed. It should be noted that the output of the element 10 is not used in the second (· · · ·)) discharge of the counter.

To represent the numbers in the meter, the binary number system is used with the numbers 1, 0, T, where the sign of the number is determined by the sign of the most significant digit.

The arrival of a positive impulse ("+1") * on the counting bus 13 adds a positive unit to the contents of the counter. The arrival of a negative impulse ("-1") adds a negative one. If the counter is in the zero · state, the first positive impulse sets it to the "+1" state, the second translates it to the "0" state, and passing through the transfer output (positive impulse from element 4) to the next (second) digit, sets it in the state of "+1", etc. Admission. negative pulses on the counting bus 13 causes a consecutive decrease of the positive number accumulated in it, and then after zero crossing, the accumulation of a negative number. The presence of feedback allows you to store the result of the addition ( Readings), i.e., provides storage of the state "+1" ("-1") of the counter discharge in the form of generation of pulses of positive (negative) polarity at its outputs. The state "+1" of the first (second) discharge of the counter is removed from the output of the element 5 (11), and the state "-1" - from the output of the element 6 (1 2).

To reset the counter, it is necessary to enter a zeroing bus connected ° to the second subtractive inputs of elements 5, 6, 11 and 12, when a pulse arrives at which the pulse of the state of the counter discharges is compensated, i.e. zeroing.

When recording a code of a certain number, it is necessary to enter an installation bus into each digit of the counter connected to the second summing inputs of the first and second ternary elements, to which the values of the digits of the record number are fed.

FIG. 2 shows a timing diagram for the case of direct counting · from Oad to 3 _1a (from 00g to 11 ^) and the counting back_pulses from 3 _4С) to - 3 ^

(from 11 to _Ζ ^ 1T).

The device works as follows.

.1160562

When the first pulse arrives on the counting bus 13, the clock pulse of the first phase of the first clock cycle, according to the logic of the element recorded in the table, is transmitted to the first summing input of the element 1 and the second summing input of the element 4; the pulse of the second phase positive pulse from element 1 is transmitted to the first summing input of element 3 and the second subtracting the input of element 4; the third phase pulse positive pulse from element 3 is transmitted to the first summing input element 5.

The pulse of the first phase of the second clock cycle positive pulse from element 5 is transmitted to the first subtractive input of element 1 and exits the counter, forming the first digit.

The resulting state of the outputs of the counter 01.

When the second pulse arrives on the bus 13 with a clock pulse of the first phase of the second cycle, a positive pulse is transmitted to the first summing input of element 1, the third phase pulse sends a positive pulse from element 4 to the first summing input of element 7 and the second summing input of element 10.

The positive impulse from element 7 is transmitted to the first summing input of element 9 and the first subtractive input of element 10 by the impulse of the first phase of the third cycle, the positive impulse from element 9 is transmitted to the first summing input of element 11 by the second phase pulse, and the positive impulse from element 11 goes out of the third phase counter, forming the second digit.

The resulting state of the outputs of the counter 10.

Upon receipt of subsequent pulses on the counting bus 13, the counter operates in a similar way.

The use of the proposed counter provides in comparison with the known extension of the scope by representing the numbers in the counter in the binary number system (in the well-known counter, a three-fold number system is used, which has a limited scope); increasing the reliability by simplifying each digit of the counter into two inter-element links (the counting discharge of the proposed counter has fourteen inter-element bonds, in the well-known sixteen inter-element bonds), and also due to the absence of the need to use the fourth ternary element with four inter-element bonds in the last discharge of the counter, on which the transfer is formed.

Number of pulses (± 1) entering the inputs condition output element Adders Subtractors 1.2 | 1.2 0 0 0 one one 0 2 2 0 0 1.2 -one one 2 -one 1.2 0 + 1 2 one + 1

1160562

1160562

K- '15

/ DJ Gamv Tact Tact? Takte Takai

444-11

— .——- ι 1-. >"-D /. / Y "" ?. ^'and

, ΙφιΓΊψ

Taktu

(D-4-4 — l iimscShZhZsh

II 1 I ι 1 II! And ¹ GT "'1 t ¹ Ί T ¹ 7 14 -) .. 14.1 14. P. ^ -1., C I Ι χ I I I and

Three-phase power supply impulses “X. record + g

write, rg -u read ,, -G — read „0 *

Read + G

Phi 2

Claims (1)

REVERSIBLE COUNTERS PULSES containing the input bus and η bits, each of which contains six, ternary elements, the first summing input of the first ternary element is connected to the first summing input of the second ternary element, the output of which is connected to the first and second subtractive inputs of the third ternary element and the first summing the input of the fourth ternary element, the first subtractive input of which is connected to the output of the first ternary element and the first and second · * · eye. summing inputs of the third ternary element, the output of which is connected to the first summing inputs of the fifth and sixth ternary elements, the outputs of which are connected respectively to the first subtractive inputs of the first and second ternary elements, in each digit except the first, the first summing input of the first threefold element is connected to the output the fourth ternary element of the previous discharge, the first summing input of the first ternary element of the first discharge is connected to the input bus, which differs 5 the fact that, in order to expand the scope> application and increase reliability in each digit, the first summing G is the input of the first ternary element connected to the second summing and calculating 2 melting inputs of the fourth ternary '* element. * about ^: SP Od N0 1 1160562 2