SU1383496A1 - Reversible pulse counter - Google Patents

Description

(21) 4146721 / 24-21

(22) 02,10.86

(46) 03/23/88, Büp. № 11

(72) S.I. Sharovatov

(53) 621.374.32 (088.8)

(56) USSR author's certificate

No. 945999, cl. H 03 K 23/00, 1980.

USSR Author's Certificate No. 1266000, cl. H 03 K 23/76, 1985.

(54) PEBEPCHBHbfli COUNTER COUNTERS (57) The invention can be used in the design of reversible digital computing devices with a binary number system. The purpose of the invention is to simplify the device. The counter contains countable bits (CP) 1-3. СР 1 has ternary elements (ТЭ) 4-14; CP 2 - TE 15-20, and CP 3 - TE 21-26. The invention makes it possible to reduce the amount of FC in the meter. 2 ill., 1 tab.

00

00

Od

with O5

The invention relates to a pulsed technology and can be used in the design of reversible digital computing devices with a binary number system.

The aim of the invention is to simplify the reversible pulse counter.

The goal is achieved by reducing by one ternary element the number of ternary elements of the first counting bit and introducing new design features.

FIG. 1 shows a diagram of a three-bit reverse counter im13834962

element 12 (18) is connected to the positive folding input of element 15 (21), the negative folding

g input element 16 (22) and the second positive folding and negative subtractive inputs of the element 18 (24). The output of element 13 (14, 19, 20, 25, 26) is connected to positive

10 subtractive input element 8 (9, 15, 16, 21, 22).

FIG. 2 denotes: time diagrams 29-31 of the first to third phases of the clock supply, time diagrams 15 and 32 and 33, respectively, of pulses

pulses; in fig. 2 - time diagram of the three-bit reversible pulse counter operation. |. The reversing pulse counter contains countable bits 1-3. The countable bit 1 contains the first - eleventh elements 4-14, the countable bit 2 contains the first - sixth ternary elements 15-20, the countable bit 3 I contains the first - sixth ternary I elements 21-26, the input buses 27 and 2.8 | Bus 27 is connected to the positive folding input of the element 4, the negative folding and the input of the element 5 and the second positive folding and negative subtractive inputs of the element 7. The bus 28 is connected to the positive subtractive input of the element 4 and the negative subtractive input of the element 5, The output of the element 4 (8, 15, 21) connect n with positive and negative folding inputs of element 6 (11, 17; 23) and positive subtractive input of element 7 (12, 18, 24). The output of element 5 (9, 16, 22) is connected to the positive and negative subtractive inputs of element 6 (11, 17, 23) and the first positive folding input of element 7 (12, 18, 24). The output of element 6 is connected to the positive folding input of element 8, the negative subtractive input of element 9 and the first positive folding and first negative subtractive inputs of element 10. The output of element 7 (10) is connected to the second positive folding and second negative subtractive inputs of element 10 (12). The output of element 11 (17, 23) is connected to the positive folding input of element 13 (19, 25) and the negative folding input of element 14 (20, 26). Output

on tires 27 and 28; timing diagrams 34-56, respectively, of the write and read pulses on elements 4-26.

The system of clock supply of the counter is three-phase. The clock pulse of the first phase receives positive and negative pulses on buses 27 and 28, and also information is read.

from the elements 8, 9, 10, 17, 18, 25 and 26J clock pulses of the second and third phases the information is read from the elements 4, 5, 11, 12, 19, 20, 21, 22 and 6, 7, 13, 14,

15, 16, 23, 24. The pulses arrive at wards 27 and 28 after periods of time that are multiples of three clock phases, power.

The counter is implemented on ternary

elements that perform operations described by the table, and are implemented, for example, on magnetic logic. the cells The folding inputs are equivalent to the subtracting inputs except for the sign of the output pulse, the counterpoint is opposite, and the first and second folding (subtractive) inputs are equivalent to each other.

 On elements 13 (14), 19 (20) and 25 (26), positive pulses form the +1 (-1) state of the counter, respectively, of the first, second, and third bits 1–3. On the elements

12 and 18 transfer pulses are generated for the first and second bits 1 and. 2 respectively.

A binary system is used to represent the numbers in the counter.

Numbers with numbers 1, 0.1, where

the sign of the number is determined by the sign of the most significant bit.

The arrival of a positive impulse (+1) on bus 27 or 28 adds a positive unit to the contents of the counter, the arrival of a negative impulse (-1) adds a negative unit, with tires 27 and 28 being equivalent. If the counter is in the zero state, the first positive pulse arriving at one of the input buses sets its first bit 1 to state +1, the second positive pulse converts the first bit 1 to state O, and passed with a positive pulse The & transfer output (item 12) of the first bit 1 into the next second bit 2 sets it to state +1. The arrival of negative pulses on one of the input lines 27 or 28 results in a successive decrease (decrease) in the accumulated number, and after zero crossing, a negative number accumulates. The simultaneous arrival of different polarity pulses on the buses 27 and 28 does not change the state of the countable bits, since these pulses compensate each other on elements 4-7. The simultaneous arrival of two positive (negative) pulses does not change the state of the first discharge, but leads to the appearance of a positive (negative) transfer pulse at the output of element 12 entering the next (second) discharge 2. The presence of feedback in a countable bit, it allows to store the result of addition and subtraction, i.e. provides storage of the states --1 and -1 in the form of generation of positive pulses on its inputs.

To set the counter to the zero state, it is necessary to enter into the CS1 every counting bit (1-3) a bus connected to the subtractive inputs of the elements (13, 14, 19, 20 and 25, 26) that do not have subtract inputs. The arrival of one or several pulses on this bus will compensate for the discharge state pulse, i.e. it is set to state O.

To write any code, it is necessary to enter into each computational bit (1-; 3) an installation bus connected to the second folding inputs of the elements (13, 14, 19, 20, 25, 26) that do not have subtracting inputs. Values of bits of the code to be written are applied to the indicated lengths.

FIG. 2 shows a timing diagram for the counting of impulses arriving at the bus:

+1, +1, +1, -1, -1, -1 - on the bus 27;

O, +1, +1, -1, -1, -1 - on the bus 28

When a positive pulse arrives on the bus 27 for the time of the clock pulse of the first phase of the first cycle, according to the logic of the element recorded in the table, the positive folding input of the element 4 and the second positive folding input of the element 7 are recorded; The second-phase clock pulse positive pulse from element 4 is transmitted to the positive folding input of element 6 and the positive high. the reading input of element 7, the third phase clock pulse, the positive pulse from element 6 is transmitted to the positive folding inputs of elements 8 and 10. The clock pulse from the first phase of the second cycle is positive pulses from elements 8 and 10 are transmitted respectively to the positive folding input of element 11, the positive subtracting input of the element 12 and the second positive folding input element 12; the second-phase clock pulse of the positive pulse from element 11 is transmitted to the positive folding input of element 13; a third phase clock pulse from element 13 reads a positive pulse. The resulting status of the outputs of the three-bit counter 001.

When entering on the second - the sixth cycles of subsequent pulses on the bus 27 and 28, the counter operates in a similar way.

Thus, in comparison with the known, the proposed technical solution is simplified. It reduces the number of ternary elements and inter-element links, while preserving the health, functionality and basic technical characteristics.

Claims (1)

Invention Formula The reverse pulse counter containing the first and second input buses and counting bits, each of which contains the first, second, three first, fourth, fifth and sixth ternary elements, the first bit additionally contains the seventh, eighth, ninth, tenth and eleven ternary elements, in each countable bit the output of the first threefold element is connected to the positive and negative folding inputs of the third and positive by the subtractive Echo of the fourth ternary elements, the move of the second ternary element is co | n, inn with positive and negative; The subtractive inputs of the third and the first positive folding input are even: the right ternary elements, The third ternary element is connected to the positive folding input of the fifth and the negative folding input of the sixth ternary elements, the positive folding input of the first, the negative folding input of the second and the second positive folding and the negative calculating input; the thawing inputs of the fourth three-dimensional elements are interconnected in the first counting bit) the first input bus is connected to the positive folding input of the first ternary element, the second input bus is from; the positive subtractive input of the first 1 The first and second negative ternary elements are input, the first output of that ternary element is connected to the positive folding input of the eighth and the positive subtractive input of the ninth ternary element, the output of the sixth threefold element is from the positive subtractive input of the eighth and the first positive folding input of the nine third ternary elements, the output of the eighth ternary element - with the positive folding input of the tenth and negative folding input of the eleventh ternary elements, rows which are respectively connected with positive subtracting input of said fifth and sixth ternary elements, a second folding Positive and negative inputs of the subtracting ninth ternary element connected between sobo minutes, yield nine tog ternary element is connected to the positive input of the first folding of the third ternary element of the second countable bit, in each countable bit, except the first one, the outputs of the fifth and sixth ternary elements are respectively connected with the positive subtractive inputs of the first and second ternary elements, and the output of the fourth ternary element is connected with the positive folding input of the first threefold element of the next of a countable bit, of which is the fact that, for the purpose of simplification, in the first counting bit, the output of the third ternary element is connected to the first positive and folding and negative the second subtractive inputs of the seventh ternary element, the second positive folding and the negative subtractive input of which are connected to the output of the fourth ternary element, the output of the seventh ternary element is connected to the negative subtractive input of the ninth ternary element, the outputs of the fifth and sixth threefold elements are connected respectively to negative folding and subtractive inputs of the eighth ternary element. F / 7g n Tant impulses -5-- record; f1 ealisd „-1 - CvufTTb / Saffue-f - Cvumb / SoHue p C fumbfSaHc e i . 2