SU1411993A1 - Device for determining logarithmic error factor in discrete communication channel - Google Patents

Abstract

The invention relates to communication technology. The purpose of the invention is to improve the accuracy and reduce the time of determination. The essence of the device operation. It is based on the fact that in it, by 2 counting blocks (CB) 1 and 2, a separate counting of the number of test signals and the number of errors recorded in these signals is carried out. Both SB 1 and 2 are counted in logarithmic. shkale SB 1 captures the current value of the logarithm of the number of signals in the test

Description

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sequence, and SAT 2 - the current value of the logarithm of the number of errors. SB 3 fixes the current value of the difference of these logarithms, equal to the logarithm of the ratio of the number of erroneously received premises to the total number of feeds (logarithmic coefficient, errors). Device

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The invention relates to communication technology and can be used to determine the characteristics of discrete communication channels.

The purpose of the invention is to increase the accuracy and reduce the time of determination.

Fig. 1 shows a block diagram of a device for determining the logarithmic error rate of a discrete communication channel; Fig. 2 is a diagram illustrating the operation of the counting blocks; FIG. 3 is a diagram of input pulse sequences.

A device for determining the logarithmic error rate of a discrete communication channel contains counting blocks 1-3, the first counter 4, consisting of triggers 5, -5 ,. , Elements 6d-6c, second counter 7, included in the first counting unit 1, identical to counting unit 2, the first reversing counter 8, consisting of flip-flops 9, -9, the first transfer chain of successively connected alternating elements And and, elements OR. , the second transfer chain from the series-connected alternating elements 1Л 12 -12 and the elements OR 13 (, -13 c., the second reversible counter 14, included in the third counting unit 3, and the multiplier 15

The device works as follows

In the proposed device, two counting blocks 1 and 2 are kept separate counting the number of test signals and the number of errors recorded in these signals. At the same time, both counting blocks 1 and 2 count in a logarithmic scale.

determines the binary logarithm of the error. To determine the logarithm of the base, ten this value must be multiplied by the coefficient Ig 2 0.3o. This is realized in block 15 multiplication by a constant number I tabLo. 3 or LO

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The first counting block 1 fixes the current value of the logarithm of the number of signals in the test sequence, and the second one fixes the current value of the logarithm of the number of errors. .

Assume that counter 7 is pro-; leads to the fixation of the pulses arriving at it in the binary code, and the outputs 7o + 7 are formed by the decoder, so the position 7 designates the combination of the binary counter - the decoder However, this construction is not necessary. Counter 7 can be built, for example, in the complete ring distributor (closed shift register with the unit circulating in it). In this case, the decoder is not required.

Counting unit 1 provides the counting of pulses arriving at it in such a way that it logs the logarithm of the number of incoming pulses. Counter 4 formed by triggers, fixes the fractional part of the logarithm (mantissa). Each of the triggers 5 has a binary weight corresponding to its index. Unit in the trigger 5 corresponds to the number 12 recorded in the counter 4. The single state of the trigger 5j corresponds to records 1-2 and the second counter 7 ensures the fixation of the integer part of the logarithm (characteristic).

In the initial state, the signals on the inputs S of all the triggers and the counter 7 in the entire counting unit 1 establish the largest number.

those. all triggers are in a single state, and counter 7 contains the maximum number. The initial setup pulse is applied to the inputs S of all device triggers using a common bus (not shown). As a result, the output 1 of the counter 7 has a single signal, and the remaining outputs have zero signals. Edivode

is open

And 6ts, with 5 steel elements

with a single signal with

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And 6 are closed.

The third counting unit 3 also consists of two reversible counters, I one of which (reversing counter 14) records the characteristic of the logarithm, and the other one reversing counter 8 on the flip-flops 9, -9k) - the mantissa. The counting unit 3 in the initial state of the scientific research institute is established in the same way; in the filling state

Suppose initially that. impulses are received only at the input of the first counting unit 1 (clock pulses). The first pulse through the open element And 6c falls on the least significant bit (trigger 5) and on the input of the third counting block 3. Since both counters are in the filled state, the incoming first pulse overflows them, and both counters are reset to zero state the Since the zero number in the counter 7 of the integer part appears, the output 7 o is excited, the excitation corresponding to this number from the output 7 is removed. Therefore, the element AND 6p is opened, and the element 6 is closed. The remaining elements And 6 remain closed.

The second clock pulse through the open element 6) hits the inputs of counters 7 and 14 of the integer part (characteristics) and writes a unit to them. In both counters, thus, the number is set to 01,000 (the lower bits are written to the right). Now in counter 7 is fixed one, and

excitement goes from output 7d to output 7 ,. Element AND 6o is closed, and Element 6 opens.

The third pulse through the element And 6 translates the triggers 5, and 9 into one state. In counting blocks 1 and 3, the number 01 is fixed; 100 1 +

one

+ ---. The integer part of the number does not change, therefore, excited

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and the element 6. It turns out the output is red.

The fourth pulse through the element And 6, again falls to the input of the trigger 5,

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x-o counters In counting blocks 1 and 3, the number 10 is fixed. The contents of the counter 7 change, output 1 is excited. And the element opens. And 6,: The counting of pulses is performed, starting from the triggers 5, and 9 ", having a weight

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; the incoming pulse adds a value of -7 to the contents of the counters.

until the change of the integer part.

The table shows the pulse counting process.

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The diagram (Fig. 2) shows the sequence of numbers written in the counting blocks 1 and 3 depending on the number of incoming pulses (dashed line) and the exact dependence of X. The counters (Fig. 2) implement; 1 is the basic interpolation of the logarithmic dependence with the nodes at the points 2 (t O, I, ...).

If we assume that the pulses arrive only at the input of blocks 2

514

(pulse error), and on. the input of the counting unit 1 does not arrive, then the processes occurring in the counting unit 2 coincide with those indicated for the counting unit K, As for the counting unit 3, since in the initial state it is filled, and the signals from the counting unit 2 arrive at the counting unit 3 to the subtraction signal transfer circuit, the number complementary to the binary logarithm of the number of pulses is fixed in it. Otherwise, as is the case in the reversible counter, the counting unit 3 is negatively fixed. The value of the number written in it in the additional code (e If there is a sign bit, then taking into account the sign).

Suppose now that the sequence of pulses arrives at both inputs (Fig. 3). The input of the counting unit 1 receives a clock sequence (fig.Za), each pulse of which corresponds to one character of the test sequence passed through the channel under study, and to the input of the counting block 2 - pulses (Fig. 36), each of which corresponds to one error found in the received sequence The first sequence is periodic with a period T, where T is the duration of the character of the test sequence. The second sequence is quasi-periodic, since its pulses appear randomly, but not necessarily at times that are multiples of T + A T, where D T is the phase shift introduced in order to eliminate the addition of subtracting and subtracting pulses.

Pulses of the first sequence (clock) give it a logarithmic growth of numbers written in the counting blocks 1 and 3. The pulses of the second sequence (errors) give a logarithmic growth in the counting block 2, and in the counting block 3 - a negative logarithmic growth, because the signals from the counting unit 2 enters the signal transfer circuit of the subtraction of the counting unit 3.

Therefore, in the counting unit 3, the current value of the binary logarithm of the number of clock pulses is simultaneously recorded and the current value of the binary logarithm of the number of error pulses s is subtracted from it.

the hararms equals the logarithm of the pulse number ratio in both sequences. Therefore, if by the time i-t is received n characters of the test sequence and in K of them errors are fixed, then in the counting block 3 the number

Sftlog n - log, - | -

,

where p is the estimate of the probability of an error in the communication channel

Moreover, since the error probability p is a quantity less than one, its logarithm is negative, and S is positive.

The proposed device determines the binary logarithm of the error probability. If it is necessary to determine the logarithm of the base ten, this value must be multiplied by the coefficient Ig 2 0.3, which is realized in block 15 multiplication by a constant number (if necessary).

Claims (1)

Invention Formula A device for determining the logarithmic error rate of a discrete communication channel, containing two counting blocks, the input of the first of which is the input of a sequence of clock pulses, and the input of the second is the input of a sequence of pulses of abnormal errors, in order to improve the accuracy and reduction of time is determined, the third counting block is entered, the first and second counting blocks are identical and contain each serially connected first counter and second counter, The common outputs of which, through the corresponding elements And, the second inputs of which are interconnected and are the input of the corresponding counting block, are connected to the bit inputs of the first counter and to the auxiliary input of the second counter, the third counting block is made in the form of two reversible counters and two identical transfer chains consisting of sequentially connected alternating elements AND and OR elements, with the first bitwise inputs and outputs 714 the first reversible counter is connected respectively to the first and second inputs of the elements AND of the first transfer chain, the output of the last element OR of which is connected to the fold input of the second reversible counter, the second peripheral inputs and outputs of the first reversible counter are connected respectively to the first and second inputs of the elements And the second transfer chain , the output of the last element OR of which is connected to the input of the subtraction of the second reversible counter, each bit input, except for the first, first counter of the first account X 1 g 3 5 6 7 6 3 Ю 1Г 1Z 73 14 15 1В п T Figg but 38 The first block of the first counter of the first counting block, the first input of the first element AND of which is connected to the first random input of the first counter of the first counting unit, each parallel input, except the first, first counter of the second counting unit, is connected to the second the input of the corresponding element OR of the second transfer chain of the third counting block; the first input of the first element AND of which is connected to the first bit input of the first counter of the second counting block. l Fig.Z