SU762009A1 - Moving average computing apparatus - Google Patents

Description

The invention relates to computing and can be used to determine the moving average in digital information processing devices, digital measuring devices and other devices.

A device for the statistical processing of the results measured | θ rhenium from moving sample, comprising an input device, a switch, a delay circuit ^1, guardian information counters, which number is equal to the sample volume Ν, N AND circuits' through ^ko_ g torye produced code reading ¹⁵ from the information keepers

N circuits AND, through which the code is recorded from the input to the information storage counters, pulse generator, reversible counter [1]. hee

The device works as follows.

During the first N ticks, the values of the input code are written into the sequential25 in the information-keepers of information and at the same time they are summed up in the re (versatile counter. Algorithm of further work (after filling in all the information-keeping counters) opi-30

It is written in the following difference equation: y (ί, TU =

Y T (! - 1) t] x [(ΐ-N) T]

+ X (1, T) (1)

where y (1, T) is the value of the output code of the reversible counter at the moment of time I, T;

y βΐ — 1) t) is the value of the output code of the reversible counter at time (1-1) T, equal to the sum of the values of the input code at time (ΐ — Ν) τ, (— Ν +

+ 1) Τ, (I — Ν + 2) Τ .....

(1-1) Τ;

• χ (1, Τ) - the value of the input code at time 1 ₍ T,

N is the sample size,

1 «« N + 1, Ν + 2, .. · ί T is the sampling interval.

The disadvantages of the above device is the large amount of memory required and low speed.

The closest technical

the essence of the proposed is a device for determining the sliding

a medium containing an input block, four keys, a trigger, two elements OR,

3

762009

four

pulse generator, difference counter, counter-divider, group of keys, reversible average counter, which by its principle of operation is a recursive digital filter with only two memory elements. The current value of the input code is stored in the input block, and the previous value of the output code is stored in the reversible average counter.

The device works as follows.

In each clock cycle, the code value from the output of the reversible counter is written to the difference counter. Then this number is added to the number of pulses equal to the value of the input code. These pulses are fed to the input of the difference counter from the input block. The resulting difference is divided by the delimiter counter into the sample size and the result of the division, taking into account the sign, is summed up by the contents of the reversible counter. The output code of the reversible counter is the output code of the filter £ 2].

The disadvantages of this device is the low speed associated with the execution of computational operations in the number of pulse codes, and a large error in the performance of the division operation using a counter-divider due to rounding off the private without taking into account the discarded part of the code.

The purpose of the invention to increase speed and reduce the error of the operation of division.

This goal is achieved by the fact that in the known device containing a clock frequency generator, the first and second registers, the input of the first register being the input of the device, two adders are entered, while the output of the second register is connected to the first input of the first adder, output η most significant bits of the second register connected to the second input of the first adder, the output of the second transfer is connected to the output of the (n + 1) -th digit of the second register, the clock input of which is combined with the clock input of the first register and connected to the output of the generator Ora clock frequency, the output of the first register is connected to the first input of the second adder, the output of which is the output of the device and connected to the input of the second register, and the output of the first adder is connected to the second input of the first adder. The performance increase is achieved by using combinational logic adders, replacing the division operation with the equivalent code shift operation and performing all computational operations on parallel codes. To reduce the error of the execution of the division operation, rounding of the private one is carried out taking into account the dropped part of the code, for which

the return code (n + 1) -th digit (counting from the senior digit), the second memory register from the third output of the second memory register is fed to the transfer input of the first adder.

The drawing shows a functional diagram of the device.

The device contains a generator 1 clock frequency, the first register 2 (memory of the current value of the input code), the second register 3 (memory of the previous value of the output code), the first adder 4, the second adder 5, the output 6 of the clock generator, input 7 of the device, the output 8 of the first memory register, the first output 9, the second memory register, the second output 10 of the second memory register, the third output 11 of the second memory register, the output 12 of the first adder, the output 13 of the second adder. Memory register 2 has a bit width η and is intended for sampling and storing the current value of the parallel p-bit binary input code input to input 7. The parallel code from output 8® of memory register 2 is fed to the second input of binary combinational logic adder 5 having word width η + k, where k is the binary logarithm of the sample size. Register 3 of the memory capacity of η + k is intended for sampling and storing the previous value of the parallel output code of the device arriving at the information input of the memory register 3 ′ from output 13 of the adder 5. The control inputs of memory registers 2 and 3 are connected to the output 6 of the clock generator. A parallel direct (n + k) -bit binary code from the first output 9 of register 3 memory is supplied to the first input of a binary combination logic adder 4 having a capacity of η + k. The second input of the adder 4 from output 10 of register 3 memory receives a parallel reverse the new binary code is the high bits of memory register 3. Reverse code (n +

+ 1) -th digit register 3 memory from the output 11 of the register is fed to the transfer input of the adder 4. Parallel binary code from the output 12 of the adder 4 is fed to the first input of the adder 5. The output 13 of the adder 5 is the output of the device.

The algorithm of the device is described by a difference equation.

Do (rt) = SITI? G? TC <-1) T] ⁺ (2,)

where y £ (| -1) t], y (!, T) are the values of the output device code, respectively, at time instants (ϊ — 1) T and 1T;

χ (ΐΤ) is the value of the input code at the moment of time ί, · T;

! - moment number

(ί - 1, 2, ...);

762009 ·

T - sampling interval; 1 N - sample size.

The device works as follows.

At the moment of time And from the output 6 of the generator 1 of clock pulses, the recording control signal is applied to the control inputs of memory registers 2 and 3. This signal is used to record the current value of the input code χ (ι'реги) in register 2 of memory and the previous value of the output code of [(| -1) T] in register 3 of memory. The values of the codes at the output 8 of the register 2 memory and at the output 9 of the register 3 memory are set respectively to .. χ (и) and y [. ("- 1) t]. In order to improve device performance and ^e facilitate operation dividing the previous value of the output code on sample size (. See formula 2) the sample size N is selected equal to 20

N = 2 ^Κ, (3)

where k is a positive integer.

When condition (3) is satisfied, the division operation is binary; code for [(ί- 1) t] 25

by N is equivalent to dropping to the lower bits of the code. To reduce the rounding error, the value of the remaining part of the code is summed with the value of the most significant digit of the discarded part of the code. The subtraction operation for ί (ΐ ~ 1) T] is implemented

with the help of adder 4 by adding the code decreasing y [(ϊ -,) t] with the additional code deductible y (((ί —1) T], 35 The latter is true only for positive input numbers χ (, t), because this is true inequality _l

at [(ϊ-1) T]> / - ^ - at G (ΐ —1) t] 40

and nonnegative difference y [(ϊ -1) T] ~ y [(Ϊ -1) t]

will be expressed in direct binary code 45 d.

Thus, the proposed device has a higher accuracy, the rounding of the private with regard to the discarded part allows the mean-square value of the error of the division operation to be reduced compared to the known two times. In this case, the systematic component of the error of the division operation in the proposed device is equal to "O", and in the known half of the unit of the lower order code. The proposed device also has a simpler structure than the known one.

Claims (1)

Claim A device for calculating the moving average, containing a clock frequency generator, the first and second registers, and the input of the first register is the device input, which is due to the fact that, in order to increase speed and accuracy, two adders are entered into it, while the output of the second the register is connected to the first input of the first adder, the high-order output η of the second register is connected to the second input of the first adder, to the transfer input of which the output n + 1 of the second register is connected, the input of which ene with a clock input of the first register and is connected to the output of the clock generator, the first register output connected to a first input of a second adder whose output is an output device and is connected to the input of the second register and the output of the first adder is connected to the second input of the second adder.