SU728126A1 - Exponential function computing arrangement - Google Patents

Description

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This invention relates to the field of computing.

A device for calculating an ex function is known that contains a long-term memory device for storing the values of functions 1.

The closest technical solution to this invention is a device (2 for calculating exponential functions containing an argument register, an accumulator consisting of n shift registers, a multiplication unit, an AND element and an utterance block, the first output of which is through with the first input of the multiplication unit and the first input of the control unit, the second output is connected to the second input of the multiplication unit, the third output of the control unit is connected to the input of the shift register registers, information The ion inputs of which are connected to information devices of the device (21. In addition, this device contains a decoder. The disadvantages of the known devices are complexity, and low computational accuracy.

The aim of the invention is to improve the accuracy of calculations.

The goal is achieved in that the device contains n elements AND and a data selection block, the first and second inputs of which are connected respectively to the array of the argument register and the fourth output of the control unit, and the bit outputs of the shift registers are connected to the first inputs of the AND elements and through the information sampling block inputs of the multiplication unit, repeat the inputs of the AND elements connected to the fifth output of the control unit, as well as the fact that the information selection block contains n AND elements, the first inputs of which are connected to the first input of the block and vys Borky informatio n, the latter - to the data inputs of the block, and the outputs of the elements and connected to the output selection unit ki; in addition, the block of information retrieval contains elements AND, a multi-input element

0 OR and the switch, the information inputs of which through the elements AND and OR are connected to the output of the information selection block, the second inputs of the elements AND are connected to the first input

SSS home block sampling information, the second input is connected to the input of the switch. The drawing shows the proposed device. It contains the argument register 1, the information selection block 2, the drive 3, the group of n elements AND 4, the control unit 5, the multiplication unit 6 and the element 7. The operation principle of the device is as follows. If you need to specify a, where ... ... + “2 ° + a 2 + - +“, and I. 11 - we can write it down. Depending on the given diatzone, the change of the argument X and the accuracy of the calculation, the number of bits for recording the integer part k and the fractional part m can be different (). To calculate the value of the exponential function N for a given basis and argument X, it is necessary to multiply all values (2j-Beca of all bits of the argument, the value of which is logical 1. At 0101, 1001 (.; NQ о.аЧа ° -. "A- ,, -1 aa aa a-, and In accumulator 3, prior to the commencement of the calculation, codes of numbers about 1 ...,, ..., and .v are written; At the same time, macrogissa and orders are stored in accumulator 5 THESE codes / Multiplication unit 6 processes numbers written with a floating point, this is caused by the fact that the values of the power functions change rapidly. At the beginning of the calculation from the control unit 5 the multiplication unit 6 is written down a code equal to one. This is necessary so that when the multiplication unit receives a code 6 (2 is the weight of the first of the digits under study, the value of which is equal to logical 1) when multiplied, the code is equal to zero The device can work by starting the calculation from any bit of the argument, while the information in the drive should be written into the sequence in which the study of the bits of the argument is used. For simplicity, consider the operation of the device if the study starts with either a low-order or high-order argument. After the i-1 clock has been executed, the output of the 8 register of the argument is the value of the discharge with weight i, if i k, or the discharge with weight. 2 () if i k, provided that the operation of the device starts with the highest bit of the argument. If the computational device starts with the low-order bit, then at the output of the 8th register register the argument is the value of the bit with a weight of 2- (1-0, with i m or 2 with i, provided that the value of the bit being examined

Claims (1)

728126 is equal to logical 1, the block of assembly-information 2 is opened. The value of this bit enters the multiply signal bus in control blocks 5 and multiplication 6. The code corresponding to this discharge is output from the accumulator through an open circuit of information block 2 post). It goes into multiplication unit 6, where it is multiplied by the code contained in it . Upon completion of the multiplication operation, the control unit 5 generates a signal which, via the bus signal of the shift of the argument register information and through the bus of the control signal, is transferred respectively to the register of argument 1, where the information in it is shifted by one bit towards the output 8 of the register of the argument, and chain of information sampling 2, where the selection of the iQwmero code is prepared. If the value of the bit being examined is equal to logical O, then the sampling circuit of informant 2 remains closed. On the multiply signal bus, this value enters the control unit 5. The control unit 5 immediately generates shift and control signals. According to these signals, similar processes occur as in the case when the value of the bit is equal to logical 1. In order for the drive to have the necessary code, it is necessary to shift the information in the registers of the drive. On the bus of the information signal of the accumulator, the control unit 5 receives signals that are controlled by the control unit. With a shift, information from the accumulator outputs of the prohibition circuit 4, which is open, arrives at the inputs of the accumulator and is rewritten. After examining the values of all n bits of the argument code X, the output of the element M 7 is a single signal. It enters the signal bus at the end of the operation into multiplication unit 6 and control unit 5. The signal end of operation means that in multiplication unit 6 there is the calculation result. To calculate the values of power functions with another basis, for example, it is necessary to replace the information in drive 3. The replacement is performed by feeding the inputs of the drive ch2 code "a.} - 1, ... b, b the control unit 5, as well as the bus offset signal of the storage information shift signal bus. The blocking signal closes prohibition patterns 4 and no rewriting of information from the outputs of the accumulator to the inputs of the accumulator is not performed. Claim 1. Device for calculating exponential functions, containing the register of the argument, the accumulator consisting of n shifted d