RU2610012C1 - System of innovation project personnel formation - Google Patents

Abstract

FIELD: information technology.

SUBSTANCE: method is performed by allocating performed functions by an automated system, comprising a start input 1, a clock generator 2, an adder unit 3, a comparison circuit 4, the first AND gate 5, an output device 6, group of n-counters 7₁, 7₂,…, 7_n, result reddiness trigger 8, a group of n decoders 9₁, …, 9_n, a group of outputs 10, adder 3 outputs are connected to the inputs of the first group of comparison circuits 4, transfer output of the n-th counter 7n is connected to a single input result readiness trigger 8. The outputs of i-th memory unit 19i are connected to the respective inputs of the i-th decoder 9_i, Included in the group of decoders 9₁,…,9_n, i=1, …n, and to the information inputs from the result storage unit 11, j--th output of i-th decoder 9i connected to the i-th input of j-th element OR 13j, Included in the group of elements OR 13₁,…,13_k, outputs of OR 13₁,…, 13_k, i=1, …, n, j=1,…, k, connected to the inputs of the adder 3, the outputs of the counter 17 are connected to the output 10, belonging to the group, and with address inputs of result storage unit 11 for executable performer function allocation.

EFFECT: broader functional capabilities.

1 dwg, 4 tbl

Description

The invention relates to systems and methods for project management, management and distribution of human resources in projects and is intended to form a variety of options for building a project team, for a given description of the applicants' functional capabilities and the distribution of functions (work) between members of the project team.

A well-known system of rational allocation of resources (RU No. 2375750 C1, IPC G06Q 10/00, announced March 27, 2008, published December 10, 2009), contains in the input block of the task for the system at the first moment of time a device for managing rational allocation and analysis of resource allocation under given conditions, cell criterial assessment analysis of the rational distribution of resources, cell fixing the planned amount of work performed, cell fixing the actual value of work performed, cell fixing the amount of work performed, cell the rational allocation of resources of the technical component, the cell of the rational distribution of work, the cell of the rational distribution of resources of the organizational component, and in the input block of the task for the system at the second moment of time - the cell for fixing the planned amount of work performed, the cell for fixing the actual amount of work performed, the redistribution of resources during the work , a cell for fixing works provided with resources, a cell for checking the exhaustion of resources.

A disadvantage of the known system is limited functionality, because it distributes resources according to time costs and does not allow to form a project team out of many applicants.

The reasons that impede the achievement of the technical result indicated below include the lack of funds to ensure the selection of applicants to the project team.

A device is known for solving the assignment problem (RU No. 2439687 C1, IPC G06F 17/50, announced June 1, 2010, published January 10, 2012), containing a clock generator 1, a group of n counters 4 ₁ , 4 ₂ , ..., 4 _n , a group of n decoders 5 ₁ , 5 ₂ , ..., 5 _n , a group of n * n first registers 6 ₁₁ , ..., 6 _nn , a group of n * n blocks of elements And 7 ₁₁ , ..., 7 _nn , element And 10 , adder 11, comparison circuit 12, a group of n second registers 13 ₁ , 13 ₂ , ..., 13 _n , a third register 14, a start input of a device 15, a first output of a device 17, a second output of a device 18, a group of n third outputs of a device 19 ₁ , 19 ₂ , ..., 19 _n .

A disadvantage of the known device is limited functionality, because it solves the task of appointing executors to carry out each work from the many already formed project teams

The reasons that impede the achievement of the technical result indicated below include the lack of funds to ensure the selection of applicants to the project team.

The closest in technical essence to the claimed system is a device for solving the assignment problem (RU No. 2511412 C1, IPC G06F 17/00, G06Q 10/06, announced December 24, 2012, published April 10, 2014), containing start input 1, clock generator pulses 2, adder 3, comparison circuit 4, the first element And 5, the output of the device 6, a group of n counters 7 ₁ , 7 ₂ , ..., 7 _n , a readiness trigger for result 8, a group of n decoders 9 ₁ , ..., 9 _n , group of outputs 10, and the outputs of the adder 3 are connected to the first group of inputs of the comparison circuit 4, the output of which is connected to the first input of the first element And 5, the transfer output of the i-th counter 7 _{i is} connected to the counting input of the (i + 1) -th counter 7 _{i + 1} , i = 1, ..., n-1, the transfer output of the nth counter 7 _{n is} connected to a single input trigger readiness result 8, the output of which is connected to the output of the device 6.

A disadvantage of the known device is limited functionality, because it distributes resources among the formed project teams, on the principle of one person - one job, and does not consider the possibility of selecting applicants for the project team, building options for building a project team for a possible redistribution of functions.

The reasons that impede the achievement of the technical result indicated below include the lack of funds to ensure the selection of applicants to the project team and the construction of options for building the project team for a possible redistribution of functions.

The objective of the invention is to expand the functionality of the system for the formation of the personnel of an innovative project: the formation of a variety of applicants options for building a project team in which one executor performs one function, and the distribution of functions between members of the project team.

This is achieved by the fact that, in contrast to the known technical solution in the personnel composition formation system of an innovative project containing a start input 1, a clock pulse generator 2, an adder 3, a comparison circuit 4, the first element And 5, the output of the device 6, a group of n counters 7 ₁ , 7 ₂ , ..., 7 _n , readiness trigger for result 8, a group of n decoders 9 ₁ , ..., 9 _n , a group of outputs 10, and the outputs of the adder 3 connected to the first group of inputs of the comparison circuit 4, the output of which is connected to the first input the first element And 5, the transfer output of the i-th counter 7 _i connected to the counting input of the (i + 1) -th counter i = 1, ..., n-1, the transfer output of the nth counter 7 _{n is} connected to a single input of the ready trigger of result 8, the output of which is connected to the output of device 6, an additional block is introduced storing the result 11, element NOT 12, a group of k elements OR 13 ₁ , ..., 13 _k , inputs to specify the number of functions 14, delay elements 15 and 16, counter 17, the second element And 18, a group of n memory blocks 19 ₁ , ... , 19 _n, and the start input 1 is connected to a first input of the second AND gate 18, output clock generator 2 is connected to a second input orogo AND gate 18, readiness latch output result 8 is connected through an element NOT 12 to the third input of the second AND gate 18, the output of the second AND gate 18 is connected to the counting input of the first counter July ₁ and through a first delay element 15 is connected to second input of first AND 5 , the output of the first element And 5 is connected to the counting input of the counter 17 and through the second delay element 16 with the recording permission input of the result storage unit 11, the outputs of the i-th counter 7 _i included in the group of counters 7 ₁ , ..., 7 _n are connected to the corresponding address inputs of the i-th a memory block 19 _i included in the group of memory blocks 19 ₁ , ..., 19 _n , the outputs of the i-th memory block 19 _i included in the group of memory blocks 19 ₁ , ..., 19 _n are connected to the corresponding inputs of the i-th decoder 9 _i included in the group of decoders 9 ₁ , ..., 9 _n , i = 1, ..., n, and with the corresponding information inputs of the result storage unit 11, the j-th output of the i-th decoder 9 _{i is} connected to the i-th input of the j-th OR gate 13 _j, included in the element group OR 13 _1, ..., 13 _k, elements outputs OR 13 _1, ..., 13 _k, i = 1, ..., n, j = 1, ..., k, in the group are connected with the corresponding inputs of the adder 3, the outputs of the counter 17 are connected with the corresponding outputs 10 included in the group, and with the address inputs of the storage unit of the result 11.

When describing the system for the formation of the personnel of an innovation project, the following notation was used:

K is the number of applicants;

n is the number of functions;

P = {P ₁ , P ₂ , ..., P _k } - many applicants;

F = {F ₁ , F ₂ , ..., F _n } is the set of functions;

M - matrix of competencies;

H _ji - an element of the competency matrix M, which links the capabilities of applicants regarding the ability to perform the corresponding functions;

T = {t ₁ , ..., t _n } - the number of applicants who can perform specified functions;

K ^c _i is the counting coefficient for the counter 7 _i included in the group of n counters 7 ₁ , 7 ₂ , ..., 7 _n , i = 1, ..., n;

Wi - the number of outputs of the counter 7 _i , included in the group of n counters 7 ₁ , 7 ₂ , ..., 7 _n , i = 1, · ..., n;

Y ⁱ = {Y ⁱ ₁ , ..., Y ⁱ _Wi }, i = 1, · ..., n are the values of binary signals at the outputs of counter 7 _i , which is part of a group of n counters 7 ₁ , 7 ₂ , ..., 7 _n , i = 1, ..., n;

z is the number of outputs of memory units 19 _i included in the group of memory units 19 ₁ , ..., 19 _n ;

X ⁱ = {X ⁱ ₁ , ..., X ⁱ _z } - the values of the binary signals at the outputs of the memory block 19 _i , included in the group of memory blocks 19 ₁ , ..., 19 _n ;, i = 1, ..., n;

v is the number of bits of the group of outputs 10;

] a [is the nearest integer, not less than the number a.

In FIG. 1 shows a diagram of the proposed system for the formation of the personnel of an innovative project.

In FIG. 1, the following designations are accepted: start input 1, clock 2, adder 3, comparison circuit 4, first element And 5, device output 6, a group of n counters 7 ₁ , 7 ₂ , ..., 7 _n , readiness trigger for result 8, group of n decoders 9 ₁ , ..., 9 _n , group of outputs 10, storage unit for result 11, element NOT 12, group of k elements OR 13 ₁ , ..., 13 _k , inputs for setting the number of functions 14, delay elements 15 and 16, counter 17, the second AND gate 18, a group of n memory blocks 19 _1, ..., 19 _n.

The start input 1 is connected to the first input of the second element And 18. The output of the clock 2 is connected to the second input of the second element And 18. The outputs of the adder 3 are connected to the first group of inputs of the comparison circuit 4, the output of which is connected to the first input of the first element And 5.

The transfer output of the i-th counter 7 _{i is} connected to the counting input of the (i + 1) -th counter 7 _{i + 1} , i = 1, ..., n-1. The transfer output of the nth counter 7 _{n is} connected to a single input of the ready trigger of result 8, the output of which is connected to the output of device 6.

The output of the trigger of readiness of result 8 is connected through the element NOT 12 to the third input of the second element And 18.

The output of the second element And 18 is connected to the counting input of the first counter 7 ₁ and through the first delay element 15 is connected to the second input of the first element And 5.

The output of the first element And 5 is connected to the counting input of the counter 17 and through the second delay element 16 with the recording permission input of the result storage unit 11.

The counter 7 _i , which is part of the group of counters 7 ₁ , ..., 7 _n , has Wi outputs, i = 1, ..., n.

The outputs of the i-th counter 7 _i , included in the group of counters 7 ₁ , ..., 7 _n , are connected to the corresponding address inputs of the i-th memory block 19 _i , included in the group of memory blocks 19 ₁ , ..., 19 _n . The output Y ⁱ _{s is} connected to the s-th input of the i-th memory block 19 _i , s = 1, ..., Wi.

The decoder 9 _i , which is part of the group of decoders 9 ₁ , ..., 9 _n , has z inputs and k outputs, i = 1, ..., n. the j-th output of the i-th decoder 9 _{i is} connected to the i-th input of the j-th element OR 13 _j , which is part of the group of elements OR 13 ₁ , ..., 13 _k . The outputs of the elements OR 13 _i , ..., 13 _k , i = 1, ..., n, j = 1, ..., k included in the group are connected to the corresponding inputs of the adder 3.

The memory block 19 _i , included in the group of memory blocks 19 ₁ , ..., 19 _n , has Wi inputs and z outputs, i = 1, ..., n.

The outputs of the i-th memory block 19 _i included in the group of memory blocks 19 ₁ , ..., 19 _n are connected to the corresponding inputs of the i-th decoder 9 _i included in the group of decoders 9 ₁ , ..., 9 _n . m-th output of the i-th block of memory 19 _i , connected to the m-th input of the i-th decoder 9 _i , i = 1, ..., n, m = 1, ..., z.

The outputs of the memory blocks included in the group of memory blocks 19 ₁ , ..., 19 _n are connected to the corresponding information inputs of the result storage block 11: the j-th output of the i-th memory block 19 _{i is} connected to z × (i-1) + j- the second information input of the storage unit of the result 11, i = 1, ..., n; j = 1, ..., z. The values of the signals at the information inputs from the first to z × n have the form: {X ¹ ₁ , ..., X ¹ _z , X ² ₁ , ..., X ² _z , ..., X ⁿ ₁ , ..., X ⁿ _z }.

OR elements included in the group of OR elements 13 ₁ , ..., 13 _k have n inputs.

The outputs of the counter 17 are connected to the corresponding outputs 10 included in the group, and to the address inputs of the storage unit of the result 11.

The proposed system for the formation of the personnel of an innovative project works as follows.

The essence of the problem under consideration is as follows.

Let a set of applicants to the team = = { _{1 1} , _{2 2} , ..., _{k k} } be given, a set of functions F = {F ₁ , F ₂ , F _n } connected by a competency matrix M, in which H _ji is an element of the matrix that connects the capabilities of applicants with respect to the ability to perform the corresponding functions (Table 1).

Applicants can perform several functions. If the j-th applicant performs the i-th function, then H _ji = 1, otherwise H _ji = 0.

Of the many applicants, it is necessary to form options for the composition of the project team S∈P, in which one executor performs one function (work), and determine the version of the distribution of work between members of the project team.

The work of the system is based on the formation of many options for building a project team, in which one executor performs one job, and determining the versions of the distribution of work between members of the project team for each option.

In the initial state, all counters included in the group of n counters 7 ₁ , 7 ₂ , ..., 7 _n , and counter 17 are in the zero state. The result ready readiness trigger 8 is in the “0” state.

The number of applicants who can perform the specified functions T = {t ₁ , ..., t _n } is determined as follows:

The account coefficient for the counters included in the group of n counters 7 ₁ , 7 ₂ , ..., 7 _n , have the following values K ^c _i = t ₁ +1; K ^c _i = t _i , i = 2, ..., n.

The memory block 19 _i contains binary codes of the numbers of applicants that can perform the i-th function, i = 1, ..., n. The number of outputs of memory blocks z =] log ₂ k [.

Information about the applicants' codes is recorded in the memory block 19 ₁ from address “1” to address t ₁ , in the memory blocks 19 _i , i = 2, ..., n from address “0” to address t _i -1.

The q-bit binary code of n, q =] log ₂ n [.

The number of outputs of the group of outputs 10 and, accordingly, the number of outputs of the additional counter 17 and the address inputs of the storage unit of the result 11 is determined as follows: v =] log ₂ (C ⁿ _k ) [, where C ⁿ _k is the number of combinations of k by n.

To turn on the system, signal “1” is applied to start input 1. Since the signal “0” is at the output of the result readiness trigger 8, the signal “1” and the pulses from the output of the clock pulse generator 2 go to the counting input of the counter 7 ₁ , which is part of the group of counters, at the output of the element NOT 12. After the first pulse arrives at the outputs of the counter 7 _{1, the} binary code is "0 ... 01", and at the outputs of the remaining counters in the group, the binary codes are "0 ... 0". These codes go to the address inputs of the corresponding memory blocks 19 and binary codes of applicants are formed at their outputs. The decoders included in the group of n decoders 9 ₁ , ..., 9 _n convert the incoming binary code into a unitary one, in which only one bit has a value of "1" and the rest has a value of "0". At the output of the OR element 13 _j , which is part of a group of k elements OR 13 ₁ , ..., 13 _k , the signal “1” is generated if the j-th applicant is part of the considered option for building the project team. The adder 3 sums the values from the outputs of the OR elements included in the group of k elements OR 13 ₁ , ..., 13 _k . The binary code of the sum goes to the first group of inputs of the comparison circuit 4, which compares it with a given code of the number of functions. If n applicants participate, i.e. the condition is one executor - one function, then the output of the comparison circuit 4 generates a signal "1", which, after a pulse from the output of the first delay element 15 passes to the counting input of the additional counter 17, changing it to the next state ("0 ... 01") . After the signal from the output of the second delay element 16, information is recorded from the outputs of the memory blocks included in the group of n memory blocks 19 ₁ , ..., 19 _n into the results storage unit 11 at the address “0 ... 01”. Delay elements 15 and 16 generate signals after the end of transients in the circuit.

If the signal “0” is at the output of the comparison circuit 5, this indicates that when the option to build the project team was formed, the condition “one executor - one function” is violated, and the result is not considered.

The indicated process is repeated with the arrival of each subsequent pulse from the output of the clock generator. After considering all the options, the signal “1” is generated at the transfer output of the nth counter 7 _n , which translates the result ready 8 trigger to state “1”, while the signal “1” is generated at the output of device 6, which indicates the end of the problem solving process. At the output of element NOT 12, a signal “0” is generated, which closes the And 18 element for the passage of pulses from the output of the clock pulse generator 2. The binary code on the group of outputs 10 indicates the number of solutions obtained, and their form is recorded in the result storage block.

Below is an example of the system for the matrix of competencies given in table. 2.

As a result of the analysis of the whole set of options for building a project team, a lot of options for building a team are formed that satisfy the condition "one job - one performer", and the distribution of functions in each of their options.

Table 3 shows the solutions recorded in the storage unit of the results 11.

The solution is a binary code made up of performer codes. The location of the executor code indicates the number of the function to be performed, for example, for address 30, the binary code 111100110010101 consists of the executor codes (Table 4):

Thus, the technical result of the claimed invention is the expansion of functionality: the formation of a variety of applicants of options for building a project team in which one executor performs one function and the distribution of functions between members of the project team is achieved through technical means along with the connections mentioned in the description of the system.

Used sources

1. The system of rational allocation of resources (RU No. 2375750 C1, IPC G06Q 10/00, announced March 27, 2008, published December 10, 2009).

2. A device for solving the assignment problem (RU No. 2439687 C1, IPC G06F 17/50, announced June 1, 2010, published January 10, 2012).

3. Device for solving the assignment problem (RU No. 2511412 C1, IPC G06F 17/00, G06Q 10/06, announced December 24, 2012, published April 10, 2014).

Claims (1)

The system for the formation of the personnel of an innovation project, containing start-up input 1, clock pulse generator (GTI) 2, adder 3, comparison circuit 4, first element 5, device output 6, a group of n counters 7 ₁ , 7 ₂ , ..., 7 _n , trigger readiness of result 8, a group of n decoders 9 ₁ , ..., 9 _n , a group of outputs 10, and the outputs of the adder 3 are connected to the first group of inputs of the comparison circuit 4, the output of which is connected to the first input of the first element And 5, the transfer output i- _i th counter 7 is connected to the counting input (i + 1) -th counter 7 _{i + 1,} i = 1, ..., n-1, the output Perrin ca n-th counter 7 _n connected to the single input trigger result readiness 8, whose output is connected to the output device 6, characterized in that it additionally introduced storage unit result 11, the element is not 12, the band of k elements or 13 _1, ... , 13 _k , inputs for setting the number of functions 14, delay elements 15 and 16, counter 17, second element And 18, a group of n memory blocks 19 ₁ , ..., 19 _n , and the start input 1 is connected to the first input of the second element And 18, the output of the clock 2 is connected to the second input of the second element And 18, the output of the trigger availability Result 8 is connected through an element NOT 12 to the third input of the second AND gate 18, the output of the second AND gate 18 is connected to the counting input of the first counter July ₁ and through a first delay element 15 is connected to a second input of the first AND gate 5, the output of the first AND gate 5 is connected with the counting input of the counter 17 and through the second delay element 16 with the recording permission input of the result storage unit 11, the outputs of the i-th counter 7 _i included in the group of counters 7 ₁ , ..., 7 _n are connected to the corresponding address inputs of the i-th memory block 19 _i, included in the Rupp memories 19 _1, ..., 19 _n, outputs of i-th memory block 19 _i, in the group of memories 19 _1, ..., 19 _n, are connected to respective inputs of i-th decoder 9 _i, included in the decoders group January ₉ , ..., 9 _n , i = 1, ..., n, and with the corresponding information inputs of the result storage unit 11, the j-th output of the i-th decoder 9 _{i is} connected to the i-th input of the j-th element OR 13 _j included in group of elements OR 13 ₁ , ..., 13 _k , outputs of elements OR 13 ₁ , ..., 13 _k , i = 1, ..., n, j = 1, ..., k included in the group are connected to the corresponding inputs of adder 3, outputs counter 17 connected to the corresponding outputs 10 included in the group, and with the address inputs of the storage unit of the result 11.

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