RU2179737C1 - Method and device for servicing different-priority requests of computer system subscribers - Google Patents

Abstract

FIELD: computer engineering; data exchange systems. SUBSTANCE: device has N subscriber units, where N ≥ 2, counter, clock generator, divider, N- input NOR gate, multiplexer, inverters, AND gate, selector-multiplexer, priority coder, N-input NAND gate, low-priority decoder, K retrieval and locking units, where K is capacity of remaining wait time code. Method describes operation of this device. EFFECT: provision for servicing low-priority requests in due time. 4 cl, 18 dwg

Description

 The proposed technical solutions are united by a single inventive concept, relate to the field of computer technology and can be used in data exchange systems.

 Known methods for servicing queries of a computing system, implemented, for example, in a device by AS USSR 1441398 "Multichannel device of dynamic priority", IPC G 06 F 9/46, publ. 11.30.88, BI 44, where the increase in the priority of the request is carried out linearly at certain intervals of time; by A.S. USSR 1562912 "Multichannel device with dynamic priority change", IPC G 06 F 9/46, publ. 05/07/90, BI 17, where the increase in the priority of the request occurs after each service request in other priority areas. (The terms service, request, priority are understood as follows. Service - a set of computer system actions, including fetching a request from the queue, allocating a resource to it, and performing final operations. Request - sending a signal that initiates a response. An input message containing a request to the system for resource allocation Priority - a number assigned to a task, process or operation that determines the sequence of their execution or maintenance. The lower the number, the higher the priority level).

 However, the known methods-analogues do not take into account the permissible time the request was in the queue, which results in a high probability of loss of low-priority requests as a result of their untimely service.

 Known service query devices - see, for example, A. with. USSR 1441398 "Multichannel device of dynamic priority", IPC G 06 F 9/46, publ. 11/30/88, BI 44; A.S. USSR 1562912 "Multichannel device with dynamic priority change", IPC G 06 F 9/46, publ. 05/07/90, BI 17.

 Known analogues contain devices for increasing priority and priority analysis blocks. A common disadvantage of analogues is the low probability of timely service of requests of lower priority.

 The closest in technical essence to the claimed method of servicing requests is the method implemented in the device for servicing requests, see.c. RF 2140666 "Method of servicing user requests of a computing system and its device that implements", IPC G 06 F 9/46, publ. 10.27.99, BI 30.

The prototype method consists in the formation of codes for the maximum waiting time for the service request T _ozh.i , where i = 1,2, ..., N is the corresponding priority number of the i-th subscriber, and N is the total number of subscribers, and remember them. Then, request signals are generated and a second order queue is organized from the request signals in accordance with the priority numbers of the subscribers. Requests from the second-order queue that have reached the maximum waiting time are transferred to the first-order queue at the positions corresponding to their priority numbers. Consistently serve requests from the first-order queue in accordance with an increase in their priority numbers, and if there are no requests in the first-order queue, service requests from the second-order queue.

 The prototype method takes into account the maximum time spent by requests in the second order queue, as well as the priority of requests when transferring them to the first order queue, which ensures a high probability of their timely service.

 However, the prototype method has a drawback: a low probability of timely servicing of low priority requests. This is because the prototype method does not take into account time intervals of requests (VIZ) from the second-order queue for their priority servicing. For this reason, requests with small VIZs expect the same amount of service as requests with the same priority with large VIZs. (VIZ refers to the time required to service a request).

 Of the known closest analogue (prototype) in its technical essence of the claimed device is a device (first option), see a. from. RF 2140666 "Method of servicing user requests of a computing system and its device that implements", IPC G 06 F 9/46, publ. 10.27.99, BI 30.

A device for servicing subscriber requests of a computing system containing N subscriber units, where N≥2, counter, AND element, clock generator, divider, N-input OR-NOT element, multiplexer, first inverter. In this case, the counting input of the counter is connected to the output of the And element, and the second input of the And element is connected to the output of the clock generator and the input of the divider. The output of the divider is connected to the clock inputs of N subscriber units. Query inputs and K-bit inputs, where K≥2 is the capacity of the code for the maximum waiting time for service requests, the “Maximum waiting time code” N subscriber units are the corresponding request inputs and the K-bit inputs “Maximum waiting time code” for the device, N inputs N the input element OR is NOT connected to the “Exceed” outputs of the corresponding N subscriber units, and the output of the N-input element is NOT connected to the “Prohibition” inputs of N subscriber units. N information inputs of the multiplexer are connected to the first signal outputs of the corresponding N subscriber units. J, where J =] log ₂ N [, the subscriber code outputs of the counter are connected to the corresponding J address inputs of the multiplexer and at the same time are respectively the J outputs of the subscriber code of the device. The multiplexer output is connected to the input of the first inverter and at the same time is the enable output of the device. The output of the first inverter is connected to the first input of the AND element, and the counter reset input is the polling input of the device. Inputs "Zeroing" N subscriber units are the corresponding inputs "Zeroing" of the device.

 Moreover, each subscriber unit consists of a counter, an AND element, a three-input AND element, an inverter, an OR element. The inverse input of the counter account resolution is the request input of the subscriber unit and is connected to the first input of the element I. The information inputs of the counter are the corresponding K-bit input "Maximum waiting time code" of the subscriber unit. The counter reset input is the “Zeroing” input of the subscriber unit. The inverse output of the counter is connected to the first input of the three-input element And and the input of the inverter. The inverter output is connected to the second input of the OR element and is the “Exceed” output of the subscriber unit. The second input of the three-input element And is connected to the first input of the element I. The second input of the element And is the input "Prohibition" of the subscriber unit. The third input of the three-input element And is the clock input of the subscriber unit. The output of the three-input element AND is connected to the counting input of the counter. The output of the AND element is connected to the first input of the OR element. The output of the OR element is the first signal output of the subscriber unit.

 This scheme allows, in comparison with analog devices, to increase the likelihood of timely service of low priority requests.

 However, the prototype device has a drawback: a low probability of timely servicing of low priority requests. This is because the prototype device does not take into account VIZ requests from the second order queue when they are priority serviced. For this reason, requests with small VIZs expect the same amount of service as requests with the same priority with large VIZs.

 The purpose of the claimed technical solutions is to develop a method and device for servicing requests that increase the likelihood of timely servicing of low-priority requests without additional time loss for requests with a higher priority level by reducing the time spent in the second-order queue of requests with small VIZs.

In the claimed method, the goal is achieved by the fact that in the known method of servicing queries of a computing system, which consists in generating codes for the maximum waiting time for servicing a request T _oz.i , where i = l, 2, ..., N is the corresponding priority number i-th subscriber, and N - the total number of subscribers, remember them, generate request signals, organize a second-order queue from request signals in accordance with subscriber priority numbers, transfer requests from the second-order queue to the first-order queue, reaching f the maximum waiting time for positions corresponding to their priority numbers, sequentially serve requests from the first order queue in accordance with the increase in the numbers of their priorities, and if there are no requests in the first order queue, service requests from the second order queue, simultaneously with the formation of the maximum waiting time codes service requests additionally form M, where M≥2, codes maximum, differing in the duration of time intervals ΔT _about , sufficient for servicing relevant queries. When servicing requests from the second-order queue, the time interval ΔT _exp.min remaining before the request service timeout with the minimum priority number has expired is preliminarily compared with the maximum time intervals ΔT _{about the} remaining requests from the second-order queue. If there are requests, ΔT ΔT is less than _{about ozh.min,} from among the service request having the smallest priority number, and in absence of service request from the second-order priority queue with a minimum number, and comparing ΔT and ΔT _{ozh.min of} service and requests from the second order queue until there are no requests in the first order queue.

The new set of essential features enables to achieve said technical result by forming M, where M≥2, maximal codes differing in the length _{of the} time intervals ΔT sufficient to service the respective queries, and requests for maintenance of second order compared to pre-queue time interval ΔT _{standby .min} remaining before the request service time-out with a minimum priority number, with maximum time intervals ΔT _{about the} remaining requests and from the second-order queue and in the presence of requests, ΔT _of which is less than ΔT _wait.min , from among them serve the request with the lowest priority number, and if they are absent, the request from the second-order queue with the lowest priority number is served, and ΔT _{wait.min is} compared and ΔT _about and serve requests from the second order queue until there are no requests in the first order queue.

The goal in the inventive device for servicing multi-priority requests of subscribers of a computer system is achieved by the fact that in a known device for servicing requests for subscribers of a computer system containing N subscriber units, where N≥2, the counter, the counter input of the counter is connected to the output of the element And the second input of the element And is connected to the output of the clock generator and the input of the divider, the output of the divider is connected to the clock inputs of N subscriber units, interrogation inputs and K-bit inputs "Maximum time code “N subscriber units” are the corresponding request inputs and K-bit inputs “Maximum latency code” of the device, N-input element OR NOT, N inputs of which are connected to the “Exceed” outputs of the corresponding N subscriber units, and the output of the N-input element OR-NO element is connected to the inputs of "prohibition" N subscriber units, multiplexer, N data inputs of which are connected with the first output signal corresponding to N subscriber units, and its J, where J =] log ₂ N [, address inputs connected to respective J you odes "Subscriber code" of the counter, the multiplexer output is connected to the input of the first inverter, the output of the first inverter is connected to the first input of the And element, and the counter reset input is a polling input of the device, and the inputs of "Zeroing" N subscriber units are the corresponding inputs of "Zeroing" the device, In addition, a selector-multiplexer, a second inverter, an N-input NAND element, a priority encoder, a low level decoder, K sampling and fixing blocks are introduced. J information inputs of the first group of the selector-multiplexer are connected to the corresponding J outputs of the “Subscriber Code” of the counter, J outputs of the selector-multiplexer are respectively J outputs of the “Subscriber Subscriber Code” of the device. The input of the second inverter is connected to the input of the first inverter, and the output of the second inverter is connected to the enable input of the selector-multiplexer and at the same time is the enable output of the device, n-th, where n = 1,2, ..., N, the inverse input of the priority encoder is connected to the second signal output (N + l) -n-th subscriber unit. J inverse outputs of the priority encoder are connected to the corresponding J inputs of the second group of inputs of the selector-multiplexer. N inputs of the N-input element AND are NOT connected to the corresponding N inverse inputs of the priority encoder, and the output of the N-input element AND is NOT connected to the control input of the selector-multiplexer. J inputs of the low level decoder are connected to the corresponding J outputs of the “Subscriber Code” counter, and N inverse outputs of the low level decoder are connected to the “Resolution Comparison” inputs of the corresponding N subscriber units. The J inputs of the “Subscriber Code” of each of the K blocks of fetching and fixing are connected to the corresponding outputs of the “Subscriber Code” counter. m-th, where m = 1,2, ..., K, the discharge bit "Code remaining timeout" of the n-th subscriber unit is connected to the n-th bit of the N-bit input "Bit code remaining time-out" of the mth block sampling and fixing. The control input of each of the K blocks of sampling and fixing is connected to the output of the first inverter. Outputs "The discharge of the selected code of the remaining latency" To the sampling and latching units are connected to the corresponding bits of the K-bit inputs "Selected code of the remaining latency" of each of the N subscriber units. Moreover, each subscriber unit is additionally equipped with a K-bit input "Code maximum service time", which are also K-bit inputs "Code maximum service time" device.

 The subscriber unit consists of a counter, an AND element, a three-input AND element, an inverter, an OR element, a three-input AND element, a comparator. The inverse input of the counter account resolution is the request input of the subscriber unit and is connected to the first input of the element I. The counter information inputs are the K-bit input “Code of maximum waiting time” of the subscriber unit, and the counter reset input is the input “Reset” of the subscriber unit, the inverse output of the counter is connected to the first input of the three-input element And and the input of the inverter. The inverter output is connected to the second input of the OR element and is the “Exceed” output of the subscriber unit. The second input of the three-input element And is connected to the first input of the element I. The second input of the element And is the input "Prohibition" of the subscriber unit. The third input of the three-input element And is the clock input of the subscriber unit, and the output of the three-input element And is connected to the counting input of the counter. The output of the AND element is connected to the first input of the OR element and the first input of the three-input element AND NOT. The output of the OR element is the first signal output of the subscriber unit. The second input of the three-input AND element is NOT connected to the output of the comparator, the first and second groups of inputs of K inputs in each of which are respectively the K-bit input "Selected code for the remaining latency" and the K-bit input "Code for maximum service time" of the subscriber unit. The third input of the three-input element AND is NOT the input "Resolution comparison" of the subscriber unit. The output of the three-input element AND is NOT the second signal output of the subscriber unit. The counter outputs are respectively the K-bit output "Code remaining time out" of the subscriber unit.

 The fetch and lock block consists of a multiplexer and a D-trigger. The N information inputs of the multiplexer are respectively the N-bit input "Remains of the code for the remaining time to wait" of the fetch and hold unit, and the J address inputs of the multiplexer are respectively the J inputs of the "Subscriber code" of the fetch and hold unit. The information input of the D-trigger is connected to the output of the multiplexer, the control input of the D-trigger is the control input of the fetch and lock block. The output of the D-flip-flop is the output "The discharge of the selected code of the remaining time to wait" block sampling and fixing.

 The analysis of the prior art carried out by the applicant made it possible to establish that there are no analogs characterized by sets of features identical to all the features of the claimed method and device for servicing diverse priorities of subscribers of a computing system. Therefore, each of the claimed inventions meets the condition of patentability "Novelty".

 Search results for known solutions in this and related fields of technology, in order to identify features that match the distinctive features of the prototypes of each claimed invention showed that they do not follow explicitly from the prior art. From the prior art determined by the applicant, the popularity of the influence of the essential features of each of the claimed inventions on the achievement of the specified technical result is not revealed. Therefore, each of the claimed inventions corresponds to the condition of patentability "Inventive step".

The claimed objects of the invention are illustrated by drawings, where shown
figure 1 - the structure of the computing system;
figure 2 - placing requests in the queue of the second order;
in FIG. 3 - the order of transferring requests from the second order queue to the first order queue;
in FIG. 4 - Fig. 7 - timing diagrams of the operation of a device for servicing multi-priority requests of subscribers of a computing system;
in FIG. 8 - the average time spent in the computer system and the likelihood of timely service requests with different priorities and different VIZ;
figure 9 is the average time spent in the queue of requests with different priorities and different VIZ;
in FIG. 10 - average time spent in the computing system of requests of all priorities with different VIZ;
11 - a device for servicing multi-priority requests of subscribers of a computing system;
in Fig.12 - subscriber unit;
in Fig.13 - block sampling and fixing.

The implementation of the claimed method is as follows. For each request (group of requests), VIZ codes ΔT _vol.i and codes for the maximum service waiting time T _{ozh.i are generated} . The formation of the above codes is carried out for the following reasons. The residence time of the request of the i-th subscriber in the computer system is known and established by regulatory documents. It is determined by the value of T _add.i. The value of the VIZ of the ith subscriber ΔT _vol.i characterizes the time _spent by the computing system on its maintenance (resource allocation). The value ΔT _vol.i for each request is determined experimentally in the initial period of the functioning of the system or on the basis of statistical data on the functioning of similar systems. Moreover, in the general case, it is possible to combine requests of the ith subscriber having similar VIZ values in M, where M≥2, groups and the assignment of ΔT _vol.ji for each group of requests, where j is the sequence number of the request group sufficient for service (resource allocation) request with the maximum VIZ from this group. The value of the maximum waiting time for servicing the request, _T.sub.i , determines the maximum time the request stays in the queue, after which the resource of the computing system must be allocated to the request and can be determined by the following relation:
T _exp.i = T _add.i -ΔT _vol.ji -T _app.i ; (1)
where T _{exp. i} - the maximum waiting time for the service of the request of the i-th priority (subscriber), where i = l, 2, ..., N;
T _add.i - permissible residence time of the request of the i-th subscriber in the computer system, after which the request loses relevance or the given subscriber incurs certain losses;
ΔT _rev.ji - VIZ of the i-th subscriber, where j = 1,2, ..., M is the number of the request group;
T _app.i is a certain margin of time determined by the costs of maintenance.

 The codes for the maximum waiting time for service and the VIZ codes generated for each subscriber of the computing system are stored (stored in memory). After which the system is ready for operation and receives request signals generated by subscribers of the computing system (see figure 1). They arrive at the request servicing device, where they are placed in the second order queue according to the initial priorities (the first subscriber has the highest priority, and the Nth subscriber has the lowest) (see Fig. 2). Immediately after this, the calculation of the time spent by the requests in this queue begins.

After a signal is received from the computing system about the release of the resource, the request service device determines in the second-order queue a request with a minimum priority number z, compares the time interval ΔT _{exp. Z} remaining until the maximum waiting time for servicing this request expires, with time intervals ΔT _rev.ji (i = z + 1, z + 2, ..., N) of the remaining requests that are currently in the second-order queue. Upon detection of a request, the VIZ of which does not exceed the time remaining before the time to wait for servicing the request with the lowest priority number, that is, satisfying the inequality
ΔT _vol.ji <ΔT _burn.z , (2)
where ΔT _rev.ji is the VIZ of the i-th subscriber, where i = z + 1, z + 2, ..., N; j = 1,2, ..., M is the number of the query group;
ΔT _ozh.z - the time interval remaining until the expiration of the maximum waiting time for servicing the request in the second-order queue,
the service device issues the AB code to the computing system in which the detected request is located, after which the system allocates the requested resource. If several queries are found that satisfy inequality (2), the computing resource will be allocated to the query with the lowest priority number.

 In the case when one or more requests have reached the maximum waiting time for service in the second order queue, a first order queue is organized in the request servicing device (from requests with the elapsed maximum service waiting time) (see Fig. 3). Moreover, requests from the second-order queue are transferred to the first-order queue at positions corresponding to their priority numbers (see Fig. 3). At the same time, requests from the first-order queue have the right of primary service. From the first order queue, requests are retrieved in accordance with the priorities.

For example, at the initial time t ₁ (see Fig. 4a), there are 4 requests in the system and a signal from the computing system about the release of the resource is received. Request 1 has the highest priority (with a minimum priority number). In addition, the device contains a request 3, whose need for a computing resource can be satisfied for the length of time left by request 1 before the maximum wait time has elapsed (ΔT _vol.j3 <ΔT _{wait 1} ) and request 1 will not be considered late. The resource will be allocated to request 3. After the resource is released by request 3, at time t _2a (see Fig. 5a), the resource will be allocated to request 1, since it has a minimum priority number and there are no requests in the device that satisfy condition (2). After the resource is freed by request 1 at time t _3a (see Fig. 6a), the resource will be allocated to request 4, since by this time the maximum waiting time for servicing request 4 in the second-order queue exceeded the value of T _{oz. 4} , and the request was transferred to first order queue. After releasing the resource by request 4, at time t _4a (see Fig. 7a), the resource will be allocated to request 2.

The sequence of service requests when applying the prototype method will be as follows. At the initial time t _{1, the} resource will be allocated to request 1 (see Fig. 4b). At time t _{2b, the} resource will be allocated to request 2 (see FIG. 5b). Further, at times t _3b and t _{4b, the} resource will be allocated to requests 4 and 3, respectively, since each of them will time out by the corresponding time points. As a result, requests 4 and 3 will be allocated the resource with a significant delay.

 The claimed method of servicing multi-priority requests provides a high probability of servicing low-priority requests by taking into account the maximum waiting time for servicing requests in the second-order queue, as well as reducing the time spent in the queue of requests with small VIZ (in comparison with the prototype method) by using the time reserve remaining before the maximum waiting time for serving priority requests.

The validity of the theoretical assumptions was checked using a simulation model of a computing system, with the exponential law of the distribution of receipt of service requests. The verification results are shown in tabular form on Fig-10, where
Etc. - request priority number (three priorities are considered for simplicity);
VIZ - time interval of the request;
T _cf. - average time spent by the request in the computing system (average service time);
σ is the standard deviation;
P (T≤T _add. ) - the probability of timely service requests by the computing system;
T _{cf. in the middle} - the average wait time by a request for resource allocation by a computing system.

 From the above data it follows that the claimed method allows to increase the likelihood of timely servicing of low priority requests to 3% by reducing the time spent in the queue of requests with small VIZ by 1.1-1.3 times in comparison with the prototype method, which indicates the possibility of achieving this technical result.

The device (Fig. 11) consists of a clock generator 2, a divider 3, an N-input element OR NOT 4, a counter 5, an element 6, a first inverter 7, a multiplexer 8, a low level decoder 11, a priority encoder 12, N- input element AND-NOT 13, the second inverter 14, the selector-multiplexer 15, N subscriber units (AB) l ₁ -l _N (the AB circuit is shown in Fig. 12), K sampling and fixing blocks (BCF) 9 ₁ -9 _k (the BVF diagram is depicted in FIG. 13).

шифратора приоритетов 12 соединены с вторыми сигнальными выходами 28 АБ 1₁-1_N, при этом подключение осуществлено следующим образом: 1-й инверсный вход шифратора приоритетов 12 подключен к второму сигнальному выходу N-го АБ, 2-й инверсный вход шифратора приоритетов 12 подключен к второму сигнальному выходу N-1-гo АБ, n-й инверсный вход шифратора приоритетов 12 подключен к второму сигнальному выходу (N+1)-n-гo АБ, а N-й инверсный вход шифратора приоритетов 12 подключен к второму сигнальному выходу 1-го АБ. Кроме того, N инверсных входов 28

шифратора приоритетов 12 соединены с соответствующими N входами N-входового элемента И-НЕ 13. Инверсные выходы

шифратора приоритетов 12 подключены к соответствующим J входам второй группы информационных входов B₁-B_J селектора-мультиплексора 15. Выход элемента И-НЕ 13 подключен к селективному входу V селектора-мультиплексора 15.Elements are interconnected as follows (see Fig.11). The output of the clock generator 2 is connected to the input of the divider 3 and the second input of the element And 6. The output of the divider 3 is connected to the clock inputs of 20 AB. The first signal outputs 25 ₁ -25 _N AB are connected respectively to the information inputs A ₁ -A _{N of} multiplexer 8, the output Y of which is connected to the input of the first inverter 7 and to the input of the second inverter 14. The output of the first inverter 7 is connected to the first input of the element And 6 and to control inputs 29 of each of the KVF. The output of element And 6 is connected to the counting input C of the counter 5. The reset input R of the counter 5 is the polling input of the device 31. The J information outputs Q ₁ -Q _{J of the} counter 5 are connected to the corresponding J inputs of the Subscriber Code 27 of the BVF, to the corresponding J control inputs V multiplexer 8, to J inputs a _{1- j of the} first group of information inputs of the selector-multiplexer 15, and to J information inputs X ₁ -X _{J of the} low-level decoder 11. The output of the second inverter 14 is connected to the enable input E of the selector-multiplexer 15 and is enable output 32 devices oystva. The 16 AB request inputs are the corresponding device input requests. K-bit inputs 17 "Code maximum latency" AB are the corresponding K-bit inputs 17 "Code maximum latency" device. The Zero Inputs 18 AB are the corresponding Zero Inputs of the device. K-bit inputs 19 "Code maximum service time" AB are the corresponding K-bit inputs 19 "Code maximum service time" device. Inverted inputs 28

Priority encoder 12 is connected to the second signal outputs 28 AB 1 ₁ -1 _N , the connection is as follows: 1st inverse input of priority encoder 12 is connected to the second signal output of N-th battery, 2nd inverse input of priority encoder 12 is connected to the second signal output of N-1st AB, the n-th inverse input of priority encoder 12 is connected to the second signal output (N + 1) -n-th AB, and the N-th inverse input of priority encoder 12 is connected to second signal output 1 AB. In addition, N inverse inputs 28

priority encoder 12 connected to the corresponding N inputs of the N-input element AND NOT 13. Inverted outputs

the priority encoder 12 is connected to the corresponding J inputs of the second group of information inputs B ₁ -B _{J of the} selector-multiplexer 15. The output of the AND-NOT 13 element is connected to the selective input V of the selector-multiplexer 15.

дешифратора низкого уровня 11 подключены соответственно к входам 22₁-22_N "Разрешение сравнения" АБ. K-разрядные выходы 23₁-23_N "Код оставшегося времени ожидания" каждого из N АБ подключены к N-разрядным входам 30₁-30_N "Разряды кода оставшегося времени ожидания" К БВФ, при этом подключение осуществлено следующим образом: 1-е разряды K-разрядных выходов 23₁-23_N "Код оставшегося времени ожидания" каждого из N АБ подключены к соответствующим разрядам N-разрядного входа 30₁ "Разряды кода оставшегося времени ожидания" 1-го БВФ, 2-е разряды K-разрядных выходов 23₁-23_N "Код оставшегося времени ожидания" каждого N АБ подключены к соответствующим разрядам N-разрядного входа 30₂ "Разряды кода оставшегося времени ожидания" 2-го БВФ, m-е разряды К-разрядных выходов 23₁-23_N "Код оставшегося времени ожидания" каждого из N AБ подключены к соответствующим разрядам N-разрядного входа 30_m "Разряды кода оставшегося времени ожидания" m-го БВФ, К-е разряды K-разрядных выходов 23₁-23_N "Код оставшегося времени ожидания" каждого из N АБ подключены к соответствующим разрядам N-разрядного входа 30_K "Разряды кода оставшегося времени ожидания" K-го БВФ. Выходы 10₁-10_K "Разряд выбранного кода оставшегося времени ожидания" К блоков выборки и фиксации подключены к соответствующим разрядам K-разрядных входов 26 "Выбранный код оставшегося времени ожидания" каждого из N АБ.The outputs Y ₁ -Y _{j of the} selector-multiplexer 15 are the corresponding J outputs 33 of the device Subscriber Subscriber Service Code 33. Exceeding outputs 24 ₁ -24 _N АБ 1 ₁ -1 _{N are} connected to the corresponding inputs of the N-input element AND-NOT 4. The output of the N-input element AND-NOT 4 is connected to inputs 21 "Inhibition" AB 1 ₁ -1 _N . Inverse outputs

low-level decoder 11 are connected respectively to the inputs 22 ₁ -22 _N "Resolution comparison" AB. K-bit outputs 23 ₁ -23 _N “Remaining time-out code” of each N battery are connected to N-bit inputs 30 ₁ -30 _N “Remains code of the remaining time-out" To the IWF, while connecting as follows: 1st bits of K-bit outputs 23 ₁ -23 _N “Remaining time-out code” of each N battery are connected to the corresponding bits of the N-bit input 30 ₁ “bits of code remaining time-out” of the 1st BVF, 2nd bits of K-bit outputs 23 ₁ -23 _N "Code remaining time out" of each N battery connected to the corresponding bits N-bit input 30 ₂ "The bits of the code for the remaining time out" of the 2nd BCF, the mth bits of the K-bit outputs 23 ₁ -23 _N "The code for the remaining time" of each of the N AB connected to the corresponding bits of the N-bit input 30 _m " The bits of the code for the remaining timeout "mth BVF, K-bits of the K-bit outputs 23 ₁ -23 _N " The code for the remaining timeout "of each N battery connected to the corresponding bits of the N-bit input 30 _K " The bits of the code for the timeout "Kth BVF. Outputs 10 ₁ -10 _K "The discharge of the selected code for the remaining timeout" K fetch and hold blocks are connected to the corresponding bits of the K-bit inputs 26 "Selected code for the remaining timeout" of each of the N AB.

 The clock generator 2 is designed to generate a synchronizing sequence of pulses and can be built according to any known scheme. See, for example, V.L. Awl. Popular chip TTL. - M.: ARGUS, 1993, p. 18.

Divider 3 is designed to increase the period following the pulse train arriving at its input. The specific value of the necessary division depends on the selected clock frequency of the device clock generator, as well as on a given range of time _delays T _oz.i. Implementation schemes for such a divider are known. In particular, the divider can be built on a counter. See, for example, P.P. Maltsev, N.S. Dolidze et al. Digital integrated circuits. Directory. - M .: Radio and communications, 1994, p. 62-74. In this case, the input of the divider will be the counter input of the counter, and the output of the divider will be one of the outputs of the counter.

 Counter 5 is intended for counting pulses arriving at its counting input and outputting their number in binary code. See, for example, P.P. Maltsev, N.S. Dolidze et al., Digital integrated circuits. Directory. - M .: Radio and communications, 1994, p. 62-74.

 The multiplexer 8 is designed for alternately switching the signal outputs 14 of the subscriber units to the input of the inverter 7 and the input of the inverter 14. See, for example, B.C. Tutnikov, V.V. Lopatin et al. Electronic devices of information-measuring equipment. Tutorial. -L .: LPI named after Kalinina, 1980, p. 70-72.

 The low level decoder 11 is designed to convert the binary code arriving at its input into a low level signal at one of its outputs. Low level decoder implementation schemes are known. See, for example, P.P. Maltsev, N.S. Dolidze et al. Digital integrated circuits. Directory. - M .: Radio and communications, 1994, p. 42-43.

 Priority encoder 12 is designed to convert a low-level signal at one of its inputs into a binary code at its output, and the conversion is carried out taking into account the priorities of the signals corresponding to the numbers of inputs. The priority encryption implementation scheme is known. See, for example, P.P. Maltsev, N. S. Dolidze, and others. Digital integrated circuits. Directory. - M .: Radio and communications, 1994, p. 40.

 The selector-multiplexer 15 is designed for switching one of two J-bit groups of inputs to output. Implementation schemes for such a selector-multiplexer are known. See, for example, P.P. Maltsev, N.S. Dolidze et al. Digital integrated circuits. Directory. - M .: Radio and communications, 1994, p. 36.

Subscriber units 1 ₁ -1 _N are designed to control the receipt of request signals, calculate the remaining waiting time, compare the remaining time to wait for the selected request with the VIZ of the remaining requests, generate control signals for extraordinary service of requests based on the results of comparison, as well as control signals to increase priority after the set timeout for each request.

 The subscriber unit can be implemented in various ways. In particular, its circuit shown in FIG. 12, contains the AND element 1.1, the OR element 1.2, the inverter 1.3, the counter 1.4, the three-input element AND 1.5, the comparator 1.6, the three-input element AND-NOT 1.7.

счетчика 1.4, с вторым входом трехвходового элемента И 1.5 и является запросным входом 16 АБ. K информационных входов D₁-D_K счетчика 1,4 являются К-разрядным входом 17 "Код максимального времени ожидания" АБ. Вход обнуления R счетчика 1.4 является входом 18 "Обнуление" АБ. Счетный вход С счетчика 1.4 подключен к выходу трехвходового элемента И 1.5, инверсный выход переполнения

счетчика 1.4 подключен к первому входу трехвходового элемента И 1.5 и к входу инвертора 1.3. Третий вход трехвходового элемента И 1.5 является тактовым входом 20 АБ. Выход инвертора 1.3 подключен к второму входу элемента ИЛИ 1.2 и одновременно является выходом 24 "Превышение" АБ. Второй вход элемента И 1.1 является входом 21 "Запрет" АБ. Выход элемента И 1.1 соединен с первым входом элемента ИЛИ 1.2 и с первым входом трехвходового элемента И-НЕ 1.7. Выход элемента ИЛИ 1.2 является первым сигнальным выходом 25 АБ. К информационных выходов Q₁-О_K счетчика 1.4 являются К-разрядным выходом 23 "Код оставшегося времени ожидания" АБ. К входов B₁-В_K второй группы информационных входов компаратора 1.6 являются K-разрядным входом 19 "Код максимального времени обслуживания" АБ. К входов А₁-А_K первой группы информационных входов компаратора 1.6 являются K-разрядным входом 26 "Выбранный код оставшегося времени ожидания" АБ. Выход "А<В" компаратора 1.6 подключен к второму входу трехвходового элемента И-НЕ 1.7. Третий вход трехвходового элемента И-НЕ 1.7 является входом 22 "Разрешение сравнения" АБ. Выход трехвходового элемента И-НЕ 1.7 является вторым сигнальным выходом 28 АБ.The first input of the element And 1.1 (see Fig. 12) is connected to the inverse input of the account resolution

counter 1.4, with the second input of the three-input element And 1.5 and is a request input of 16 AB. K information inputs D ₁ -D _K counter 1,4 are K-bit input 17 "Code maximum latency" AB. The input zeroing R counter 1.4 is the input 18 "Zeroing" AB. Counting input From counter 1.4 is connected to the output of a three-input element AND 1.5, inverse overflow output

counter 1.4 is connected to the first input of the three-input element And 1.5 and to the input of the inverter 1.3. The third input of the three-input element AND 1.5 is a clock input of 20 AB. The output of the inverter 1.3 is connected to the second input of the OR element 1.2 and at the same time is the output 24 "Excess" AB. The second input of the element And 1.1 is the input 21 "Prohibition" AB. The output of AND 1.1 is connected to the first input of OR 1.2 and to the first input of a three-input AND-NOT 1.7 element. The output of the OR element 1.2 is the first signal output of 25 AB. To the information outputs Q ₁ -O _{K of the} counter 1.4 are K-bit output 23 "Code remaining time out" AB. To the inputs B ₁ -B _{K of the} second group of information inputs of the comparator 1.6 are K-bit input 19 "Code maximum service time" AB. To the inputs A ₁ -A _{K of the} first group of information inputs of the comparator 1.6 are K-bit input 26 "Selected code remaining timeout" AB. The output "A <B" of the comparator 1.6 is connected to the second input of the three-input element AND-NOT 1.7. The third input of the three-input element AND-NOT 1.7 is input 22 "Resolution of comparison" AB. The output of the three-input element AND-NOT 1.7 is the second signal output of 28 AB.

 Counter 1.4 is intended for counting pulses (counting pulses) received at its input, generating the counting result in binary code, generating a control signal determined by the initial filling code for inputs D and the repetition period of the clock pulses, that is, it is a configurable timer. The description of the operation and the circuit of such a counter are known and are given, for example, in the book: P.P. Maltsev, N.S. Dolidze et al. Digital integrated circuits. Directory - M .: Radio and communications, 1994, p. 64-65.

 Comparator 1.6 is intended for comparing binary codes of two groups of K-bit inputs and generating a comparison result. A description of the work and the comparator circuit are given, for example, in the book: V.L. Shilo Popular TTL chips. - M.: ARGUS, 1993, p. 183-184.

The sampling and fixing blocks 9 ₁ -9 _K are designed to allocate bits of code for the remaining time to wait for the selected request and to fix them for subsequent comparison in AB.

 BVF can be implemented in various ways. In particular, its circuit shown in FIG. 13, comprises a multiplexer 9.1 and a D-trigger 9.2.

N information inputs a ₁ -a _{n of} multiplexer 9.1 (see Fig. 13) are N-bit input 30 "bits of the code remaining timeout" BCF. J address inputs of V multiplexer 9.1 are the corresponding J inputs 27 "Subscriber code" BCF. The output Y of the multiplexer 9.1 is connected to the information input D of the D-flip-flop 9.2. Control input C of the D-flip-flop 9.2 is the control input 29 of the BCF. The output of the D-flip-flop 9.2 is the output 10 "Discharge of the selected code for the remaining latency" BVF.

 The multiplexer 9.1 is designed for switching one of the N inputs to its output. The implementation scheme of such a multiplexer is known. See, for example, in the book: P.P. Maltsev, N.S. Dolidze et al. Digital integrated circuits. Directory. - M .: Radio and communications, 1994, p. 34-35.

 D-trigger 9.2 is designed to store the signal received at its information input. See, for example, in the book: P.P. Maltsev, N.S. Dolidze et al. Digital integrated circuits. Directory. - M .: Radio and communications, 1994, p. 50-51.

The device operates as follows. In the initial period of operation, when service requests are not received, low logic levels are set at the request inputs 16 ₁ -16 _N АБ 1 ₁ -1 _N (see Fig. 11). The pulses come from the clock generator 2 through the open element And 6 to the counting input C of the counter 5, the outputs of which along the front of each clock pulse sequentially changes the code combinations, which are the numbers of AB in binary J-bit code (2 ^J = N). Code combinations from the output of counter 5 are supplied to the address inputs V of multiplexer 8, alternately switching to the output Y of multiplexer 8 the signals from the first signal outputs 25 ₁ -25 _N АБ 1 ₁ -l _N in the sequence determined by their priorities (i.e., from top to bottom). The enable output 32 of the device is set to a high logic level.

When a request is received on a group of inputs 17 ₁ -17 _N "Code maximum waiting time" to the information inputs D ₁ -D _K - counter 1.4 AB receives a K-bit code for the maximum waiting time for servicing a request Т _ozh.i. The smallest latency corresponds to the largest code, which is in addition to the maximum number represented in the K-bit code. According to the group of inputs 19 "Maximum service time", the K-bit VIZ code is received at the information inputs b ₁ -b _{k of the} comparator 1.6 of the corresponding battery. The smallest VIZ corresponds to the largest code, which is in addition to the maximum number represented in the K-bit code. Then, at the request input 16 of the corresponding battery, a high level is set. At the same time, a high level will be established at the signal output of 25 AB (through the open AND 1.1 element and the OR 1.2 element). The counting input From the counter 1.4 of the corresponding battery receives pulses from the clock generator 2 through the circuit: divider 3, clock input 20 AB, open three-input element AND 1.5 AB. The counter 1.4 AB performs the function of a timer, which is triggered after a certain interval of time (upon reaching overflow).

The current values of the counters 1.4 ₁ -1.4 _N from the outputs Q ₁ -Q _K are sent to the K-bit outputs 23 ₁ -23 _N "Remaining standby time code" _{of the} battery. The bits of the current values of the counters are supplied to the N-bit inputs 30 ₁ -30 _K “bits of the code for the remaining latency time” of the BVF, while the bits with the same serial number arrive at the BVF with the number corresponding to this serial number, that is, the m-th bit K- bit output 23 "Code remaining time" (where m = 1,2, ..., K) of the n-th battery goes to the n-th bit (where n = 1, 2, ..., N) N-bit input 30 "discharge code remaining timeout" m-th block sampling and fixing.

As the resource becomes free, the computing system generates a high-level pulse, which is fed to the interrogation input 31 of the device, and the counter 5 is reset. Further, as clock pulses arrive from the clock pulse generator 2, the counter input 5 is scanned by the multiplexer 8 of the signal outputs 25 ₁ -25 _N AB in priority order (top to bottom), and one at a switching discharge current values of the remaining waiting time code requests from the inlet 30 ₁ -30 _N BVF on output 10 ₁ -10 _K for BVF enu: data inputs A ₁ -A _N multiplexers ₁ 9.1 -9.1 _K, Y data outputs of the multiplexers ₁ 9.1 -9.1 _K data inputs of flip-flops D _D-1 9.2 -9.2 _K data outputs of flip-flops _D-1 9.2 -9.2 _K.

шифратора приоритетов 12, причем второй сигнальный выход n-ого АБ подключен к (N+1)-n-му инверсному входу шифратора приоритетов 12. Указанный способ подключения вторых сигнальных выходов 28₁-28_N АБ на входы

шифратора приоритетов 12 обусловлен тем, что выходы шифратора приоритетов 12 инверсные, то есть для получения на его выходе кода АБ с наименьшим номером приоритета следует скоммутировать его входы в обратном порядке. Шифратор приоритетов 12 формирует на своих выходах

код АБ с наименьшим номером приоритета из числа АБ, имеющих низкий уровень на втором сигнальном выходе 28 (то есть из числа АБ, участвующих в рассмотрении). С инверсных выходов

шифратора приоритетов 12 код АБ поступает на J входов B₁-B_J второй группы информационных входов селектора-мультиплексора 15. Одновременно на J входов A₁-A_J второй группы информационных входов селектора-мультиплексора 15 поступает код выбранного АБ. В том случае, если существует хотя бы один АБ, в котором находится сигнал запроса, ВИЗ которого меньше текущего значения времени ожидания запроса в выбранном АБ, на входе V селектора-мультиплексора 15 N-входовым элементом И-НЕ 13 будет установлен сигнал высокого уровня. При этом селектор-мультиплексор 15 коммутирует на выходы 33 "Код подлежащего обслуживанию абонента" устройства код АБ, установленный на группе входов b₁-В_J. В противном случае селектор-мультиплексор 15 коммутирует на выходы 33 "Код подлежащего обслуживанию абонента" устройства код АБ, установленный на группе входов A₁-A_J. Сигналом, разрешающим работу селектора-мультиплексора 15 является сигнал низкого уровня на разрешающем входе Е, поступающий через второй инвертор 14 с выхода Y мультиплексора 8. Одновременно сигнал низкого уровня с выхода второго инвертора 14 является разрешающим сигналом вычислительной системе на считывание кода АБ, подлежащего обслуживанию. Второй инвертор 14 выбирается таким образом, чтобы время задержки сигнала в нем было не меньше, чем время последовательного прохождения сигналов по цепи: мультиплексор 9.1 БВФ, D-триггер 9.2 БВФ, компаратор 1.6 АБ, трехвходовый элемент И-НЕ 1.7 АБ, шифратор приоритетов 12.Upon detection of the first counter high level at the signal outputs of 25 AB, it is switched to the output Y of multiplexer 8. At the same time, the output of the inverter 7 is set to a low level, which closes the And 6 element and prevents the receipt of clock pulses at the input C of counter 5, stopping scanning and fixing on counter output 5 code selected AB? and also sets the low level on the control inputs 29 of the BVF 9 ₁ -9 _K , thereby transferring the D-triggers 9.2 ₁ -9.2 _K BVF 9 ₁ -9 _K to the information storage mode. At the same time, at the outputs 10 ₁ -10 _K BVF 9 ₁ -9 _K the current value of the code of the remaining time to wait for a request located in the selected battery is received, which is received via K-bit inputs 26 "Selected code of the remaining time to wait" AB 1 ₁ -1 _N to the K-bit inputs of group A of comparators 1.6 ₁ -1.6 _{N of} each of the batteries. In comparators 1.6 ₁ -1.6 _{N of} all ABs, the current value of the remaining waiting time for the request located in the selected AB with the codes of VIZ requests located in other ABs with lower priorities is compared to identify one or more ABs with requests whose VIZ does not exceed the remaining waiting time request in the selected AB. In the event that there is a request in the AB whose VIZ is less than the time remaining until the maximum waiting time for the request to be served in the selected AB (that is, “A <B”, since codes that complement the maximum value presented in K- are compared bit code), at the output "A <B" of comparator 1.6, a high level signal is formed, which, arriving at the three-input element AND-NOT 1.7, sets a low level at the second signal input 28. Only those ABs will have a high level at the second signal outputs 28 in which there is a request signal at the request input 16 (the three-input AND-1.7 element is closed by a low level at the first input), as well as in the selected battery, since the third input of the three-input AND-1.7 element of the selected AB receives a low signal from the corresponding output of the low level decoder 11. The low-level decoder 11 allows to exclude from further consideration the result of comparing the remaining waiting time of the request in the selected AB with its VIZ. From the second signal outputs 28 AB signals are fed to the inverse inputs

the priority encoder 12, and the second signal output of the nth battery is connected to the (N + 1) -th inverse input of the priority encoder 12. The specified method of connecting the second signal outputs 28 ₁ -28 _N AB to the inputs

Priority encoder 12 is due to the fact that the outputs of the priority encoder 12 are inverse, that is, to get the AB code with the lowest priority number on its output, you must switch its inputs in the reverse order. Priority encoder 12 generates at its outputs

AB code with the lowest priority number from the number of ABs having a low level at the second signal output 28 (that is, from the number of ABs participating in the review). From inverse outputs

Priority encoder 12, the AB code is supplied to the J inputs B ₁ -B _{J of the} second group of information inputs of the selector-multiplexer 15. At the same time, the J code of the selected AB is sent to the J inputs A ₁ -A _{J of the} second group of information inputs of the selector-multiplexer 15. In the event that there is at least one battery in which the request signal is located, the VIZ of which is less than the current value of the request timeout in the selected battery, a high level signal will be set at the input V of the selector-multiplexer 15 by the N-input element NAND 13. In this case, the selector-multiplexer 15 switches to the outputs 33 "Code subject to servicing the subscriber" device code AB installed on the group of inputs b ₁ -B _J. Otherwise, the selector-multiplexer 15 switches to the outputs 33 "Code subject to servicing of the subscriber" device code AB installed on the group of inputs A ₁ -A _J. The signal enabling the operation of the selector-multiplexer 15 is a low level signal at the enable input E, supplied through the second inverter 14 from the output Y of the multiplexer 8. At the same time, the low level signal from the output of the second inverter 14 is an enable signal to the computer system for reading the AB code to be serviced. The second inverter 14 is selected so that the delay time of the signal in it is not less than the time of the sequential passage of signals along the circuit: multiplexer 9.1 BVF, D-trigger 9.2 BVF, comparator 1.6 AB, three-input element NAND 1.7 AB, priority encoder 12 .

счетчика 1.4 устанавливается низкий уровень, который запирает трехвходовый элемент И 1.5, запрещая поступление тактовых импульсов на счетный вход С счетчика 1.4. Переключается инвертор 1.3 и на его выходе устанавливается высокий уровень. При этом высокий уровень с выхода "Превышение" 24 данного АБ переключает N-входовый элемент ИЛИ-НЕ 4 и на входах 21 "Запрет" всех АБ устанавливается сигнал низкого уровня. В результате на выходе элемента И 1.1 всех АБ устанавливается сигнал низкого уровня, который запирает трехвходовые элементы И-НЕ 1.7. При этом высокий уровень на первых сигнальных выходах 25 АБ будет только у запросов, достигших максимального времени ожидания, а на вторых сигнальных выходах 28 всех АБ будет установлен высокий уровень. В результате на селективном входе V селектора-мультиплексора 15 N-входовым элементом И-НЕ 13 будет установлен низкий уровень, коммутирующий на выходы 33 "Код подлежащего обслуживанию абонента" коды АБ, поступающие на входы группы А селектора-мультиплексора 15. В результате сканирования первых сигнальных выходов 25 АБ счетчиком 5 будет выбран АБ, имеющий наивысший приоритет из числа АБ с запросами, достигшими максимального времени ожидания. После выполнения очередного запроса с истекшим временем ожидания осуществляется сброс счетчика 1.4 АБ по входу "Обнуление" 18, что установит высокий уровень на выходе

счетчика 1.4, устанавливая тем самым на выходе "Превышение" 24 низкий уровень, что позволит устройству после выполнения всех запросов с истекшим временем ожидания перейти к обслуживанию вновь поступивших, либо ждущих своей очереди запросов в порядке, определенном логикой работы устройства.If one or several requests as a result of the created queue have reached the maximum waiting time, their priority service is performed. Upon reaching the maximum latency on the inverse overflow output

counter 1.4 is set to a low level that locks the three-input element And 1.5, prohibiting the receipt of clock pulses at the counting input From the counter 1.4. The inverter 1.3 is switched and a high level is set at its output. At the same time, the high level from the “Exceed” output 24 of this battery switches the N-input element OR NOT 4 and a low level signal is set at inputs 21 of the “Prohibition” of all batteries. As a result, a low-level signal is established at the output of the AND 1.1 element of all batteries, which blocks the three-input AND-NOT 1.7 elements. At the same time, only the requests that have reached the maximum waiting time will have a high level at the first signal outputs of 25 AB, and a high level will be set at the second signal outputs of 28 ABs. As a result, at the selective input V of the selector-multiplexer 15, the N-input element NAND 13 will be set to a low level that switches to the outputs 33 "Code of the subscriber to be serviced" AB codes received at the inputs of group A of the selector-multiplexer 15. As a result of scanning the first signal outputs of 25 AB counter 5 will be selected AB having the highest priority from among the AB with requests that have reached the maximum latency. After the execution of the next request with the expired waiting time, the counter is reset to 1.4 AB at the input "Zero" 18, which will set a high level at the output

counter 1.4, thereby setting the output “Exceed” 24 to a low level, which will allow the device after completing all requests with an expired wait time to proceed to service newly arrived or waiting for their turn requests in the order determined by the logic of the device.

Claims (4)

1. A method of servicing requests of subscribers of a computing system, which consists in generating codes for the maximum waiting time for servicing a request T _ozh.i , where i = 1,2 _,. . . , N is the corresponding priority number of the i-th subscriber, and N is the total number of subscribers, remember them, generate request signals, organize a second order queue from the request signals in accordance with the priority numbers of subscribers, transfer requests from the second order queue to the first order queue, having reached the maximum waiting time for positions corresponding to their priority numbers, they sequentially serve requests from the first order queue in accordance with an increase in their priority numbers, and in the absence of requests mong the first-order service request from a second-order queue, characterized in that simultaneously with the formation of the maximum service latency codes requests further form where M ≥ 2, code maximal differing duration time intervals ΔT _of sufficient to service the respective requests, wherein when servicing requests from the second-order queue, the time interval ΔT _{exp is} previously compared _{. min} , remaining until the request service timeout has expired with a minimum priority number, with maximum time intervals ΔT _{about the} remaining requests from the second order queue, and if there are requests, ΔT _about which is less than ΔT _{exp. min} , from among them a request is served having the smallest priority number, and in their absence, a request is served from a second order queue with a minimum priority number, and ΔT _{aw are} compared _{. min} and ΔT _about and serve requests from the second order queue until there are no requests in the first order queue. 2. A device for servicing subscriber requests of a computing system containing N subscriber units, where N ≥ 2, the counter the counter input of the counter is connected to the output of the element And the second input of the element And is connected to the output of the clock generator and the input of the divider, the output of the divider is connected to the clock inputs N subscriber units, interrogation inputs and K-bit inputs "Code of maximum waiting time", where K ≥ 2 is the capacity of the code of the maximum waiting time for servicing a request, N subscriber units are corresponding interrogation moves and K-bit inputs "Code of maximum latency" of the device, N-input OR-NOT element, N inputs of which are connected to the "Exceed" outputs of the corresponding N subscriber units, and the output of the N-input OR-NOT element is connected to inputs "Prohibition "N subscriber units, a multiplexer, N information inputs of which are connected to the first signal outputs of the corresponding N subscriber units, and its J, where J =] log ₂ N [, address inputs are connected to the corresponding J outputs of the" Subscriber Code "counter, the multiplexer output is connected to the entrance p of the first inverter, the output of the first inverter is connected to the first input of the And element, and the counter reset input is a polling input of the device, and the inputs “Zeroing” N of the subscriber units are the corresponding inputs “Zeroing” of the device, characterized in that the selector-multiplexer, J information the inputs of the first group of which are connected to the corresponding J outputs of the “Subscriber Code” of the counter, the J outputs of the selector-multiplexer are respectively J outputs of the “Code of Subscriber Subscriber Service” devices A second inverter having an input connected to the input of the first inverter, and the output - to the enabling input of the selector-multiplexer and is simultaneously permitting output device priority encoder, n-th inverse input of which, where n = 1,2. . . , N, is connected to the second signal output (N + 1) of the nth subscriber unit, J inverse outputs of the priority encoder are connected to the corresponding J inputs of the second group of inputs of the selector-multiplexer, the N-input element is NOT, the N inputs of which are connected to the corresponding N inverse inputs of the priority encoder, and the output of the N-input element AND is NOT connected to the control input of the selector-multiplexer, a low level decoder, J inputs of which are connected to the corresponding J outputs of the “Subscriber code” of the counter, N inverse outputs of the decoder are at a low level are connected to the “Resolution Comparison” inputs of the corresponding N subscriber units, K is the sampling and fixing blocks, where K is the length of the code of the remaining waiting time, J inputs of the “Subscriber Code” of each of which are connected to the corresponding outputs of the “Subscriber Code” counter, m- th digit, where m = 1,2. . . , K, K-bit output "Code remaining time out" of the n-th subscriber unit is connected to the n-th bit of the N-bit input "Bit code remaining time out" of the m-th block of sampling and fixing, the control input of each of K blocks of sampling and latching is connected to the output of the first inverter, the outputs are “Discharge of the selected code for the remaining latency” To the sampling and latching blocks are connected to the corresponding bits of the K-bit inputs “Selected code of the remaining latency” for each of the N subscriber units, each subscriber unit ok is additionally equipped with a K-bit input "Code of maximum service time", which is also a K-bit input "Code of maximum service time" of the device.  3. The device according to p. 2, characterized in that the subscriber unit consists of a counter, the inverse of the account resolution of which is the request input of the subscriber unit and is connected to the first input of the I element, K information inputs of the counter are K-bit input "of the subscriber unit, and the counter reset input is the input" Zeroing "of the subscriber unit, the inverse output of the counter is connected to the first input of the three-input element And and the input of the inverter, the inverter output is connected to the second input of the element OR, and is the “Exceed” output of the subscriber unit, the second input of the three-input element And is connected to the first input of the element And, the second input of the element And is the input "Prohibition" of the subscriber unit, the third input of the three-input element And is the clock input of the subscriber unit, and the output of the three-input element And connected to the counter counter input, the output of the AND element is connected to the first input of the OR element and the first input of the three-input AND element, and the output of the OR element is the first signal output of the subscriber unit, the second input of three inputs of the ith element is NOT connected to the output of the comparator, the first and second groups of inputs of K inputs in each of which are respectively the K-bit input "Selected code for the remaining latency" and the K-bit input "Code for maximum service time" of the subscriber unit, and the third the input of the three-input element AND-NOT is the input "Comparison resolution" of the subscriber unit, the output of the three-input element AND-NOT is the second signal output of the subscriber unit, K outputs of the counter are respectively K-bit output vshegosya timeout "subscriber unit.  4. The device according to claim 2 or 3, characterized in that the sampling and fixing unit consists of a multiplexer, N information inputs of which are the N-bit input "Remaining time-out code bits" of the sampling and fixing unit, and J address inputs of the multiplexer are J the “Subscriber Code” inputs of the fetch and fix block, D-flip-flop, the information input of which is connected to the output of the multiplexer, and whose control input is the control input of the fetch and fix block, the D-flip-flop output is the output “The selected code bit remains the remaining latency of the fetch and commit block.

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