RU2287179C1 - Device for servicing requests of different priorities from clients of a computer system - Google Patents

Abstract

FIELD: computer engineering, possible use in data exchange networks and local area networks.

SUBSTANCE: device contains N ≥ 2 client blocks, clock impulse generator, queue control block, OR element, AND-NOT element, selector-multiplexer, two N-input AND-NOT elements, two priority encoders.

EFFECT: increased trustworthiness of identification of number of queue of client requests under conditions, inherent in real process of computer system functioning - under conditions of ambiguousness of parameters of code, characterizing relation of request signal of certain client to queue of priorities of first or second order.

2 cl, 6 dwg

Description

The invention relates to the field of computer technology and can be used in data exchange systems and local area networks (LAN).

Known multi-channel device with dynamic priority change by av. St. USSR No. 1562912, G 06 F 9/46, 1990, bull. No. 17, containing N≥2 subscriber units, a counter, an AND element, a clock, a divider, a priority analysis unit and a priority building unit.

The disadvantage of this device is the relatively large time servicing requests of subscribers of a computing system with a low priority.

A device for servicing user requests of a computing system is known, comprising N≥2 subscriber units, a counter, an AND element, a clock generator, a divider, an N-input element OR NOT, a multiplexer and an inverter (see av. St. USSR No. 2140666, G 06 F 9/46, 1999, bull. No. 30).

However, this device has a relatively low reliability and low speed, due to the large number of interconnected elements included in its composition.

The closest in technical essence to the claimed device (prototype) is a device for servicing multi-priority requests of subscribers of a computing system (see RF patent No. 2186420, G 06 F 9/46, 2002, bull. No. 21), containing N≥2 subscriber units, generator clock pulses, the first and second N-input NAND elements, the first and second priority encoders, the OR element, the NAND element and the selector-multiplexer. The output of the clock generator is connected to the clock inputs of each of the N subscriber units. The request inputs and K-bit inputs "Maximum latency code" of each of the N subscriber units, where K≥2 is the length of the code for the maximum latency time for servicing requests, are the corresponding request inputs and K-bit inputs "Maximum latency code" of the device. The “Zero” inputs of each of the N subscriber units are the corresponding “Zero" inputs of the device. Each of the N inputs of the first and second N-input elements is NOT connected to the corresponding N inverse inputs of the first and second priority encoders, respectively. The outputs of the first and second N-input elements AND are NOT connected respectively to the second and first inputs of the OR element. Each n, n = 1, 2, ..., N, inverse input of the first and second priority encoders is connected respectively to the first and second signal output of the ((N + 1) -n) -th subscriber unit. The output of the OR element is connected to the second input of the AND-NOT element, the first input of which is the polling input of the device, and the output of the AND-NOT element is connected to the inverse enable input of the selector-multiplexer and is the enable output of the device. The control input of the selector-multiplexer is connected to the second input of the OR element. Each of J, where J =] log ₂ N [, the inverse outputs of the first and second priority encoders is connected to the corresponding J primary inputs and the corresponding J secondary inputs of the selector-multiplexer, and the J-bit output of the selector-multiplexer is a J-bit output "Code customer service "device.

The prototype implements the possibility of increasing speed and reliability by reducing the number of elements that make up the device for servicing different-priority requests of subscribers of a computer system.

However, the prototype has a drawback - the relatively low reliability of identifying the number of the request line of the subscriber in the conditions of ambiguity (ambiguity) of the code parameters characterizing the membership of the request signal of a particular subscriber in the priority queue of the first or second order. This device allows with high reliability to identify the request queue number, the code parameters of which are set quantitatively and take unambiguous, clearly identifiable values, while the vast majority of signals of different priority requests of many subscribers that simultaneously access the resources of a really functioning computing system are objectively in permanent the state of "collision" of requests, and their code parameters that determine the queue number can be identified only on a qualitative level (ambiguous, unclear) with the involvement of linguistic variable.

By “maintenance” is meant a set of actions of a computing system, including fetching a request from a queue, allocating a resource to it, as well as carrying out final operations. Request - sending a signal initiating a response. An input message containing a system requirement for a resource allocation.

“Priority” refers to the number assigned to a task, process, or operation that determines the order in which they are performed or serviced. The lower the number, the higher the priority level.

By "parameters of the request signal code" is meant initial data that allows us to characterize the belonging of the request signal of a particular subscriber to the first or second order queue - the set of parameters (numerical values of the characteristics of the properties) of the request signal code at a given time.

The purpose of the claimed technical solution is to create a device for servicing multi-priority subscriber requests of a computing system that provides increased reliability of identification of the number of the queue of subscribers' requests in the conditions of ambiguity (ambiguity) of the code parameters characterizing the membership of the request signal of a particular subscriber in the priority queue of the first or second order, a device capable of identify with certainty the number of the queue of subscribers' requests in the conditions inherent in real the entire process of functioning of a computing system - when the initial data that determine the choice of the queue number for a particular request have both quantitative and qualitative (ambiguous, fuzzy, involving a linguistic variable) expressed physical meaning.

This goal is achieved by the fact that in the known device for servicing multi-priority requests of subscribers of a computing system, comprising N≥2 subscriber units, a clock, the first and second N-input elements AND, the first and second priority encoders, the OR element, the And element NOT and a selector-multiplexer, J-bit output, where J =] log ₂ N [, which is the J-bit output "Subscriber code to be serviced" of the device, the output of the clock generator is connected to the clock inputs of each of N subscriber units shackles, request inputs and K-bit inputs “Code of maximum waiting time” of each of N subscriber units, where K≥2 is the capacity of the code of maximum time to wait for service requests, are the corresponding N request inputs and N K-bit inputs “Code of maximum waiting time "Device, inputs" Zeroing "of each of the N subscriber units are the corresponding inputs" Zeroing "of the device, each of the N inputs of the first and second N-input elements are NOT connected to the corresponding N inverse inputs, respectively As for the first and second priority encoders, the outputs of the first and second N-input NAND elements are connected respectively to the second and first inputs of the OR element, the output of which is connected to the second input of the NAND element, the first input of which is a polling input of the device, the output of the AND element - NOT connected to the inverse enable input of the selector-multiplexer and is the enable output of the device, the control input of the selector-multiplexer is connected to the second input of the OR element, each of the J inverse outputs of the first and second Priority fracers are connected to the corresponding J inputs of the first group of inputs and the corresponding J inputs of the second group of inputs of the selector-multiplexer; an additional queue control unit is also included. In this case, the n-th, where n = 1, 2, ..., N, the inverse input of the first priority encoder is connected to the ((N + 1) -n) -th output of the queue control unit, on which a request signal is generated for the queue of the first order, the n-th inverse input of the second priority encoder is connected to the ((N-1) -n) -th output of the queue control unit, on which a request signal is generated for the second-order queue. The first and second signal outputs of the nth subscriber unit are connected to the nth inputs of the queue control unit, at which request signals are generated for the queues, respectively, of the first and second orders.

The queue control unit consists of a first order queue controller, a second order queue controller, and a terminal queue controller. In this case, the N inputs of the first-order queue controller are the corresponding N inputs of the block on which request signals are generated for the first-order queue, N inputs of the second-order queue controller are the corresponding N inputs of the block on which request signals are generated for the second-order queue. The inhibitory input of the first order queue controller is connected to the enable output of the second order queue controller, the inhibitory input of which is connected to the enable output of the first order queue controller. Moreover, N outputs of the first order queue controller are connected to the corresponding N inputs of the first order queue of the terminal queue controller, N outputs of the second order queue controller are connected to the corresponding N inputs of the second order queue of the terminal queue controller, N outputs of the first order queue of the terminal queue controller are the corresponding N outputs of the block on which request signals are generated for the first order queue, and N outputs of the second order queue of the terminal queue controller are Xia respective N outputs of the queue control block, which signals are formed for the second-order requests queue.

Due to the new set of essential features, due to the introduction of a queue control unit that provides processing and transformation of fuzzy parameters of the request signal code to a form suitable for reliable identification of the subscriber's request queue number, the claimed device provides the possibility of preliminary analysis and verification of the request signal, which increase the reliability of identification queue numbers for multi-priority requests of multiple subscribers providing simultaneous access to the resource the actual functioning computing system under conditions of ambiguity (fuzziness) of the code parameters characterizing the membership of the request signal of a particular subscriber in the priority queue of the first or second order.

The analysis of the prior art made it possible to establish that analogues that are characterized by a combination of features identical to all the features of the claimed technical solution are absent, which indicates the compliance of the claimed device with the patentability condition of "novelty".

Search results for known solutions in this and related fields of technology in order to identify features that match the distinctive features of the claimed object from the prototype showed that they do not follow explicitly from the prior art. The prior art also did not reveal the popularity of the impact provided by the essential features of the claimed invention, the transformations on the achievement of the specified technical result. Therefore, the claimed invention meets the condition of patentability "inventive step".

The claimed device is illustrated by drawings, on which are presented:

figure 1 is a structural diagram of a device for servicing multi-priority requests of subscribers of a computing system,

figure 2 is a structural diagram of a control unit queue;

figure 3 is a structural diagram of a subscriber unit;

figure 4 - the structure of the computing system;

figure 5 - placement of request signals in the second order queue;

figure 6 - order transfer requests from the second order queue to the first order queue.

The device for servicing multi-priority subscriber requests of the computing system shown in Fig. 1 consists of N≥2 subscriber units 1 ₁ -1 _N (AB), a clock generator 2, a queue control unit 3, an OR element 4, an AND-NOT 5 element, selector-multiplexer 6, the first 7 and second 10 N-input elements NAND, the first 8 and second 9 priority encoders. In this case, J-bit, where J =] log ₂ N [, output 65 of the selector-multiplexer 6 is the J-bit output "Subscriber code to be serviced" of the device, the output 21 of the clock 2 is connected to the clock inputs 014 ₁ -014 _{N of} each of N subscriber units 1 ₁ -1 _N , request inputs 011 ₁ -011 _N and K-bit inputs "Code maximum latency" 012 ₁ -012 _{N of} each of N subscriber units 1 ₁ -1 _N , where K≥1 - bit depth code of the maximum waiting time for servicing requests, are the corresponding N request inputs and N K-bit inputs "Code maximum latency ”of the device. Inputs “Zeroing” 013 ₁ -013 _{N of} each of the N subscriber units 1 ₁ -1 _N are the corresponding N inputs “Zeroing” of the device. Each of the N inputs of the first 7 and second 10 N-input elements AND-NOT (respectively 71 ₁ -71 _N and 101 ₁ -101 _N ) are connected to the corresponding N inverse inputs (81 ₁ -81 _N and 91 ₁ -91 _N ), respectively first 8 and second 9 priority scramblers. The outputs of the first 7 and second 10 N-input NAND elements (72 and 102, respectively) are connected respectively to the second 42 and first 41 inputs of the OR element 4, the output of which 43 is connected to the second input 52 of the AND-NOT 5 element, the first input 51 of which is the polling input of the device. The output 53 of the AND-NOT 5 element is connected to the inverse enable input 61 of the selector-multiplexer 6 and is the enable output of the device. The control input 64 of the selector-multiplexer 6 is connected to the second input 42 of the OR element 4. Each of the J inverse outputs (82 ₁ -82 _J and 92 ₁ -92 _J, respectively) of the first 8 and second 9 priority encoders are connected to the corresponding J inputs 62 ₁ - 62 _{J of the} first group of inputs and corresponding J inputs 63 ₁ -63 _{J of the} second group of inputs of the selector-multiplexer 6. In this case, the n-th, where n = 1, 2, ..., N, the inverse input 81 _{n of the} first priority encoder 8 is connected to the ((N + 1) -n) -th output 31 _{(N + 1) -n} queue control unit 3, which is formed request signal to the first-order queue, n-s _n inverted input 91 of the second priority encoder 9 connected to the ((N + 1) -n) -th output 32 _{(N + 1) -n} queue control unit 3, which is formed by the request signal for the second-order queue. The first 015 _n and second 016 _n signal outputs of the n-th subscriber unit 1 _{n are} connected to the corresponding n-th inputs (35 _n and 36 _n ) of the control unit of queue 3, on which request signals are generated for the first and second order queues, respectively.

The number "N (N≥2)" (subscriber units, inputs, outputs, etc.) is determined in accordance with the possible number of subscribers of the computer system and, as a rule, ranges from 2 (two) to 50 (fifty). The number "K (K≥2)" characterizes the capacity of the code for the maximum waiting time for servicing subscriber requests and, as a rule, ranges from 2 (two) to 10 (ten).

Block control queue 3 (figure 2) is intended for preliminary analysis and verification of the request signal in the conditions of ambiguity (ambiguity) of the code parameters characterizing the membership of the request signal of a particular subscriber in the priority queue of the first or second order.

контроллера очереди первого порядка 3.1 подключен к разрешающему выходу М₂ контроллера очереди второго порядка 3.2, запрещающий вход

которого соединен с разрешающим выходом M₁ контроллера очереди первого порядка 3.1. Причем N выходов контроллера очереди первого порядка 3.1 подключены к соответствующим N входам 3.3-3₁-3.3-3_N очереди первого порядка оконечного контроллера очереди 3.3, N выходов контроллера очереди второго порядка 3.2 соединены с соответствующими N входами 3.3-4₁-3.3-4_N очереди второго порядка оконечного контроллера очереди 3.3, N выходов 3.3-1₁-3.3-1_N очереди первого порядка оконечного контроллера очереди 3.3 являются соответствующими N выходами 31₁-31_N блока 3, на которых формируются сигналы запросов для очереди первого порядка, а N выходов 3.3-2₁-3.3-2_N очереди второго порядка оконечного контроллера очереди 3.3 являются соответствующими N выходами 32₁-32_N блока контроля очереди 3, на которых формируются сигналы запросов для очереди второго порядка.Queue control unit 3 consists of a first-order queue controller 3.1, a second-order queue controller 3.2, and a terminal queue 3.3 controller. In this case, the N inputs of the first-order queue controller 3.1 are the corresponding N inputs 35 ₁ -35 _{N of} block 3, on which request signals are generated for the first-order queue, the N inputs of the second-order queue controller 3.2 are the corresponding N inputs 36 ₁ -36 _{N of} block 3, on which request signals are generated for the second order queue. Prohibition Entrance

first-order queue controller 3.1 is connected to the enable output M ₂ second-order queue controller 3.2, prohibiting entry

which is connected to the enable output M _{1 of the} first order queue controller 3.1. Moreover, the N outputs of the first-order queue controller 3.1 are connected to the corresponding N inputs 3.3-3 ₁ -3.3-3 _{N the} first-order queues of the terminal queue 3.3 controller, the N outputs of the second-order queue controller 3.2 are connected to the corresponding N inputs 3.3-4 ₁ -3.3-4 _N second-order queues of the terminal queue controller 3.3, N outputs 3.3-1 ₁ -3.3-1 _N first-order queues of the terminal queue 3.3 controller are the corresponding N outputs 31 ₁ -31 _{N of} block 3, on which request signals are generated for the first-order queue, and N outputs 3.3-2 ₁ -3.3-2 _N queues the second order of the terminal queue controller 3.3 are the corresponding N outputs 32 ₁ -32 _N of the control unit of the queue 3, on which request signals are generated for the second order queue.

, одним разрешающим выходом M₁, N информационными входами и выходами, где N может принимать значения от 2 до 50. Контроллер очереди первого порядка 3.1 может быть технически реализован в виде типового программируемого параллельного арифметико-логического устройства (АЛУ) на базе серийно выпускаемой программируемой КМОП-микросхемы серии 564 (например, ALU К564ИП3), как показано в работе [Шило В.Л. Популярные цифровые микросхемы. Справочник. - М.: Радио и связь, 1987. С.273-275, рис.2.70].The first-order queue controller 3.1 of the queue control unit 3 is designed to solve the problem of preliminary analysis, verification of the request signal and transforming fuzzy code parameters characterizing the membership of the request signal of a particular subscriber in the first-order priority queue, to a form suitable for reliable identification of the first-order queue for this subscriber request. The first order queue controller 3.1 is a programmable parallel arithmetic logic device with one inhibit input

, one enabling output M ₁ , N information inputs and outputs, where N can take values from 2 to 50. The first-order queue controller 3.1 can be technically implemented as a typical programmable parallel arithmetic logic device (ALU) based on a commercially available programmable CMOS microcircuits of the 564 series (for example, ALU K564IP3), as shown in [Shilo V.L. Popular digital circuits. Directory. - M.: Radio and Communications, 1987. S. 273-275, Fig. 2.70].

, одним разрешающим выходом М₂ и может быть технически реализован в виде типового программируемого параллельного АЛУ на базе серийно выпускаемой программируемой КМОП-микросхемы серии 564 (например, ALU К564ИП3), как описано в литературе [Шило В.Л. Популярные цифровые микросхемы. Справочник. - М.: Радио и связь, 1987. С.273-275, рис.2.70].The second-order queue controller 3.2 of the queue 3 control unit is designed to solve the problem of preliminary analysis, verification of the request signal and transforming fuzzy code parameters characterizing whether a particular subscriber's request signal belongs to the second-order priority queue to a form suitable for reliable identification of the second-order queue for this subscriber request. The second-order queue controller 3.1 is also a programmable parallel ALU with N information inputs and outputs, one inhibit input

, with one enabling output M ₂ and can be technically implemented in the form of a typical programmable parallel ALU based on a commercially available programmable CMOS chip of the 564 series (for example, ALU K564IP3), as described in the literature [Shilo V.L. Popular digital circuits. Directory. - M.: Radio and Communications, 1987. S. 273-275, Fig. 2.70].

The terminal queue controller 3.3 of the queue control block 3 is intended for an unambiguous decision (final verification) on whether the code of a particular request belongs to the request space of the priority queue of the first or second order. The terminal queue controller 33 is a commercially available programmable TTL comparator type 74LS85, described in [Jansen J. Digital Electronics Course: Complex ICs for data transmission devices. T.3. - M .: Mir, 1987. S.38-40, Fig.1.21].

Subscriber units 1 ₁ -1 _N , included in the general structural scheme, are designed to control the receipt of request signals, control the remaining waiting time, and also generate control signals after a specified waiting time for each request. The principle of operation and the structural diagram (figure 3) of any n-th battery (1 _n ) of N subscriber units are similar, known and described in detail in the prototype (see RF patent No. 2186420, G 06 F 9/46, 2002, bull. No. 21).

The clock generator 2, which is part of the general block diagram, is designed to generate a synchronizing sequence of pulses. Technical implementation of the clock generator 2 is possible on the basis of a commercially available clock generator described in [Shilo V.L. Popular digital circuits. Directory. - M .: Radio and communications, 1987. S.50-53].

The OR element 4, which is part of the general block diagram, is intended to combine the output signals of a certain logical level coming from the outputs of the first 7 and second 10 N-input elements AND. The OR element 4 can be technically implemented on the basis of a commercially available OR element, described in detail in [Gusev V.V., Lebedev ON, Sidorov A.M. Fundamentals of pulsed and digital technology. - St. Petersburg: SPVVIUS, 1995. S.24-26, Fig. 1.7].

The NAND 5 element, which is part of the general block diagram, is designed to generate low or high logic level signals and, respectively, enable or disable data transmission to the selector-multiplexer 6. The NAND 5 element can be technically implemented based on the commercially available NAND gate , as shown in [Gusev VV, Lebedev ON, Sidorov AM The basics of pulsed and digital technology - St. Petersburg: SPVVIUS, 1995. P.26-28, Fig. 1.9 (a)].

The selector-multiplexer 6, which is part of the general block diagram, is designed to switch either J inputs 62 ₁ -62 _{J of the} first group of inputs, or J inputs 63 ₁ -63 _{J of the} second group of inputs of the selector-multiplexer 6 to its J-bit output 65. Private the case of the technical implementation of the selector-multiplexer 6 is described in [Maltsev P. P., Dolidze N. S. and others. Digital integrated circuits: a reference. - M .: Radio and communications, 1994. S.34-35].

The first 7 and second 10 N-input NAND elements included in the general block diagram are similar in structure and principle of operation, designed to establish a high level of the output signal if there is at least one request signal in the queue (respectively, first and second order). The first 7 and second 10 N-input NAND elements can be technically implemented on the basis of a commercially available multi-input NAND input element, as shown in [Gusev V.V., Lebedev ON, Sidorov A.M. Fundamentals of pulsed and digital technology. - St. Petersburg: SPVVIUS, 1995. S.26-28, Fig. 1.9 (b)].

The first 8 and second 9 priority encoders included in the general structural scheme are similar in structure and operating principle, designed to convert a low-level signal at one of their inputs to a binary output code, and the conversion is carried out taking into account the priorities of the signals corresponding to the numbers of inputs. The first 8 and second 9 priority encoders can be technically implemented on the basis of commercially available encryptors, as shown in [Shilo V.L. Popular digital circuits. Directory. - M .: Radio and communications, 1987. S.147-148].

A device for servicing multi-priority requests of subscribers of a computing system operates as follows. It is known [1-5] that, within the framework of multiple access systems, from the point of view of identifying the number of the request queue of subscribers under ambiguity (ambiguity) of the code parameters characterizing the belonging of the request signal of a particular subscriber to the priority queue of the first or second order, there is the possibility of preliminary analysis and conversion (verification) of the request, the code of which is identified on the basis of both quantitatively and qualitatively (ambiguous, fuzzy, involving a linguistic variable) is observed Mykh parameters. This possibility is traditionally realized through successive transformations using fuzzy set theory methods that allow solving the problems of combining the opinions of experts whose knowledge is used in the form of pre-formed data on the possible values of the degree of membership of a particular request code in the request space of the first or second order priority queue.

In this case, one of the typical operations on fuzzy sets is used — the disjunctive summation operation [1-5]. The disjunctive sum, for example, of two fuzzy sets (according to the number of experts) is defined in terms of unions and intersections of fuzzy sets as follows:

- нечеткое множество, характеризующее мнение первого А (второго B) эксперта о степени принадлежности кода конкретного i-го сигнала запроса к пространству истинных (однозначно, четко определенных) запросов очереди приоритетов 1-го (первого) порядка;

- дополнения этих нечетких множеств;

- нечеткое множество, характеризующее мнение первого А (второго В) эксперта о степени принадлежности кода конкретного j-го сигнала запроса к пространству истинных (однозначно, четко определенных) запросов очереди приоритетов 2-го (второго) порядка;

- дополнения этих нечетких множеств. Полученные дизъюнктивные суммы

и

характеризуют соответственно объединенное мнение (в нашем случае двух, А и В) экспертов о значениях нечетких параметров кода, характеризующего принадлежность конкретного i-го и j-го сигналов запроса абонента к очереди приоритетов первого либо второго порядка. Для однозначной верификации принадлежности (либо не принадлежности) значения кода конкретного (i-го либо j-го) сигнала запроса к пространству истинных (однозначно, четко определенных) запросов очереди приоритетов первого либо второго порядка объединенное мнение экспертов анализируется на основе так называемой функции α-уровня, являющейся критерием однозначного выбора (присвоения) количественных значений для анализируемых нечетких параметров [1, 3, 5].Where

- a fuzzy set characterizing the opinion of the first A (second B) expert on the degree of belonging of the code of a particular i-th request signal to the space of true (unambiguously, clearly defined) requests of the priority queue of the 1st (first) order;

- additions to these fuzzy sets;

- a fuzzy set characterizing the opinion of the first A (second B) expert on the degree to which the code of a particular j-th request signal belongs to the space of true (unambiguously, clearly defined) requests of the priority queue of the 2nd (second) order;

- complements of these fuzzy sets. Disjunctive Amounts Received

and

respectively characterize the combined opinion (in our case, two, A and B) of experts on the values of fuzzy code parameters characterizing the membership of a particular i-th and j-th request signals of a subscriber in the priority queue of the first or second order. To unambiguously verify the membership (or non-membership) of the code value of a specific (i-th or j-th) request signal to the space of true (uniquely, clearly defined) requests of the priority queue of the first or second order, the combined opinion of experts is analyzed based on the so-called α- level, which is the criterion for the unambiguous selection (assignment) of quantitative values for the analyzed fuzzy parameters [1, 3, 5].

This α-level is set in advance as a threshold that determines the uniqueness of the value of a particular (i-th or j-th) request signal in the space of true (uniquely, clearly defined) requests of the priority queue, respectively, of the first or second order, and by the set of the α-level of the fuzzy set , characterizing the joint opinion of experts, is called the usual set:

Expression (3), for example, characterizes the fact that if the value of the membership function (degree of confidence) of the integrated expert opinion for the value of a particular ith request signal exceeds the α level or is equal to it, this request signal is uniquely verified, and this request is reliable belongs to the space of true (unambiguously, clearly defined) requests of the first-order priority queue.

The disjunctive summation of fuzzy sets considered and described in detail in [1-5] allows mathematically correct, within the framework of the real process of functioning of multiple access systems, verification of the signal code of a particular request of a subscriber of a computing system and thereby eliminating uncertainty (ambiguity, fuzziness) when making requests for service in the first or second order queue, and ultimately, increase the reliability of identification of the number of the queue of requests of subscribers in the condition s, inherent in the real process of functioning of the computing system, in the presence of unreliable (ambiguous, fuzzy) information about the true current values of the parameters of the requests of subscribers.

With this in mind, a reliable queue is formed for servicing multi-priority requests and the implementation of the needs of subscribers in the computing resource in the claimed device. Before starting the operation of the device from its K-bit inputs, the “Code of maximum latency” through K-bit inputs 012 ₁ -012 _{N of} subscriber units 1 ₁ -1 _N to the information inputs D ₁ -D _{K of} counters 1.1 ₁ -1.1 _N (see figure 3) the code values that specify the maximum waiting time for service requests. This ensures the initialization of the counters 1.1 ₁ -1.1 _N AB 1 ₁ -1 _N. Moreover, the smallest waiting time corresponds to the largest code, which is an addition to the maximum number represented in the K-bit code.

) через элемент ИЛИ 4 и элемент И-НЕ 5 установлен высокий логический уровень. Устройство готово к работе и ожидает сигналы запросов, вырабатываемые абонентами вычислительной системы (см. фиг.4).In the initial period when there are no service requests, low logic levels are set at all N request inputs of the device and at the corresponding request inputs 011 ₁ -011 _{N of} subscriber units 1 ₁ -1 _N Trehvhodovye elements and -1.3 _N 1.3 ₁ of AB are closed, the clock pulses from the clock pulse generator 2 via the AND trehvhodovye 1.3 ₁ -1.3 _N to counting inputs of counters Z ₁ 1.1 -1.1 _N AB 1 ₁ -1 _N is not received. From the side of the computing resource (computer, LAN) there is no signal about the release of the resource (a low logic level is set at the polling input of the device). The second 016 ₁ -016 _N and the first 015 ₁ -015 _N signal outputs AB 1 ₁ -1 _N set high logic levels. Accordingly, at the output 72 of the first N-input element AND-NOT 7 and the output 102 of the second N-input element AND-NOT 10 low logic levels are set. In this case, the 7-bit output 65 of the selector-multiplexer 6 is open, since at its inverse enable input 61 (

) through the element OR 4 and the element AND NOT 5 set a high logical level. The device is ready for operation and awaits request signals generated by subscribers of the computing system (see figure 4).

счетчиков 1.1₁-1.1_N через установленный интервал времени, определяемый кодами начального заполнения счетчиков и частотой тактовых импульсов.When a need arises for a computing resource, subscribers of the computing system generate request signals that are sent to the request service device and placed in a second-order queue. The request signal from the subscriber is considered a high level signal installed on any of the request inputs 011 ₁ -011 _{N of the} corresponding battery 1 ₁ -1 _N. At the same time, at the second signal outputs 016 ₁ -016 _{N of} these batteries through inverters 1.2 ₁ -1.2 _N , low-level signals will be established. The set of low-level signals at the second signal outputs 016 ₁ -016 _N AB forms a second-order queue. The position of the request signal in the second order queue is determined by its initial priority: the request signal received from the subscriber with the lowest number has the highest priority (see Fig. 5). The counting inputs Z of the counters 1.1 ₁ -1.1 _N АБ 1 ₁ -1 _N containing the request signals receive pulses from the output of 21 clock pulses 2 through the circuit: clock inputs 014 ₁ -014 _N АБ 1 ₁ -1 _N , open three-input elements And 1.3 ₁ -1.3 _N AB 1 ₁ -1 _N. The counters 1.1 ₁ -1.1 _{N of} each battery perform the function of timers that control the expiration of the allowable time for requests in the second order queue by summing the clock pulses arriving at their counting input Z and generate an overflow signal at the inverted outputs

counters 1.1 ₁ -1.1 _N after a set time interval determined by the codes for the initial filling of the counters and the frequency of the clock pulses.

контроллера очереди первого порядка 3.1 поступает в двоичном коде сигнал, запирающий контроллер очереди первого порядка 3.1.The signals from the second signal outputs 016 ₁ -016 _N АБ 1 ₁ -1 _N are supplied through the inputs 36 ₁ -36 _N for the second-order queue to the N inputs of the second-order queue controller 3.2 of the queue control unit 3, If any of the N inputs of the second priority controller of the order 3.2, a signal is received from the AB characterizing the subscriber’s request, previously (vaguely) identified as a second-order queue request requiring verification (verification), from the enable output M _{2 of the} second-order queue controller 3.2 to the inhibit input

first-order queue controller 3.1 receives a signal in binary code that locks the first-order queue controller 3.1.

In this case, in the second-order queue controller 3.2 of the queue 3 control unit, the procedure of converting the identifiable unreliable (fuzzy) code parameters that characterizes the belonging of the request signal of a particular subscriber to the second-order priority queue to a form suitable for reliable identification of the second-order queue for this subscriber request is carried out .

функции принадлежности значения конкретного j-го сигнала запроса к пространству истинных (однозначно, четко определенных) запросов очереди приоритетов 2-го (второго) порядка.The second-order queue controller 3.2 of the queue 3 control unit is technically implemented on the basis of a programmable (from the point of view of expert opinion for the value of the particular j-th request signal) parallel ALU that implements the computational algorithm of disjunctive summation, described in detail in [1-3] and corresponding to the expression ( 2). Thus, a programmable ALU (second-order queue controller 3.2), relying on the programmed values of membership functions characterizing expert opinions for the value of a particular j-th request signal, performs the calculation procedure in accordance with the computational algorithm of the disjunctive summation described by expression (2). Moreover, the N inputs (1, ..., N) of the programmable ALU (second-order queue controller 3.2) are equal N inputs of the disjunctive summation algorithm, to which the values of the code parameters that have the physical meaning of the second number of the request signal queue identified based on fuzzy source data. A set of direct and feedback connections, which takes place within the framework of the implementation of the disjunctive summation algorithm and is programmatically implemented within the framework of a programmable ALU (second-order queue controller 3.2), allows us to take into account membership functions formulated by experts and to obtain the final 3.2 second-order queue controller outputs values (general opinion of experts on the meaning)

the membership function of the value of a particular j-th request signal to the space of true (uniquely, clearly defined) requests of the priority queue of the 2nd (second) order.

In this case, the supply (and record for storage) in binary code to any nth, where n = 1, 2, ..., N, is the input of a second-order queue controller 3.2 (to any n-th ALU memory cell) code values, characterizing the request queue number, identified on the basis of fuzzy initial data, initiates the issuance in binary code from the nth output of the second-order queue controller 3.2 programmed, in accordance with the computational algorithm of the disjunctive summation described in [1-3], the values of mathematically correctly verified relatively reliable generalized expert opinion on the meaning of the queue number.

функции принадлежности значения конкретного j-го сигнала запроса к пространству истинных (однозначно, четко определенных) запросов очереди приоритетов 2-го (второго) порядка поступают на N вторичных входов 3.3-4₁-3.3-4_N оконечного контроллера очереди 3.3.From each of the N outputs of the second-order queue controller 3.2 total values (generalized opinion of experts on the value)

the membership functions of the value of the particular j-th request signal to the space of true (uniquely, clearly defined) requests of the priority queue of the 2nd (second) order are received at N secondary inputs 3.3-4 ₁ -3.3-4 _{N of the} terminal controller of the queue 3.3.

The terminal queue controller 3.3 makes an unambiguous decision (final verification) about whether a particular request code belongs to the request space of a priority queue of the first or second order [1, 3, 5] in accordance with expression (4). It is, in fact, a programmable comparison scheme (TTL-type comparator 74LS85), in which binary values are used to compare the values of a pre-entered (programmed) α-level of a second-order queue and pre-verified values of the membership function of a particular j the second request to the space of true (unambiguously, clearly defined) requests of the second-order priority queue, the terminal queue controller 3.3, by comparing the threshold (α-level) uniquely and ok thoroughly determines whether a given request belongs to a priority order of priority.

, полученное с выходов контроллера очереди второго порядка 3.2, для конкретного j-го запроса конкретного n-го, где n=1, 2, ..., N, абонента превышает α-уровень или равен ему, второй номер очереди является истинным, т.е. однозначно определенным, и оконечный контроллер очереди 33 выдает сигнал запроса n-го абонента на соответствующем n-ом своем выходе (выходе 3.3-2_n из 3.3-2₁-3.3-2_N), на котором формируется сигнал запроса для очереди первого порядка.If the value of the membership function (degree of confidence) of the integrated expert opinion

received from the outputs of the second-order queue controller 3.2 for a particular j-th request of a specific n-th, where n = 1, 2, ..., N, the subscriber exceeds the α level or is equal to it, the second queue number is true, t .e. uniquely determined, and the terminal queue controller 33 generates a request signal of the nth subscriber at its corresponding nth output (output 3.3-2 _n from 3.3-2 ₁ -3.3-2 _N ), on which a request signal is generated for the first-order queue.

If the α-level exceeds the value of the membership function (degree of confidence) of the integrated expert opinion obtained from the outputs of the second-order queue controller 3.2, for a particular j-th request of a specific n-th, where n = 1, 2, ..., N, of the subscriber , the second queue number for this request of the nth subscriber is false, i.e. this request should be placed in the first order queue. In this case, the terminal controller of queue 3.3 generates a request signal of the nth subscriber at its corresponding nth output (output 3.3-1 _n from 3.3-1 ₁ -3.3-1 _N ), on which a request signal is generated for the second-order queue.

Thus, at N outputs 3.3-2 ₁ -3.3-2 _{N of the} second order queue of the terminal controller of queue 3.3 and at the corresponding outputs 32 ₁ -32 _N of the control unit of queue 3, on which request signals are generated for the second order queue, we have reliable (verified ) query signals for a second-order queue obtained on the basis of a mathematically correct analysis of the integrated expert opinion in the framework of the apparatus of the theory of fuzzy sets.

Reliable (verified) request signals for the second-order queue from the outputs 32 ₁ -32 _N of the control unit of the queue 3, on which request signals are generated for the second-order queue, are supplied to the inverse inputs 91 ₁ -91 _{N of the} second priority encoder 9, which provides the conversion of request signals into a J-bit code corresponding to the AB number, taking into account its priority. The signal from the first output 32 _{1 of} block 3, on which the request signal is generated for the second-order queue, goes to the N-th inverse input 91 _{N of the} second priority encoder 9, the signal from the second output 32 _{2 of} block 3, on which the request signal is generated for second-order queue, fed to the (N-1) th inverse input 91 _{N-1 of the} second priority encoder 9, the signal from the n-th output 32 _{n of} block 3, on which the request signal is generated for the second-order queue, is sent to ((N +1) -n) -th inverse input 91 _{(N + 1) -n of the} second priority encoder 9, the signal from the N-th output 32 _N block 3, on which the request signal is generated for the second-order queue, is fed to the first inverse input 91 _{1 of the} second priority encoder 9. The specified method for connecting the outputs 32 ₁ -32 _N of the control unit of queue 3, on which request signals are generated for the second-order queue, due to the fact that the outputs 92 ₁ -92 _{J of the} second priority encoder 9 are inverse, that is, to obtain at its output a code corresponding to a specific n-th battery (1 _n ) with the lowest number from those batteries 1 ₁ -1 _N , on the second signal outputs 016 ₁ -016 _{N of} which (and hence the corresponding outputs 32 ₁ -32 _N of the control unit of the queue 3, on which request signals are generated for the second-order queue) low logic levels (request signals) are set, the outputs 32 ₁ -32 _N of the control unit of the queue 3, on which request signals are generated for second-order queues, to the inputs of the second priority encoder 9 in the reverse order. If there is at least one request signal in the verified second-order queue, a high level will be established at the output 102 of the second N-input AND-NOT 10 element.

As the computing resource (computer resource, LAN) is released, a high-level signal is generated that goes to the interrogation input of the device and then to the first input 51 of the AND-NOT element 5. If there is at least one request in the verified second-order queue at the output of the 53 AND element -NOT 5 a low level signal will be established that will allow data transmission to the selector-multiplexer 6. At the selective input 61 (input S) of the selector-multiplexer 6, a low level is set (at the first signal outputs 015 ₁ -015 _{N of} all batteries and at the corresponding outputs 31 ₁ -31 _{N of} block 3, on which request signals are generated for a first-order queue (high level), therefore, to J-bit, where J =] log ₂ N [, output 65 of selector-multiplexer 6 and to J-bit output “Subscriber code to be serviced” of the device, the code sent to the J inputs 62 ₁ -62 _{N of the} first group of inputs (inputs A ₁ -A _J ) of the selector-multiplexer 6 and corresponding to the lowest AB number containing the request signal from the second-order queue will be switched.

After satisfying the need for a computing resource, the n-th subscriber removes the request signal from the corresponding n-th request input of the device, from the request input 011 _{n of the} corresponding battery (1 _n ), and resets the counter 1.1 _{n of the} corresponding battery 1 _n at the n-th input " Zeroing ”the device and the“ Zeroing ”input 013 _{n of the} corresponding battery 1 _n . At the same time, the first and second signal outputs 015 _n and 016 _{n of the} corresponding battery 1 _n will have high levels.

, а следовательно, и на первых сигнальных выходах 015₁-015_N соответствующих АБ 1₁-1_N сигналов низкого уровня, что соответствует переносу запросов в очередь первого порядка на места, соответствующие их приоритетам (см. фиг.6), в целях их дальнейшего внеочередного, по отношению к очереди второго порядка, обслуживания. При этом запираются соответствующие трехвходовые элементы И 1.3₁-1.3_N (фиг.3), запрещая поступление тактовых импульсов на счетные входы Z соответствующих счетчиков 1.1₁-1.1_N. Совокупность сигналов низкого уровня на первых сигнальных выходах 015₁-015_N соответствующих АБ 1₁-1_N образует очередь первого порядка. Обслуживание запросов из очереди первого порядка осуществляется с учетом их начальных приоритетов.In the event that one or several requests as a result of the created queue have reached the maximum waiting time, there is an overflow of counters 1.1 ₁ -1.1 _{N of the} corresponding batteries 1 ₁ -1 _N , formation of overflow on their inverse outputs

and, therefore, at the first signal outputs 015 ₁ -015 _{N of the} corresponding AB 1 ₁ -1 _N low-level signals, which corresponds to transferring requests to the first-order queue to places corresponding to their priorities (see Fig. 6), in order to further extraordinary, in relation to the second-order queue, service. In this case, the corresponding three-input elements AND 1.3 ₁ -1.3 _N are locked (Fig. 3), prohibiting the arrival of clock pulses to the counting inputs Z of the corresponding counters 1.1 ₁ -1.1 _N. The set of low-level signals at the first signal outputs 015 ₁ -015 _{N of the} corresponding batteries 1 ₁ -1 _N forms a first-order queue. Requests from the first order queue are serviced taking into account their initial priorities.

The signals from the first signal outputs 015 ₁ -015 _N АБ 1 ₁ -1 _N are supplied through the inputs 35 ₁ -35 _N for the first-order queue to the N inputs of the first-order queue controller 3.1 of the priority control unit 3. In the first-order queue controller 3.1 of the queue control unit 3, the procedure of converting the identifiably identified (unclearly) code parameters characterizing the belonging of the request signal of a particular subscriber to the first-order priority queue to a form suitable for reliable identification of the first-order queue for This subscriber request. Similar to the procedure for verifying a second-order queue number, the terminal queue 3.3 controller makes an unambiguous decision (final verification) about whether a particular pre-verified first-order request code belongs to the request space of the first or second order priority queue in accordance with expression (3).

As a result, at N outputs 3.3-1 ₁ -3.3-1 _{N of the} first order queue of the terminal controller of queue 3.3 and at the corresponding outputs 31 ₁ -31 _N of the control unit of queue 3, on which request signals are generated for the first order queue, we have reliable (verified ) request signals for a first-order queue, obtained, as in the case of a second-order queue, based on a mathematically correct analysis of the integrated opinion of experts within the framework of the apparatus of the theory of fuzzy sets.

Reliable (verified) request signals for the first order queue from the outputs 31 ₁ -31 _N of the control unit of the queue 3, on which the request signals for the first order queue are generated, go to the inverse inputs 81 ₁ -81 _{N of the} first priority encoder 8. In this case, the code generation corresponding to the smallest AB number containing the request signal from the verified first-order queue is carried out by the first priority encoder 8 in the same manner as for the second-order queue. If there is a request in the first-order queue, their extraordinary, in relation to requests from the second-order queue, service is provided by a high-level signal at the output 72 of the first N-input AND-NOT 7 element, which, coming to the selective input 64 (input S) of the selector- multiplexer 6, switches to the J-bit output 65 of the selector-multiplexer 6 and to the J-bit output "Subscriber code to be serviced" of the device, the code received on the J inputs 63 ₁ -63 _{N of the} second group of inputs (inputs B ₁ -B _J ) of the selector multiplexer 6 and the corresponding smaller AB number containing the request signal from the first order queue. The high-level signal at the output 72 of the first N-input element AND-NOT 7 will be as long as there is at least one request in the verified first-order queue.

счетчика 1.1_n соответствующего АБ 1_n, что, в свою очередь, обуславливает установку на первом и втором сигнальных выходах 015_n и 016_n этого АБ 1_n высокие уровни. Это позволяет устройству после выполнения всех запросов с истекшим временем ожидания перейти к обслуживанию вновь поступивших либо ждущих своей очереди запросов в порядке, определенном логикой работы устройства.After releasing the resource allocated in the interests of the next request of the subscriber from the first-order queue (with the elapsed waiting time), each n-th subscriber removes the request signal from the request input 011 _{n of the} corresponding battery (1 _n ) and resets the counter 1.1 _{n of the} corresponding battery 1 _n on the nth input “Zeroing” the device and the input “Zeroing” 013 _n AB 1 _n . This predetermines a high level output.

the counter 1.1 _{n of the} corresponding battery 1 _n , which, in turn, causes the installation at the first and second signal outputs 015 _n and 016 _{n of} this battery 1 _n high levels. This allows the device, after all requests with an expired timeout, to proceed to service newly received or waiting for its turn requests in the order determined by the logic of the device.

Thus, in the framework of serving diverse priorities of subscribers of complex computing systems under ambiguity (ambiguity) of the code parameters characterizing the belonging of the request signal of a particular subscriber to the priority queue of the first or second order, at outputs 31 ₁ -31 _N , on which request signals are generated for the queue first order, and at outputs 32 ₁ -32 _N of the control unit of queue 3, on which request signals are generated for the second-order queue, we have reliable ones verified using m the mathematical apparatus of the theory of fuzzy sets, query signals for a queue, respectively, of the first or second order. The presence of these signals makes it possible to mathematically correctly and more reliably identify the number of the queue for servicing the subscriber in a complex (ambiguous) situation and has a well-defined physical meaning - the subscriber's request signal, identified in the conditions of ambiguity (ambiguity) of the code parameters characterizing this signal, is unambiguously recognized by the request signal first order queues or, conversely, second order queues.

An analysis of the principle of operation of the claimed device for servicing multi-priority requests of subscribers of a computing system shows the evidence of the fact that, along with the capabilities to improve speed and reliability stored and described in the prototype, the device is able to identify with high reliability the number of the queue of requests of subscribers in conditions inherent in the real process of functioning of a computing system - when the initial data, which determine the choice of the queue number for a particular request, have as Quantitative and qualitative (ambiguous, vague, with the assistance of the linguistic variable) pronounced physical sense.

This device provides increased reliability of identification of the number of the request queue of subscribers in the conditions of ambiguity (ambiguity) of the code parameters characterizing the belonging of the request signal of a particular subscriber to the priority queue of the first or second order, which significantly expands the scope of the device, expands the functionality of the queuing subsystems within the framework of exchange systems data and local area networks, where the claimed service device of different priorities APROSAM subscribers computing system will be used.

INFORMATION SOURCES

1. Kofman A. Introduction to the theory of fuzzy sets: Per. with french - M.: Radio and Communications, 1982, - 432 p.

2. Fuzzy sets and the theory of possibilities. Recent achievements: Per. from English / Ed. Yager P.P. - M .: Radio and communications, 1986, - 408 p.

3. Voronov M.V. Fuzzy sets in models of organizational management systems. - L .: VMA, 1988, - 54 p.

4. Martynov V.I. The mathematical foundations of managing primary communication networks using fuzzy parameters. - M .: "Elf-M", 1997, - 48 p.

5. Parashchuk I. B., Bobrik I. P. Fuzzy sets in the analysis of communication networks. - SPb .: VUS, 2001. - 80 p.

Claims (2)

1. A device for servicing multi-priority subscriber requests of a computing system, comprising N≥2 subscriber units, a clock, the first and second N-input NAND elements, the first and second priority encoders, the OR element, the NAND element and the selector multiplexer, J-bit output, where J =] log ₂ N [, which is the J-bit output "Subscriber code to be serviced" of the device, the output of the clock generator is connected to the clock inputs of each of the N subscriber units, request inputs and K-bit inputs " Code m the maximum latency "of each of the N subscriber units, where K≥2 is the capacity of the code for the maximum waiting time for servicing requests, are the corresponding N request inputs and N K-bit inputs" Code of the maximum waiting time "of the device, the inputs" Zeroing "of each of the N subscriber units blocks are the corresponding inputs "Zeroing" the device, each of the N inputs of the first and second N-input elements AND NOT connected to the corresponding N inverse inputs, respectively, of the first and second priority encoders, output The odes of the first and second N-input NAND elements are connected respectively to the second and first inputs of the OR element, the output of which is connected to the second input of the NAND element, the first input of which is a polling input of the device, the output of the NAND element is connected to an inverse enable input selector-multiplexer and is the enable output of the device, the control input of the selector-multiplexer is connected to the second input of the OR element, each of the J inverse outputs of the first and second priority encoders are connected to the corresponding J-inputs of the first group of inputs and corresponding J-inputs of the second group of inputs of the selector-multiplexer, characterized in that the queue control unit is additionally introduced, the n-th one, where n = 1, 2, ..., N, the inverse input of the first encoder of priorities is connected to the ((N + 1) -n) -th output of the queue control block, on which a request signal is generated for the first-order queue, the nth inverse input of the second priority encoder is connected to ((N + 1) -n) -m the output of the queue control unit, on which the request signal is generated for the second-order queue, the first and second gnalnye outputs n-th subscriber unit are connected to the n-th inputs of the queue control block, on which signals are generated requests for bursts of the first and second orders. 2. The service device for multi-priority requests of subscribers of a computing system according to claim 1, characterized in that the queue control unit consists of a first order queue controller, a second order queue controller and a terminal queue controller, wherein N inputs of the first order queue controller are corresponding N inputs of the block, on which request signals are generated for a first-order queue, N inputs of a second-order queue controller are the corresponding N block inputs on which signals are generated of requests for a second-order queue, prohibiting the input of a first-order queue controller is connected to the enable output of a second-order queue controller, a prohibiting input of which is connected to the enable output of a first-order queue controller, N outputs of a first-order queue controller are connected to the corresponding N inputs of a first-order queue of a terminal queue controller , N outputs of the second order queue controller are connected to the corresponding N inputs of the second order queue of the terminal queue controller, N in The outputs of the first order queue of the terminal queue controller are the corresponding N outputs of the block on which the request signals for the first order queue are generated, and the N outputs of the second order queue of the terminal queue controller are the corresponding N outputs of the queue control block on which the request signals for the second order queue are formed.

Images