RU2290684C1 - Device for servicing of various priority calls of computer system users - Google Patents

Abstract

FIELD: computer engineering, data exchange systems, local networks.

SUBSTANCE: device consists of N ≥ 2 users blocks, timing pulse generator, OR element, NAND element, selector-multiplexer, N input NAND elements, priorities encipherer, priorities analyzers, priorities authenticator.

EFFECT: increased authentication reliability of users, who generate call signals to computer system resources in the condition of real dynamics of functioning process of a data exchange system and local networks, that is uncertainty about real user number.

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Description

The invention relates to the field of computer technology and can be used in data exchange systems and local area networks (LAN).

Known multi-channel device with dynamic priority change by ed. St. USSR No. 1562912, G 06 F 9/46, 1990, bull. No. 17, containing N≥2 subscriber units, a counter, an AND element, a clock, a divider, a priority analysis unit and a priority building unit.

The disadvantage of this device is the relatively large time servicing requests of subscribers of a computing system with a low priority.

A device for servicing user requests of a computing system comprising N≥2 subscriber units, a counter, an I element, a clock generator, a divider, an N-input element OR NOT, a multiplexer and an inverter (see ed. St. USSR No. 2140666, G 06 F 9/46, 1999, bull. No. 30).

However, this device has a relatively low reliability and low speed, due to the large number of interconnected elements included in its composition.

The closest in technical essence to the claimed device (prototype) is a device for servicing multi-priority requests of subscribers of a computing system (see RF patent No. 2186420, G 06 F 9/46, 2002, bull. No. 21), containing N≥2 subscriber units, generator clock pulses, the first and second N-input NAND elements, the first and second priority encoders, the OR element, the NAND element and the selector-multiplexer. The output of the clock generator is connected to the clock inputs of each of the N subscriber units. The request inputs and K-bit inputs "Code of maximum latency" of each of the N subscriber units, where K≥2 is the capacity of the code of the maximum time to wait for service requests, are the corresponding request inputs and K-bit inputs of the Code maximum latency of the device. The “Zero” inputs of each of the N subscriber units are the corresponding “Zero" inputs of the device. Each of the N inputs of the first and second N-input elements is NOT connected to the corresponding N inverse inputs of the first and second priority encoders, respectively. The outputs of the first and second N-input elements AND are NOT connected respectively to the second and first inputs of the OR element. Each and, n = 1, 2, ..., N, inverse input of the first and second priority encoders are connected respectively to the first and second signal output of the ((N + 1) -n) -th subscriber unit. The output of the OR element is connected to the second input of the AND-NOT element, the first input of which is the polling input of the device, and the output of the AND-NOT element is connected to the inverse enable input of the selector-multiplexer and is the enable output of the device. The control input of the selector-multiplexer is connected to the second input of the OR element. Each of J, where J =] log ₂ N [, the inverse outputs of the first and second priority encoders are connected to the corresponding J primary inputs and the corresponding J secondary inputs of the selector-multiplexer, the J-bit output of the selector-multiplexer is a J-bit output "Subject code customer service "device.

The prototype implements the possibility of increasing speed and reliability by reducing the number of elements that make up the device for servicing different-priority requests of subscribers of a computer system.

However, the prototype has a drawback - the relatively low reliability of the authentication of the subscriber initiating the request signal during the simultaneous access of a large number of subscribers to the resources of a really functioning computing system in various conditions of a priori uncertainty, in particular, in the conditions of unreliability (insufficiency, incompleteness and inconsistency) of the results of determining the smallest number subscriber. This device allows with high reliability to serve the multi-priority requests of subscribers of the computing system in situations in which the subscriber is uniquely authenticated - the highest priority of the subscriber in the general stream of multi-priority requests is quantitatively set and consistent, while in the vast majority of situations that actually arise within the real process of functioning multiple access data exchange systems, the highest priority of the subscriber can be in the current time scale of recognition (defined) only qualitatively (at a qualitative level - unreliable, insufficient, incomplete), and in the dynamics of the functioning of the computer system reliable decisions about the lowest subscriber number (i.e., about his highest priority) in such situations are traditionally made based on mathematical methods of adoption solutions in poorly structured problems.

The “authentication” of the subscriber is understood as the dynamic recognition (determination) of the priority of the subscriber - making a decision on the lowest number of the subscriber in the dynamics of the functioning of the computer system (in real time), taking into account the possible redistribution of priorities, change of authority and other destabilizing factors.

By “maintenance” is meant a set of actions of a computing system, including fetching a request from a queue, allocating a resource to it, as well as carrying out final operations. Request - sending a signal initiating a response. An input message containing a system requirement for a resource allocation.

“Priority” refers to the number assigned to a task, process, or operation that determines the order in which they are performed or serviced. The lower the number, the higher the priority level.

The aim of the invention is to provide a device for servicing multi-priority requests of subscribers of a computer system, which provides increased reliability of authentication of subscribers generating request signals to resources of a computer system under conditions inherent in the real dynamics of the functioning of data exchange and LAN systems, i.e. in conditions of uncertainty (inaccuracy, insufficiency, incompleteness and inconsistency) of data on the true number of the subscriber, a device capable of determining the priority of the subscriber in the current time scale, the number of which can be recognized both quantitatively and qualitatively - unreliable, insufficient, incomplete.

This goal is achieved by the fact that in the known device for servicing multi-priority requests of subscribers of a computing system, comprising N≥2 subscriber units, a clock, the first and second N-input elements AND, the first and second priority encoders, the OR element, the And element NOT and a selector-multiplexer, J-bit, where J =] log ₂ N [, the output of which is the J-bit output "Subscriber code to be serviced" of the device, the output of the clock generator is connected to the clock inputs of each of N subscriber units shackles, request inputs and K-bit inputs “Code of maximum waiting time” of each of N subscriber units, where K≥2 is the capacity of the code of maximum time to wait for service requests, are the corresponding N request inputs and N K-bit inputs “Code of maximum waiting time "Device, inputs" Zeroing "of each of the N subscriber units are the corresponding N inputs" Zeroing "of the device, N inputs of the first and second N-input elements are NOT connected to the corresponding N inverse inputs, respectively of the second and second priority encoders, the outputs of the first and second N-input elements AND are NOT connected respectively to the second and first inputs of the OR element, the output of which is connected to the second input of the AND gate, the first input of which is a polling input of the device, the output of the And NOT connected to the inverse enable input of the selector-multiplexer and is the enable output of the device, the control input of the selector-multiplexer is connected to the second input of the OR element, the nth inverse inputs of the first and second encoders are priority s, where n = 1, 2, ..., N, are connected respectively to the first and second signal outputs of the ((N + 1) -n) -th subscriber unit, the first and second priority analyzers for preliminary data analysis are additionally included about the true priority of the subscriber for the queue of multi-priority requests of the first and second order, respectively, and a priority authenticator designed to record, store the results of the analysis of priorities and mathematically correct verification of the subscriber with the highest priority, by converting the ambiguously identified source data characterizing the priority of subscribers to a form suitable for unambiguous adoption of a reliable decision about the priority level of a particular subscriber of a computing system. Moreover, each of the J inverse outputs of the first and second priority encoders are connected to the J inputs of the first and second priority analyzers, respectively, whose J-bit outputs are connected to the second and first J-bit inputs of the priority authenticator, respectively. The control outputs of the first and second priority analyzers are connected respectively to the second and first control inputs of the priority authenticator, the first group of J outputs and the second group of J outputs of which are connected to the first and second groups of information inputs of the selector-multiplexer, respectively, and connected to the groups of direct outputs J, respectively second and first priority analyzers.

The first priority analyzer consists of a first selector and a first converter for registering data characterizing the priority of subscribers for a first-order queue and converting this data from parallel to serial code. Moreover, the J-bit output of the first converter is the J-bit output of the first priority analyzer, the transmission output of the first converter is the control output of the first priority analyzer, the enable output of the first converter is connected to the inverse enable input of the first selector, the J outputs of which are a group of corresponding J direct outputs of the first priority analyzer. The inhibitory input of the first converter is connected to the inhibitory output of the first selector, the J inputs of which are connected to the corresponding J inputs of the first converter and are the corresponding J inputs of the first priority analyzer.

The second priority analyzer consists of a second selector and a second converter designed to register data characterizing the priority for the second order queue and convert this data from parallel to serial code. In this case, the J-bit output of the second converter is the J-bit output of the second priority analyzer, the transmission output of the second converter is the control output of the second priority analyzer, the enable output of the second converter is connected to the inverse enable input of the second selector, J outputs of which are a group of corresponding J direct outputs of the second priority analyzer. The inhibitory input of the second converter is connected to the inhibitory output of the second selector, the J inputs of which are connected to the corresponding J inputs of the second converter and are the corresponding J inputs of the second priority analyzer.

The priority authenticator consists of a programmable computer, the first and second storage elements intended for recording and storing a code containing verified results of priority analysis - a code corresponding to the lowest number of the subscriber unit containing the request signal from the queue, respectively, of the second and first order. In this case, the J-bit input I and the J-bit input E of the programmable calculator are, respectively, the first and second J-bit inputs of the priority authenticator, the enable input of outputs A and the input of the resolution of the outputs B of the programmable computer are the first and second control inputs of the priority authenticator, J outputs, respectively A and J outputs B of the programmable computer are connected respectively to the J inputs of the first and J inputs of the second storage elements. Moreover, the J outputs of the first and J outputs of the second storage elements are the corresponding J outputs of the first and second groups of outputs of the priority authenticator J, respectively.

Thanks to a new set of essential features, by introducing the first and second priority analyzer, which, respectively, provide analysis of data on the true subscriber number for the first and second order queues, from the point of view of reliability of recognizing the priority of the subscriber and by introducing the priority authenticator, which provides mathematically correct support making (in the dynamics of the functioning of the computing system) a reliable decision about the lowest subscriber number (i.e., about his highest priority), in The claimed device achieves the possibility of preliminary analysis and verification of the subscriber’s number, which leads to an increase in the authenticity of authentication of subscribers in conditions inherent in the real dynamics of the functioning of data exchange systems and LANs - in conditions of inaccuracy (insufficiency, incompleteness, and often inconsistency) of data characterizing the priority of a particular subscriber when serving multi-priority requests.

The analysis of the prior art made it possible to establish that analogues that are characterized by a combination of features identical to all the features of the claimed technical solution are absent, which indicates the compliance of the claimed device with the patentability condition of "novelty".

Search results for known solutions in this and related fields of technology in order to identify features that match the distinctive features of the claimed object from the prototype showed that they do not follow explicitly from the prior art. The prior art also did not reveal the popularity of the impact provided by the essential features of the claimed invention, the transformations on the achievement of the specified technical result. Therefore, the claimed invention meets the condition of patentability "inventive step".

The claimed device is illustrated by drawings, on which are presented:

figure 1 is a structural diagram of a device for servicing multi-priority requests of subscribers of a computing system;

figure 2 is a structural diagram of a first priority analyzer;

figure 3 is a structural diagram of a second priority analyzer;

figure 4 is a structural diagram of a priority authenticator;

figure 5 is a structural diagram of a subscriber unit;

figure 6 - structure of the computing system;

Fig.7 - the placement of request signals in the second order queue;

on Fig - order transfer requests from the second order queue to the first order queue.

The device for servicing multi-priority subscriber requests of the computing system shown in Fig. 1 consists of N≥2 subscriber units 1 ₁ -1 _N (AB), a clock generator 2, an OR element 4, an NAND 5 element, a selector-multiplexer 6, the first 7 and second 10 N-input elements NAND, the first 8 and second 9 priority encoders, the first 11 and second 12 priority analyzers, the priority authenticator 13. Moreover, J-bit, where J =] log ₂ N [, output 65 selector-multiplexer 6 is a J-bit output "Code subject to service subscriber enta "device. The output 21 of the clock 2 is connected to the clock inputs 014 ₁ -014 _{N of} each of N subscriber units 1 ₁ -1 _N , the request inputs 011 ₁ -011 _N and K-bit inputs "Code maximum latency" 012 ₁ -012 _N each of N subscriber units 1 ₁ -1 _N , where K≥2 is the capacity of the code for the maximum waiting time for service requests, are the corresponding N request inputs and N K-bit inputs "Code maximum waiting time" of the device. Inputs “Zeroing” 013 ₁ -013 _{N of} each of the N subscriber units 1 ₁ -1 _N are the corresponding N inputs “Zeroing” of the device. Each of the N inputs of the first 7 and second 10 N-input elements AND-NOT (respectively 71 ₁ -71 _N and 101 ₁ -101 _N ) are connected to the corresponding N inverse inputs (81 ₁ -81 _N and 91 ₁ -91 _N ), respectively first 8 and second 9 priority scramblers. The outputs of the first 7 and second 10 N-input NAND elements (72 and 102, respectively) are connected respectively to the second 42 and first 41 inputs of the OR element 4, the output of which 43 is connected to the second input 52 of the AND-NOT 5 element, the first input 51 of which is the polling input of the device. The output 53 of the AND-NOT 5 element is connected to the inverse enable input 61 of the selector-multiplexer 6 and is the enable output of the device. The control input 64 of the selector-multiplexer 6 is connected to the second input 42 of the OR element 4. Moreover, the nth, where n = 1, 2, ..., N, are inverse inputs (respectively, the n-th input is 81 _n out of 81 ₁ -81 _N and n-th input 91 _n of 91 ₁ -91 _N ) of the first 8 and second 9 priority encoders are connected respectively to the first 015 _{(N-1) n} and second 016 _{(N + 1) -n} signal outputs ((N + 1 ) -n) -th subscriber unit 1 _{(N-1) -n} . Each of the J inverse outputs (82 ₁ -82 _J and 92 ₁ -91 _J, respectively) of the first 8 and second 9 priority encoders are connected to the J inputs (111 ₁ -111 _J and 121 ₁ -121 _J ) of the first 11 and second 12 analyzers, respectively priorities, J-bit outputs 112 and 122 of which are connected respectively to the second 132 and first 131 J-bit inputs of the priority authenticator 13. The control outputs 114 and 124 of the first 11 and second 12 priority analyzers are connected to the second 136 and first 135 control inputs of the priority authenticator, respectively 13. In this case, the J outputs of the first 133 ₁ -1 33 _J and second 134 ₁ -134 _J groups of J outputs of the priority authenticator 13 are connected to the corresponding J inputs of the first 62 ₁ -62 _J and second 63 ₁ -63 _{J of} groups J of the information inputs of the selector-multiplexer 6, respectively, and connected to the corresponding J direct outputs ( 123 ₁ -123 _J and 113 ₁ -113 _J ) groups J of direct outputs of the second 12 and first 11 priority analyzers, respectively.

The number "N, (N≥2)" (subscriber units, inputs, outputs, etc.) is determined in accordance with the possible number of subscribers of the computer system and, as a rule, ranges from 2 (two) to 50 (fifty). The number "K, (K≥2)" characterizes the capacity of the code for the maximum waiting time for servicing subscriber requests and, as a rule, ranges from 2 (two) to 10 (ten).

первого селектора 11.1, J выходов которого являются соответствующими J прямыми выходами группы J прямых выходов 113₁-113_J первого анализатора приоритетов 11. Запрещающий вход DST первого преобразователя 11.2 подключен к запрещающему выходу МТ первого селектора 11.1, J входов которого соединены с соответствующими J входами первого преобразователя 11.2 и являются соответствующими J входами 111₁-111_J первого анализатора приоритетов 11.The first priority analyzer 11 (Fig. 2) is intended for preliminary analysis of data on the true number (priority) of a subscriber for a queue of first-priority requests of different priorities. The first priority analyzer 11 consists of a first selector 11.1 and a first converter 11.2, the J-bit output of which is the J-bit output 112 of the first priority analyzer 11. The transmission output T × D of the first converter 11.2 is the control output 114 of the first priority analyzer 11. The DSR enable output the first converter 11.2 is connected to an inverse enable input

the first selector 11.1, the J outputs of which are the corresponding J direct outputs of the group J of the direct outputs 113 ₁ -113 _{J of the} first priority analyzer 11. The inhibit input DST of the first converter 11.2 is connected to the inhibit output MT of the first selector 11.1, the J inputs of which are connected to the corresponding J inputs of the first Converter 11.2 and are the corresponding J inputs 111 ₁ -111 _{J of the} first priority analyzer 11.

The first selector 11.1 of the first priority analyzer 11 is designed to perform the selection of data on the true number (priority) of the subscriber for a queue of different priority requests of the first order and decide on the mathematical nature of this data - data characterizing the priority of a particular subscriber is defined (recognized) unambiguously or ambiguously (not valid , incomplete) and need verification. The first selector 11.1 can be technically implemented as a commercially available selector on KMDP structures with one inverse enable input and one inhibit output, based on the 564 series integrated circuit (for example, SEL K564KP2), as shown in the literature [P. Maltsev, Dolidze N.S. et al. Digital Integrated Circuits: A Guide. - M .: Radio and communications, 1994. S. 28-33].

The first converter 11.2 of the first priority analyzer 11 is intended for recording data characterizing the priority of subscribers for a queue of first-priority requests of different priorities and converting this data from parallel to serial code. The first converter 11.2 can be technically implemented in the form of a universal programmable synchronous-asynchronous transceiver based on the PCI integrated circuit КР580IK51 described in [Grishin G.G., Moshkov A.A., Olshansky O.V. and other Microprocessors: A reference guide for developers of ship REA. 2nd ed. - L .: Shipbuilding, 1988. S. 66-74, Fig. 3.14].

второго селектора 12.1, J выходов которого являются соответствующими J прямыми выходами группы J прямых выходов 123₁-123_J второго анализатора приоритетов 12. Запрещающий вход DST второго преобразователя 12.2 подключен к запрещающему выходу МТ второго селектора 12.1, J входов которого соединены с соответствующими J входами второго преобразователя 12.2 и являются соответствующими J входами 121₁-121_J второго анализатора приоритетов 12.The second priority analyzer 12 (Fig. 3) is intended for preliminary analysis of data on the true number (priority) of a subscriber for a queue of second-priority requests of different priorities. The second priority analyzer 12 consists of a second selector 12.1 and a second converter 12.2, the J-bit output of which is the J-bit output 122 of the second priority analyzer 12. The transmission output T × D of the second converter 12.2 is the control output 124 of the second priority analyzer 12. The DSR enable output the second converter 12.2 is connected to an inverse enable input

the second selector 12.1, the J outputs of which are the corresponding J direct outputs of the group J of the direct outputs 123 ₁ -123 _{J of the} second priority analyzer 12. The inhibit input DST of the second converter 12.2 is connected to the inhibit output MT of the second selector 12.1, the J inputs of which are connected to the corresponding J inputs of the second Converter 12.2 and are the corresponding J inputs 121 ₁ -121 _{J of the} second priority analyzer 12.

The second selector 12.1 of the second priority analyzer 12 is designed to perform the procedure of selecting data on the true number (priority) of the subscriber for a queue of second-priority queries of different priorities and deciding on the mathematical nature of this data - data characterizing the priority of a particular subscriber is defined (recognized) unambiguously or ambiguously ( unreliable, incomplete) and need verification. The second selector 12.1 is a commercially available selector on KMDP structures with one inverse enable input and one inhibit output, implemented on the basis of the 564 series integrated circuit (for example, SEL K564KP2), as shown in the literature [P. Maltsev, I. Dolidze I. S. and others. Digital integrated circuits: a reference. - M .: Radio and communications, 1994. S. 28-33].

The second converter 12.2 of the second priority analyzer 12 is intended for recording data characterizing the priority of subscribers for a queue of second-priority requests of different priorities and converting this data from parallel to serial code. The technical implementation of the second converter 12.2 can be implemented in the form of a typical universal programmable synchronous-asynchronous transceiver based on the PCI integrated circuit КР580IK51, described in [Grishin G.G., Moshkov A.A., Olshansky O.V. and other Microprocessors: A reference guide for developers of ship REA. 2nd ed. - L .: Shipbuilding, 1988. S. 66-74, Fig. 3.14].

Priority authenticator 13, the structural diagram of which is shown in Fig. 4, is intended for recording, storing the results of priority analysis and mathematically correct verification of the lowest subscriber number (verification of the subscriber with the highest priority) by converting certain (recognized) ambiguously (inaccurate, incomplete) source data, characterizing the priority of subscribers, to a form suitable for unambiguous adoption of a reliable decision about the priority level of a particular subscriber of a computing system.

The priority authenticator 13 consists of a programmable computer 13.1, the first 13.2 and the second 13.3 storage elements. Moreover, the J-bit input I and the J-bit input E of the programmable calculator 13.1 are respectively the first 131 and second 132 J-bit inputs of the priority authenticator 13. The input OE _I enable outputs A and the input OE _E enable outputs B of programmable calculator 13.1 are respectively the first 135 and the second 136 control inputs of the priority authenticator 13, J outputs A (A ₁ -A _J ) and J outputs B (B ₁ -B _J ) of the programmable calculator 13.1 are connected respectively to the J inputs 13.2-1 ₁ -13.2-1 _{J of the} first 13.2 and J inputs 13.3-1 ₁ -13.3-1 _{J of the} second 13.3 memory items. Moreover, J outputs 13.2-2 ₁ -13.2-2 _{J of the} first 13.2 and J outputs 13.3-2 ₁ -13.2-2 _{J of the} second 13.3 memory elements are the corresponding J outputs respectively of the first 133 ₁ -133 _J and the second 134 ₁ -134 _{J of} groups J Priority authenticator outputs 13.

The programmable calculator 13.1 of the priority authenticator 13 is intended for the implementation of the procedure for converting certain (recognized) ambiguously (inaccurate, incomplete) source data characterizing the priority of subscribers to a form suitable for unambiguous adoption of a reliable decision about the priority level of a particular subscriber.

Programmable computer 13.1 is a commercially available microprocessor section (MPS or MPS - Micro-Processingoring Section) type MPS K1804BC1, described in detail in [Grishin G.G., Moshkov A.A., Olshansky O.V. and other Microprocessors: A reference guide for developers of ship REA. 2nd ed. - L .: Shipbuilding, 1988. S. 243-281, Fig. 7.1 and 7.2]. Programmable calculator 13.1 in the form of a microprocessor section MPS K1804BC1 is used as a programmable parallel arithmetic logic unit (ALU), which has the ability to increase bit capacity and has two J-bit inputs, where J =] log ₂ N [, two inputs enable outputs and two groups of outputs on J exits in each group.

The first 13.2 and second 13.3 storage elements of the priority authenticator 13 are similar in structure, function and are used to record and store a code containing verified results of priority analysis - the code corresponding to the lowest AB number containing a request signal from the queue, respectively, of the second and first order. The first 13.2 and second 13.3 storage elements can be technically implemented on the basis of a commercially available programmable storage device with J inputs and J outputs in accordance with the description presented in [Gusev V.V., Lebedev ON, Sidorov A.M. Fundamentals of pulsed and digital technology. - SPb .: SPVVIUS, 1995. S.197-199, Fig. 6.10].

Subscriber units 1 ₁ -1 _N , included in the general structural scheme, are designed to control the receipt of request signals, control the remaining waiting time, and also generate control signals after a specified waiting time for each request. The principle of operation and the structural diagram (figure 5) of any n-th battery (1 _n ) of N subscriber units are similar, known and described in detail in the prototype (see RF patent No. 2186420, G 06 F 9/46, 2002, bull. No. 21).

The clock generator 2, which is part of the general block diagram, is designed to generate a synchronizing sequence of pulses. Technical implementation of the clock generator 2 is possible on the basis of a commercially available clock generator described in [Shilo V.L. Popular digital circuits. Directory. - M .: Radio and communications, 1987. S.50-53].

The OR element 4, which is part of the general block diagram, is intended to combine the output signals of a certain logical level coming from the outputs of the first 7 and second 10 N-input elements AND. The OR element 4 can be technically implemented on the basis of a commercially available OR element, described in detail in [Gusev V.V., Lebedev ON, Sidorov A.M. Fundamentals of pulsed and digital technology. - St. Petersburg: SPVVIUS, 1995. S.24-26, Fig. 1.7].

The NAND 5 element, which is part of the general block diagram, is designed to generate low or high logic level signals and, respectively, enable or disable data transmission to the selector-multiplexer 6. The NAND 5 element can be technically implemented based on the commercially available NAND gate , as shown in [Gusev VV, Lebedev ON, Sidorov AM Fundamentals of pulsed and digital technology. - St. Petersburg: SPVVIUS, 1995. S.26-28, Fig. 1.9 (a)].

The selector-multiplexer 6, which is part of the general block diagram, is designed to switch either J primary 62 ₁ -62 _J or J secondary 63 ₁ -63 _J inputs of the selector-multiplexer 6 to its J-bit output 65. A special case of the technical implementation of the selector-multiplexer 6 is described in [Maltsev P.P., Dolidze N.S. and others. Digital integrated circuits: a reference. - M .: Radio and communications, 1994. S.34-35].

The first 7 and second 10 N-input NAND elements included in the general block diagram are similar in structure and principle of operation, designed to establish a high level of the output signal if there is at least one request signal in the queue (respectively, first and second order). The first 7 and second 10 N-input NAND elements can be technically implemented on the basis of a commercially available multi-input NAND input element, as shown in [Gusev V.V., Lebedev ON, Sidorov A.M. Fundamentals of pulsed and digital technology. - St. Petersburg: SPVVIUS, 1995. S.26-28, Fig. 1.9 (b)].

The first 8 and second 9 priority encoders included in the general structural scheme are similar in structure and operation principle, designed to convert a low-level signal at one of their inputs into a binary code at the output, and the conversion is carried out taking into account the preliminary priorities of the signals corresponding to the initial ones ( not verified) input numbers. The first 8 and second 9 priority encoders can be technically implemented on the basis of commercially available encryptors, as shown in [Shilo V.L. Popular digital circuits. Directory. - M .: Radio and communications, 1987. S.147-148].

A device for servicing multi-priority requests of subscribers of a computing system operates as follows. It is known [1-5] that from the point of view of the subscriber’s verification with the highest priority, it is possible to recognize (determine) the data characterizing the priority of subscribers defined both quantitatively and qualitatively (unreliably, incompletely, contradictory). This feature is implemented using neural network computing methods and algorithms that allow, through successive neural network data transformations characterizing the priority of subscribers, to switch from unreliable (insufficient, incomplete) recognized (defined) data to a type of data suitable for making an unambiguous reliable decision about the priority level specific subscriber computing system.

Moreover, the initial number (priority) of the subscriber, under whom he requested the resource of the computing system, can be verified on the basis of mathematical decision-making methods in poorly structured problems - neural network computing methods and algorithms that can be quite easily implemented in hardware.

Neural network computing methods and algorithms are based on expert estimates, and to solve the problem of combining the opinions of experts whose knowledge is used to verify the priority of the subscriber, one of the typical computing algorithms of the theory of neural networks is used - a neural network extrapolating computational algorithm or the so-called extrapolating neural network (ENS) , which is a kind of well-known computational models of associative memory [1-5].

A computational neural network algorithm (extrapolating neural network) of this class consists of two layers of calculators (neurons) - the input layer S _a and the output layer S _b . The input layer S _a is composed of J _Rin neurons possessing a set of forward and reverse links with J _O output layer neurons S _b, wherein the number of input and output images of J equal (J = J _Bx = J _O =] log ₂ N [) and depends from the number of experts and the corresponding number of device inputs of the hardware implementation of the neural network algorithm. In our case, J can take values from 2 (two) to 20 (twenty), corresponding to the number of inputs of the microprocessor section MPS K1804BC1, on the basis of which the programmable calculator 13.1 of the priority authenticator 13 is built.

The so-called cognitive map is used in the ENS, which is completely defined by the matrix of connections and characterizes the cause-effect relations of the current priorities of the subscribers, which influence the adoption in the device of a reliable decision about the priority level of a particular subscriber of the computing system. The cognitive map is formulated by experts, the principle of forming cognitive maps is described in detail in [2, 3]. Moreover, the J branches of the algorithm are responsible for converting the opinions of experts on unreliably (incompletely) recognized (defined) priorities of subscribers to a form suitable for unambiguous recognition of priority.

An input image is received at the input of a computational neural network algorithm (ENS) - data characterizing the priority of subscribers and recognized (defined) both quantitatively and qualitatively (unreliable, incomplete, contradictory). It is determined which of the data characterizing the priority of subscribers at a given time is quantified, and which data is identified indefinitely (unreliably, inaccurately). In order to verify the subscriber with the highest priority, it is necessary, mathematically correct, using the ENS, to convert the data recognized inaccurately (incompletely).

The stages of functioning of a computational neural network algorithm (ENS) are described in detail, algorithmically and analytically in [3].

At the output of the computational neural network algorithm (ENS) we have an output image - data that completely (reliably) characterizes the integrated opinion of experts about the priority of a particular subscriber belonging to the space of reliable, verified priorities of the highest order.

The computational neural network algorithm considered in [1, 2, 5] and described in detail in [3] makes it possible to eliminate the uncertainty (inaccuracy, incompleteness) of data characterizing the priority of subscribers, it makes it possible to unambiguously recognize (verify) the true priority of a particular subscriber at the current time, and in ultimately, to increase the reliability of subscriber authentication in conditions inherent in the real dynamics of the process of functioning of data exchange systems and LANs - in conditions of uncertainty (unreliability, insufficiency, incompleteness and inconsistency) of data about the true number of the subscriber.

With this in mind, reliable authentication (priority recognition) is carried out and, in accordance with the verified priority, the implementation of the needs of subscribers in the computing resource in the claimed device. Before starting the operation of the device from its K-bit inputs, the “Code of maximum latency” through K-bit inputs 012 ₁ -012 _{N of} subscriber units 1 ₁ -1 _N to the information inputs D ₁ -D _{K of} counters 1.1 ₁ -1.1 _N (see 5) code values are supplied that specify the maximum waiting time for service requests. This ensures the initialization of the counters 1.1 ₁ -1.1 _N AB 1 ₁ -1 _N. Moreover, the smallest waiting time corresponds to the largest code, which is an addition to the maximum number represented in the K-bit code.

) через элемент ИЛИ 4 и элемент И-НЕ 5 установлен высокий логический уровень. Устройство готово к работе и ожидает сигналы запросов, вырабатываемые абонентами вычислительной системы (см. фиг.6).In the initial period when there are no service requests, low logic levels are set at all N request inputs of the device and at the corresponding request inputs 011 ₁ -011 _{N of} subscriber units 1 ₁ -1 _N Trehvhodovye elements and -1.3 _N 1.3 ₁ of AB are closed, the clock pulses from the clock pulse generator 2 via the AND trehvhodovye 1.3 ₁ -1.3 _N to counting inputs of counters Z ₁ 1.1 -1.1 _N AB 1 ₁ -1 _N is not received. From the side of the computing resource (computer, LAN) there is no signal about the release of the resource (a low logic level is set at the polling input of the device). The second 016 ₁ -016 _N and the first 015 ₁ -015 _N signal outputs AB 1 ₁ -1 _N set high logic levels. Accordingly, at the output 72 of the first N-input element AND-NOT 7 and the output 102 of the second N-input element AND-NOT 10 low logic levels are set. In this case, the J-bit output 65 of the selector-multiplexer 6 is open, since at its inverse enable input 61 (

) through the element OR 4 and the element AND NOT 5 set a high logical level. The device is ready for operation and awaits request signals generated by subscribers of the computing system (see Fig.6).

счетчиков 1.1₁-1.1_N через установленный интервал времени, определяемый кодами начального заполнения счетчиков и частотой тактовых импульсов.When a need arises for a computing resource, subscribers of the computing system generate request signals that are sent to the request service device and placed in a second-order queue. The request signal from the subscriber is considered a high level signal installed on any of the request inputs 011 ₁ -011 _{N of the} corresponding battery 1 ₁ -1 _N. At the same time, at the second signal outputs 016 ₁ -016 _{N of} these batteries through inverters 1.2 ₁ -1.2 _N , low-level signals will be established. The set of low-level signals at the second signal outputs 016 ₁ -016 _N AB forms a second-order queue. The position of the request signal in the second-order queue is determined by its initial (unverified) priority: the request signal received from the subscriber with the lowest initial (unverified) number has a preliminary highest priority (see Fig. 7). The counting inputs Z of the counters 1.1 ₁ -1.1 _N АБ 1 ₁ -1 _N containing the request signals receive pulses from the output of 21 clock pulses 2 through the circuit: clock inputs 014 ₁ -014 _N АБ 1 ₁ -1 _N , open three-input elements And 1.3 ₁ -1.3 _N AB 1 ₁ -1 _N. The counters 1.1 ₁ -1.1 _{N of} each battery perform the function of timers that control the expiration of the allowable time for requests in the second order queue by summing the clock pulses arriving at their counting input Z and generate an overflow signal at the inverted outputs

counters 1.1 ₁ -1.1 _N after a set time interval determined by the codes for the initial filling of the counters and the frequency of the clock pulses.

The signals from the second signal outputs 016 ₁ -016 _N АБ 1 ₁ -1 _N go to the inverse inputs 91 ₁ -91 _{N of the} second priority encoder 9, which converts the request signals into a J-bit code corresponding to the number of the AB taking into account its initial (not verified ) priority. The signal from the second signal output 016 _{1 of the} first battery (1 ₁ ) is supplied to the N-th inverse input 91 _{N of the} second priority encoder 9, the signal from the second signal output 016 _{2 of the} second battery (1 ₂ ) is fed to (N-1) - the inverse input 91 _{N-1 of the} second priority encoder 9, the signal from the second signal output 016 _{n of the} n-th AB (I _n ) goes to the ((N + 1) -n) -th inverse input 91 _{(N-1) -n} the second priority encoder 9, the signal from the second signal output 016 _{N of the} Nth battery (1 _N ) is supplied to the first inverse input 91 _{1 of the} second priority encoder 9. The specified method of connecting the second signal of the outputs 016 ₁ -016 _N AB is due to the fact that the outputs 92 ₁ -92 _{J of the} second priority encoder 9 are inverse, that is, to receive on its J inverse outputs a code corresponding to the AB with the initial lowest number (not verified highest priority) among those AB 1 ₁ -1 _N , at the second signal outputs 016 ₁ -016 _N which have low logic levels (request signals), you should connect the second signal outputs of the AB to the inputs 91 ₁ -91 _{N of the} second priority encoder 9 in the reverse order. If there is at least one request signal in the second-order queue, a high level will be established at the output 102 of the second N-input AND-NOT 10 element.

From the inverse outputs 92 ₁ -92 _{J of the} second priority encoder 9, the code corresponding to the battery with the lowest initial number, i.e. the subscriber’s code, which a priori (initially, before verification) is authenticated as the highest priority subscriber, is sent to the J inputs 121 ₁ -121 _{J of the} second priority analyzer 12. Preliminary analysis of the data in the interest of determining the true number (priority) of the subscriber within the queue of multi-priority requests second order is carried out in the second priority analyzer 12 as follows. From the inputs 121 ₁ -121 _{J of the} second priority analyzer 12, the code corresponding to the battery with the lowest initial number goes to the J inputs of the second selector 12.1 and to the J inputs of the second converter 12.2 (see figure 3).

The procedure for selecting data on the true number (priority) of the subscriber for a queue of second-priority queries of different priorities and deciding on the mathematical nature of these data is carried out in the second selector 12.1 as follows. The subscriber’s code, which a priori (initially, prior to verification) is authenticated as the highest priority subscriber, is sent to the J inputs of the second selector 12.1, which is designed to store five bits of incoming information in each cell.

второго селектора 12.1 поступает в двоичном коде команда, инициирующая запрет трансляции информации с J выходов второго селектора 12.1 на соответствующие прямые выходы группы J прямых выходов 123₁-123_J второго анализатора приоритетов 12. Последовательный код абонента, который недостоверно (неполно, неоднозначно) аутентифицирован как абонент высшего приоритета, с J-разрядного выхода второго преобразователя 12.2 через J-разрядный выход 122 второго анализатора приоритетов 12 поступает на первый 131 J-разрядный вход аутентификатора приоритетов 13. С выхода передачи T×D второго преобразователя 12.2 через контрольный выход 124 второго анализатора приоритетов 12 на первый контрольный вход 135 аутентификатора приоритетов 13 поступает команда, инициирующая начало процедуры верификации приоритета.If the number of bits of the code corresponding to the battery with the lowest initial number exceeds this number, it means, from the point of view of mathematics, this code sequence contains redundancy, which causes the reliability (incompleteness) of data characterizing the priority of a particular subscriber when servicing multi-priority requests in the second-order queue. In this case, a command is issued in binary code from the MT inhibitory output of the second selector 12.1 to the inhibitory DST input of the second converter 12.2, which initiates the start of registration of data characterizing the priority of subscribers for the queue of second-priority requests of different orders and the start of converting this data from parallel to serial. The second converter 12.2 registers the data received through its J inputs, recognized by the second selector 12.1 as invalid (incomplete, ambiguous), and converts them from parallel to serial code. In this case, from the DSR enable output of the second converter 12.2 to the inverse enable input

the second selector 12.1 receives in binary code a command initiating the prohibition of transmitting information from the J outputs of the second selector 12.1 to the corresponding direct outputs of the group J of direct outputs 123 ₁ -123 _{J of the} second priority analyzer 12. The serial code of the subscriber that is unreliable (incomplete, ambiguous) is authenticated as the subscriber of the highest priority, from the J-bit output of the second converter 12.2 through the J-bit output 122 of the second priority analyzer 12 goes to the first 131 J-bit input of the priority authenticator 13. From the output and the transmission T × D 12.2 second transducer 124 via the control output of the second priority analyzer 12 to the first control input of priority 135 authenticator 13 receives the command that initiates the beginning of a priority verification procedure.

If the code in the amount of five bits is received from inputs 121 ₁ -121 _{J of the} second priority analyzer 12 to the J inputs of the second selector 12.1 and to the J inputs of the second converter 12.2, then this code does not need to be verified, it reliably (fully, unambiguously) corresponds to the battery with the smallest number (to the highest priority subscriber). In this case, without receiving the appropriate command to its DST inhibiting input, the second converter 12.2 locks its J-bit output and T × D transmission output, and the second selector 12.1 transmits a parallel code that uniquely corresponds to the lowest AB number containing the request signal from the second order, from its J outputs through the corresponding direct outputs of the group J of direct outputs 123 ₁ -123 _{J of the} second priority analyzer 12 to the corresponding inputs of the first group J of information inputs 62 ₁ -62 _{J of the} selector-multiplexer 6.

The data characterizing the priority of a particular subscriber in the second-order queue, defined (recognized) in the second priority analyzer 12 as ambiguous (false, incomplete) and requiring verification, comes from the J-bit output 122 of the second priority analyzer 12 to the first 131 J-bit input priority authenticator 13, which records, stores the results of the priority analysis and mathematically correct verification of the lowest subscriber number (verification of the subscriber with the highest priority). The conversion of certain (recognized) ambiguous (unreliable, incomplete) source data characterizing the priority of subscribers to a form suitable for unambiguous adoption of a reliable decision on the priority level of a particular subscriber of a computer system is carried out in a programmable calculator 13.1 of the priority authenticator 13 as follows.

The programmable calculator 13.1 of the priority authenticator 13 (see Fig. 4) is technically implemented on the basis of the programmable (from the point of view of the weight matrix — causal cognitive opinions on priority formulated by experts) microprocessor section that plays the role of a programmable parallel ALU that implements a computational neural network algorithm ( ENS) described in [3]. If there is no information on the first 131 J-bit input of the priority authenticator 13 and on the J-bit input I of the programmable calculator 13.1, respectively, there is no command initiating the beginning of the priority verification procedure, to the first control input 135 of the priority authenticator 13 and to the output enable input A ( OE _I ) programmable computer 13.1. In this case, the J outputs A (A ₁ -A _J ) of the programmable calculator 13.1, and hence the J outputs 13.2-2 ₁ -13.2-2 _{J of the} first memory element 13.2 are blocked. Otherwise, there is a signal at the output enable input of outputs A (OE _I ) of programmable calculator 13.1 and ambiguously (unreliably, incompletely) certain initial data characterizing the priority of subscribers are sent to the J-bit input I of programmable calculator 13.1, which implements the functions of programmable parallel ALU.

The programmable calculator 13.1, which implements the functions of a programmable parallel ALU, relying on the programmed values of the elements of the weight matrix — the cause-and-effect cognitive opinions on priority analytically described by experts, implements the calculation (extrapolation) procedure in accordance with the computational neural network algorithm described in detail in [3 ]. In this case, the input cells I ₁ -I _J correspond to the category (1, ..., J) of the serial code supplied to the J-bit input I of the programmable calculator 13.1, and are equal J inputs (J _I ) of the calculators (neurons) of the input layer S _a ENS, to which values of J bits of a code having a physical meaning are ambiguously (inaccurate, incomplete) of a certain priority of a subscriber. The set of direct and feedback connections J _in with J _out ENS, programmatically implemented in the framework of programmable calculator 13.1, allows you to take into account weighting coefficients of priorities for the second-order queue formulated by experts and get extrapolated 13.1 on J outputs A (A ₁ -A _J ) of programmable calculator the values of J bits of the parallel code having the physical meaning of the verified (mathematically correctly verified) lowest AB number, i.e. the highest priority of the subscriber in the second order queue, determined on the basis of verified (reliable, complete) source data. In this case, the supply to the jth, where j = 1, 2, ..., J, the input (I _j ) of the programmable calculator 13.1 values of the discharge of the code characterizing the ambiguous (inaccurate, incomplete) certain priority of the subscriber, initiates the issuance from the corresponding j- of the output (А _j ) of the programmable calculator 13.1 (output of the j-th neuron of the output layer S _b ) of the programmed value according to the computational neural network algorithm described in [3], which is mathematically correctly transformed relative to the reliable discharge of the code characterizing the true priority of the subscriber For second order queues.

As a result, at the J outputs A (A ₁ -A _J ) of the programmable calculator 13.1 and at the corresponding J inputs 13.2-1 ₁ -13.2-1 _{J of the} first memory element 13.2 we obtain information characterizing (based on the analysis of the integrated expert opinion obtained in the framework of the ENS) the true priority of the subscriber for the second-order queue, transformed (verified) in the interest of increasing the reliability of authentication of this subscriber.

The first memory element 13.2 records, stores and outputs from its J outputs 13.2-2 ₁ -13.2-2 _J through the corresponding outputs of the first group J of outputs 133 ₁ -133 _{J of the} priority authenticator 13 to the corresponding inputs of the first group J of information inputs 62 ₁ -61 _J selector-multiplexer 6 code containing verified results of priority analysis - a code that unambiguously corresponds to the lowest AB number containing a request signal from a second-order queue.

As the computing resource (computer resource, LAN) is released, a high-level signal is generated that goes to the interrogation input of the device and then to the first input 51 of the AND-NOT 5. If there is at least one request in the second-order queue at the output 53 of the AND gate NOT 5, a low level signal will be established that will allow data transmission to the selector-multiplexer 6. At the control input 64 (input S) of the selector-multiplexer 6, a low level is set (at the first signal outputs 015 ₁ -015 _{N of} all ABs - a high level), therefore, on jr gas tube, where J =] log ₂ N [, output 65 of the selector-multiplexer 6 and J-bit output "subscriber service code to be" switched device is verified code reliably characterizing the local priority for the second-order queue. This data comes from the outputs of the first group of J outputs 133 ₁ -133 _{J of the} priority authenticator 13 to the corresponding inputs of the first group of J information inputs 62 ₁ -62 _N (inputs A ₁ -A _J ) of the selector-multiplexer 6 and unambiguously correspond to the smallest AB number containing request signal from the second order queue.

After satisfying the need for a computing resource, the n-th subscriber removes the request signal from the corresponding n-th request input of the device, from the request input 011 _{n of the} corresponding battery (1 _n ), and resets the counter 1.1 _{n of the} corresponding battery 1 _n at the n-th input Zeroing "the device and the input" Zeroing "013 _n corresponding to the battery 1 _n (see figure 5). At the same time, the first and second signal outputs 015 _n and 016 _{n of the} corresponding battery 1 _n will have high levels.

, а следовательно, и на первых сигнальных выходах 015₁-015_N соответствующих АБ 1₁-1_N сигналов низкого уровня, что соответствует переносу запросов в очередь первого порядка на места, соответствующие их изначальным (не верифицированным) приоритетам (см. фиг.6), в целях их дальнейшего внеочередного, по отношению к очереди второго порядка, обслуживания. При этом запираются соответствующие трехвходовые элементы И 1.3₁-1.3_N (фиг.5), запрещая поступление тактовых импульсов на счетные входы Z соответствующих счетчиков 1.1₁-1.1_N. Совокупность сигналов низкого уровня на первых сигнальных выходах 015₁-015_N соответствующих АБ 1₁-1_N образует очередь первого порядка. Обслуживание запросов из очереди первого порядка осуществляется с учетом достоверной аутентификации (определения их истинных и однозначно распознанных приоритетов), аналогично запросам из очереди второго порядка. Сигналы запросов для очереди первого порядка с первых сигнальных выходов 015₁-015_N соответствующих АБ 1₁-1_N поступают (в обратном порядке) на инверсные входы 81₁-81_N первого шифратора приоритетов 8. При этом формирование кода, соответствующего наименьшему номеру АБ, содержащему сигнал запроса из верифицированной очереди первого порядка, осуществляется первым шифратором приоритетов 8 тем же способом, что и для очереди второго порядка.In the event that one or several requests as a result of the created queue have reached the maximum waiting time, there is an overflow of counters 1.1 ₁ -1.1 _{N of the} corresponding batteries 1 ₁ -1 _N , formation of overflow on their inverse outputs

and, therefore, at the first signal outputs 015 ₁ -015 _{N of the} corresponding AB 1 ₁ -1 _N low-level signals, which corresponds to the transfer of requests to the first-order queue to the places corresponding to their initial (unverified) priorities (see Fig. 6 ), with a view to their further extraordinary, in relation to the second-order queue, service. In this case, the corresponding three-input elements AND 1.3 ₁ -1.3 _N are locked (Fig. 5), prohibiting the arrival of clock pulses to the counting inputs Z of the corresponding counters 1.1 ₁ -1.1 _N. The set of low-level signals at the first signal outputs 015 ₁ -015 _{N of the} corresponding batteries 1 ₁ -1 _N forms a first-order queue. Requests from the first order queue are serviced taking into account reliable authentication (determining their true and unambiguously recognized priorities), similar to requests from the second order queue. Request signals for the first-order queue from the first signal outputs 015 ₁ -015 _{N of the} corresponding batteries 1 ₁ -1 _N are received (in reverse order) to the inverse inputs 81 ₁ -81 _{N of the} first priority encoder 8. In this case, the formation of the code corresponding to the lowest number of AB containing the request signal from the verified first-order queue is carried out by the first priority encoder 8 in the same manner as for the second-order queue.

From the inverse outputs 82 ₁ -82 _{J of the} first priority encoder 8, the code corresponding to the battery with the lowest initial number, i.e. the subscriber’s code, which a priori (initially, before verification) is authenticated in the first-order queue as the highest priority subscriber, is sent to the J inputs 111 ₁ -111 _{J of the} first priority analyzer 11. In the first priority analyzer 11, a preliminary analysis of the data about the true number (priority ) of the subscriber for the queue of different priorities of the first order, similar to the procedure described earlier, carried out in the second analyzer of priorities 12 for the second order queue. A parallel code that unambiguously corresponds to the smallest AB number containing a request signal from a first-order queue from the outputs of the group J of direct outputs 113 ₁ -113 _{J of the} first priority analyzer 11 goes to the corresponding inputs of the second group J of information inputs 63 ₁ -63 _{J of the} selector-multiplexer 6 Otherwise, a sequential code that ambiguously (unreliably, incompletely) characterizes the smallest number of batteries containing a request signal from a first-order queue from J-bit output 112 of the first priority analyzer 11 steps t to the second input of J-bit authenticator 132 13 priorities, and the enable signal fed from the control output 114 of the first priorities of the analyzer 11 to the second control input 136 authenticator 13 priorities.

Similarly, authenticating subscribers from a second-order queue, recording, storing the results of priority analysis for a first-order queue and converting certain (recognized) ambiguously (inaccurate, incomplete) source data characterizing the priority of subscribers to a form suitable for unambiguous making a reliable decision about the priority level of a particular subscriber computing system is carried out in the authenticator of priorities 13. This happens after the control output 114 of the first analyzer pri 11 signals through the second control input 136 of the priority authenticator 13, a signal is received at the output enable input B (OE _E ) of programmable calculator 13.1 and ambiguous (unreliable, incomplete) certain initial data characterizing the priority of subscribers in the first-order queue are received from J-bit output 112 the first priority analyzer 11 through the secondary J-bit input 132 of the priority authenticator 13 to the J-bit input E of the programmable calculator 13.1, which implements the functions of the programmable parallel ALU in accordance obstacle to the programmed neural network algorithm.

At the J outputs B (B ₁ -B _J ) of the programmable calculator 13.1 and at the corresponding J inputs 13.3-1 ₁ -13.3-1 _{J of the} second memory element 13.3, we obtain information characterizing (based on the analysis of the integrated expert opinion obtained in the framework of the ENS) the true priority a subscriber for a first-order queue, transformed (verified) in the interest of increasing the authenticity of authentication of a given subscriber. The second memory element 13.3 records, stores and outputs from its J outputs 13.3-2 ₁ -13.3-2 _J through the corresponding outputs of the second group J of outputs 134 ₁ -134 _{J of the} priority authenticator 13 to the corresponding inputs of the second group J of information inputs 63 ₁ -63 _J selector-multiplexer 6 code containing verified results of priority analysis - a code that uniquely corresponds to the lowest AB number containing a request signal from a first-order queue.

As a result, on the J inputs of the first group J of information inputs 62 ₁ -62 _J and on the J inputs of the second group J of information inputs 63 ₁ -63 _{J of the} selector-multiplexer 6, we have a reliable (verified) code that uniquely characterizes the priority of subscribers for the queue of the second and first order, respectively, obtained on the basis of mathematically correct, within the framework of the apparatus of the theory of neural computing networks, analysis of the integrated opinions of experts about the true priority of these subscribers.

If there is a request with an unambiguously recognized priority in the first order queue, their extraordinary in relation to requests from the second order queue, service is provided by a high-level signal at the output 72 of the first N-input element AND-NOT 7, which, arriving at the control input 64 (input S) selector-multiplexer 6 switches on the J-bit output of the selector 65, the multiplexer 6 and J-bit output "subscriber service code to be" device code, ringing on J J inputs of the second group of information inputs 63 ₁ -63 _N (of inputs B ₁ -B _J) selector-multiplexer 6 and corresponding to the verified (reliably defined) smallest number AB containing a request signal from the first-order queue. The high-level signal at the output 72 of the first N-input element AND-NOT 7 will be until there is at least one request in the first-order queue.

счетчика 1.1_n соответствующего АБ 1_n, что, в свою очередь, обуславливает установку на первом и втором сигнальных выходах 015_n и 016_n этого АБ 1_n высоких уровней. Это позволяет устройству после выполнения всех запросов абонентов соответствующего верифицированного приоритета с истекшим временем ожидания перейти к обслуживанию вновь поступивших либо ждущих своей очереди запросов в порядке, определенном логикой работы устройства.After the release of the resource allocated in the interests of the next request of the subscriber with the corresponding verified priority from the first order queue (with the elapsed waiting time), each n-th subscriber removes the request signal from the request input 011 _{n of the} corresponding battery (1 _n ) and resets the counter 1.1 _n corresponding AB 1 _n at the nth input “Zeroing” the device and the input “Zeroing” 013 _n AB 1 _n . This predetermines a high level output.

the counter 1.1 _{n of the} corresponding battery 1 _n , which, in turn, causes the installation of the first and second signal outputs 015 _n and 016 _{n of} this battery 1 _n high levels. This allows the device, after fulfilling all the requests of subscribers of the corresponding verified priority with an expired waiting time, to switch to servicing newly received or waiting for its turn requests in the order determined by the logic of the device.

Thus, in the framework of the verification of the subscriber with the highest priority in the second order queue, at the J outputs of the group J of direct outputs 123 ₁ -123 _{J of the} second priority analyzer 12 or at the J outputs of the first group of J outputs 133 ₁ -133 _{J of the} priority authenticator 13, which means , and on the corresponding J inputs of the first group J of information inputs 62 ₁ -61 _{J of the} selector-multiplexer 6, we have a reliable (verified) code that uniquely characterizes the priority of subscribers for the second-order queue. As part of the verification of the subscriber with the highest priority in the first order queue, at the J outputs of the group J of direct outputs 113 ₁ -113 _{J of the} first priority analyzer 11 or at the J outputs of the second group of J outputs 134 ₁ -134 _{J of the} priority authenticator 13, and hence corresponding to the J inputs of the second group of J information inputs 63 ₁ -63 _{J of the} selector-multiplexer 6, we have a reliable (verified) code that uniquely characterizes the priority of subscribers for the first-order queue.

An analysis of the principle of operation of the claimed device for servicing multi-priority requests of subscribers of a computing system shows the evidence of the fact that, along with the capabilities to improve speed and reliability stored and described in the prototype, the device is able to identify the lowest AB number (the highest priority of the subscriber, mathematically correct and more reliably) ) initiating the request signal under conditions inherent in the real dynamics of the functioning of the data exchange systems E and a LAN.

This device provides increased authenticity of authentication of subscribers under conditions of inaccuracy (insufficiency, incompleteness, and often inconsistency) of data characterizing the priority of a particular subscriber when serving different priority requests, which significantly expands the scope of the device, expands the functionality of the mass service subsystems within the framework of exchange systems data and local area networks, where the claimed device servicing multi-priority subscriber requests ntov computing system will be used.

INFORMATION SOURCES

1. Wassermen F. Neurocomputer technology: Theory and practice. - M.: Mir, 1992 .-- 240 p.

2. Kosko, V. Fuzzy cognitive maps // International Journal of Man-Machine Studies. V.24. N.Y., 1986. P.16-22.

3. Shcherbakov M.A. Artificial neural networks. - Penza: PSTU, 1996 .-- 44 p.

4. Trachtengerts E.A. Computer decision support. - M .: SINTEG, 1998 .-- 342 p.

5. Gorban A.N., Rossiev D.A. Neural networks on a personal computer. - Novosibirsk: Science. Siberian Publishing Company RAS, 1996. - 146 p.

Claims (4)

1. A device for servicing multi-priority subscriber requests of a computing system, comprising N≥2 subscriber units, a clock, the first and second N-input NAND elements, the first and second priority encoders, the OR element, the NAND element and the selector multiplexer, J-bit, where J =] log ₂ N [, the output of which is the J-bit output "Subscriber code to be serviced", the output of the clock generator is connected to the clock inputs of each of the N subscriber units, request inputs and K-bit inputs " The code the maximum latency ”of each of the N subscriber units, where K≥2 is the code length of the maximum time to wait for service requests, are the corresponding N query inputs and N K-bit inputs“ Code maximum waiting ”of the device, the inputs“ Zeroing ”of each of the N subscriber units are the corresponding N inputs “Zeroing” the device, N inputs of the first and second N-input elements are NOT connected to the corresponding N inverse inputs of the first and second priority encoders, respectively, the outputs of the first and the second N-input elements AND are NOT connected respectively to the second and first inputs of the OR element, the output of which is connected to the second input of the AND element, the first input of which is a polling input of the device, the output of the AND gate is connected to the inverse enable input of the selector the multiplexer and is the enable output of the device, the control input of the selector-multiplexer is connected to the second input of the OR element, the n-th inverse inputs of the first and second priority encoders, where n = 1, 2, ..., N, are connected respectively to the first and second signal outputs of the (N + 1) -n) -th subscriber unit, characterized in that the first and second priority analyzers are introduced for preliminary analysis of data on the true priority of the subscriber for a queue of different priority requests, respectively, of the first and second order and priority authenticator , intended for recording, storing the results of priority analysis and mathematically correct verification of the subscriber with the highest priority, by converting the recognized x data characterizing the priority of subscribers to a form suitable for making an unambiguous reliable decision about the priority level of a particular subscriber of a computing system, each of the J inverse outputs of the first and second priority encoders connected to the J inputs of the first and second priority analyzers, respectively, J-bit outputs which are connected respectively to the second and first J-bit inputs of the priority authenticator, the control outputs of the first and second priority analyzers are connected respectively -retarded to the first and second control inputs authenticator priorities, the first group of J outputs and a second group of J outputs of which are connected respectively with the first and second groups of information inputs J-selector multiplexer are connected to the groups and J direct output respectively first and second priorities analyzers. 2. The device for servicing multi-priority requests of subscribers of a computing system according to claim 1, characterized in that the first priority analyzer consists of a first selector and a first converter for recording data characterizing the priority of subscribers for a first-order queue and converting this data from parallel code to serial wherein the J-bit output of the first converter is the J-bit output of the first priority analyzer, the transmission output of the first converter is I control the output of the first priority analyzer, the enable output of the first converter is connected to the inverse enable input of the first selector J, the outputs of which are a group of corresponding J direct outputs of the first priority analyzer, the inhibitory input of the first converter is connected to the inhibit output of the first selector, J inputs of which are connected to the corresponding J inputs of the first converter and are the corresponding J inputs of the first priority analyzer. 3. The service device for multi-priority requests of subscribers of the computing system according to claim 1, characterized in that the second priority analyzer consists of a second selector and a second converter for recording data characterizing priority for a second-order queue and converting this data from parallel code to serial, moreover, the J-bit output of the second converter is the J-bit output of the second priority analyzer, the transmission output of the second converter is control the output of the second priority analyzer, the enable output of the second converter is connected to the inverse enable input of the second selector, J outputs of which are a group of corresponding J direct outputs of the second priority analyzer, the inhibitory input of the second converter is connected to the inhibit output of the second selector, J inputs of which are connected to the corresponding J inputs the second converter and are the corresponding J inputs of the second priority analyzer. 4. The service device for multi-priority requests of subscribers of a computing system according to claim 1, characterized in that the priority authenticator consists of a programmable computer, first and second memory elements designed to record and store a code containing verified results of priority analysis - a code corresponding to the lowest subscriber number block containing the request signal from the queue, respectively, of the second and first order, while the J-bit input I and the J-bit input E are programmable the calculators are, respectively, the first and second J-bit inputs of the priority authenticator, the enable input of the outputs A and the enable input of the outputs B of the programmable computer are the first and second control inputs of the priority authenticator, the J outputs A and J outputs B of the programmable computer are connected respectively to the J inputs of the first and J inputs of the second storage elements, and the J outputs of the first and J outputs of the second storage elements are the corresponding J outputs, respectively first and second groups J authenticator priority outputs.

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