RU2799386C1 - Parallel structure tasks manager arbiter - Google Patents

Abstract

FIELD: computer technology.

SUBSTANCE: invention can be used for arbitration in multiprocessor information processing systems for parallelizing the flow of applications. The device comprises N channels for processing tasks, an external bus for the input request IP and N external tires for channel parameters IC1, IC2, …, ICN, external priority bus of the input request IPR, N external priority buses of channels IK1, IK2, …, IKN, N internal priority buses of channels BZ1, BZ2, …, BZN in the unitary code "1 of M", internal buses of priority ranks BV, multi-bit single code of low priority BW, input priority in unitary code BPR, channels of low priority VK, as well as a group of N blocks of parameter analysis 1₁, 1₂, …, 1_N, a group of N decoders 4₁, 4₂, …, 4 _N, input priority decoder 5, groups of OR elements, groups of prohibition elements AND with inverted inputs, group of N blocks for analysis of channel readiness 8₁, 8₂, …, 8_N, AND elements, groups of AND elements, OR elements and an OR-NOT element.

EFFECT: expansion of functionality in terms of the possibility of parallel detection of a processing channel with a minimum priority rank and comparison with the priority rank of the input task.

1 cl, 1 dwg, 1 tbl

Description

FIELD OF TECHNOLOGY

The invention relates to the field of computer technology and can be used for arbitration in multiprocessor information processing systems for parallelizing the flow of applications.

PRIOR ART

A multi-channel priority device is known (RU No. 2415465 C2, IPC G06F 9/46, declared 06/01/2009, publ. 03/27/2011, Bull. No. 9), containing M channels, each of which contains a decoder, a group of elements AND, the first and second OR elements, an AND element with direct and inverse inputs, a delay element, a group of priority code inputs, a request input and a response output, moreover, in each channel, the request input is connected to the input of the delay element, the output of which is connected to the second inputs of all AND elements of the group of elements AND of its own channel, the group of code inputs of the channel is connected to the group of inputs of the channel decoder, and the output of the first OR element is the output of the channel response.

This device introduced the discipline of servicing subscribers' requests with absolute priorities, which can be quickly changed when the computer system is reconfigured. The disadvantage of this device is the task of only unequal priorities

A multi-rank request priority arbiter is known (RU No. 2649948 C1, IPC G06F 13/37, announced on May 15, 2017, published on April 5, 2018, Bull. No. 10), containing N groups of external query inputs IZ1, IZ2, ..., IZN, each of which contains M bits of the priority rank (the highest priority rank has the highest M-th bit, the highest priority has the highest group IZN), the first group of N external outputs of the pointers of the group of the highest priority U1, U2, ..., UN, the second group of M external outputs of the pointers the highest priority rank in the group OZ1, OZ2, …, OZM, a group of (N-2) elements OR 4 ₁ , 4 ₂ , …, 4 _(N-2) , the first group of (N-1) prohibition elements AND with one inverse input 5 ₁ , 5 ₂ , ..., 5 _(N-1) , a group of M elements OR-NOT 6 ₁ , 6 ₂ , ..., 6 _M , the second group of (M-1) prohibition elements AND with one inverse input 7 ₁ , 7 ₂ , …, 7 _(M-1) , inverter 8 and a group of N blocks of priority analysis channels 1 ₁ , 1 ₂ , …, 1 _N , each of which contains an OR element 3 and a group of (M-1 ) elements AND 2 ₁ , 2 ₂ , …, 2 _(M-1) , while each v-th element of AND 2 _v (v=1, 2, …, (M-1)) contains (M-v+1 ) inputs.

The disadvantage of this device is the lack of tools for analyzing the parameters of the required parameters of input requests and parameters of task processing channels.

The closest device for the same purpose to the claimed invention in terms of the totality of features is, taken as a prototype, the task manager arbiter (RU No. 2749151 C1, IPC G06F 13/37, G06F 9/50, declared 10/26/2020, publ. 06/07/2021, Bull . No. 16) containing the external bus of the input request IP and N external bus parameters of the channels IC1, IC2, ..., ICN, which consist of L groups of parameters, N external busses of the busy channels IT1, IT2, ..., ITN, each of which contains M bits of the priority rank (the highest priority rank has the lowest zero digit, the highest priority has the highest channel ITN), the first group of N external outputs of the highest priority channel indicators QU1, QU2, ..., QUN and the second group of M external outputs of the highest priority rank indicators in the channel OZ0, OZ1, …, OZ(M-1), N internal request buses IZ1, IZ2, …, IZN, each of which contains M priority bits, N bits of the internal status bus of channels S1, S2, …, SN, N bits of the internal the readiness buses of channels K1, K2, ..., KN and the readiness flag F, and also contains a group of N parameter analysis blocks, each of which contains a group of L comparators, and an AND element, a group of N request resolution blocks, each of which contains the first a group of M AND elements, a first group of M OR elements, a second group of (M-1) AND prohibition elements with inverse inputs, a group of N channel readiness analysis blocks, each of which contains a third group of (M-1) AND elements and the first OR element, as well as the second OR element, the second group of (N-2) OR elements and the fourth group of (N-1) prohibition elements AND with one inverse input.

The disadvantage of this device is the lack of means for comparing the priority ranks of serviced claims and the priority rank of the input claim.

OBJECT OF THE INVENTION

The problem to be solved by the invention is to create a task manager arbiter for multiprocessor processing systems for parallel analysis of the priority ranks of current running tasks, identifying a channel with a minimum rank and comparing it with the priority rank of the input task.

The technical result of the invention is the expansion of functionality in terms of the possibility of parallel detection of a processing channel with a minimum priority rank and comparison with the priority rank of the input task.

BRIEF DESCRIPTION OF THE INVENTION

The specified technical result in the implementation of the invention is achieved by the fact that the arbiter of the task manager of the parallel structure contains N channels for processing tasks, an external bus of the input request IP and N external tires of channel parameters IC1, IC2, ..., ICN, each of which consists of L groups of channel parameters, an external priority bus of the input IPR request, which contains m bits of setting the priority rank (where m=] log ₂ M [(] [is a larger integer), M is the number of priority ranks in the range from 0 to (M-1), the highest priority rank has the highest number (M-1)), N external priority buses of the channels IK1, IK2, ..., IKN each of which contains m bits of the priority rank (the lowest priority has the lowest first channel, the highest priority has the highest Nth channel), N internal priority buses of channels BZ1, BZ2, ..., BZN in the unitary code "1 of M", N bits of the internal bus S of the state of the channels S1, S2, ..., SN, the internal bus of priority ranks BV, which contains M bits, the internal bus of the multi-bit single low priority code BW and the internal input priority bus in the unitary BPR code, each of which contains (M-1) bits, the internal low priority channel bus VC, which contains N bits, the first group of N external outputs QU1, QU2, ..., QUN of low-priority channel indicators in the "1 out of N" code, the second group of M external outputs QZ0, QZ1, ..., QZ(M-1) of low-priority pointers in channels in the "1 out of M" code, an external ready flag QF and external QFS status flag,

and also contains a group of N blocks for analyzing parameters 1 ₁ , 1 ₂ , …, 1 _N , each of which contains a group of L comparators 2 ₁ , 2 ₂ , …, 2 _L and an AND element 3, a group of N decoders 4 ₁ , 4 ₂ , …, 4 _N , input priority decoder 5, the first group of M OR elements 6 ₀ , 6 ₁ , …, 6 _(M-1) , the first group of (M-1) prohibition elements AND with inverse inputs 7 _{1 . _ _ _ _ _ _} , …, 9 _(M-1) and the first element OR 10, the third group of (N-1) prohibition elements AND (AND) with inverse inputs 11 ₁ , 11 ₂ , …, 11 _(N-1) , the second element AND (AND) 12, the second group of (M-2) elements OR 13 ₁ , 13 ₂ , ..., 13 _(M-2) , the fourth group of (M-1) elements AND 14 ₁ , 14 ₂ , ..., 14 _{( M-1)} , second element OR 15 and element OR NOT 16,

moreover, L groups of parameters of the task of the external bus of the input request IP are connected to the first groups of inputs of the corresponding comparators of the same name 2 ₁ , 2 ₂ , …, 2 _L of all N blocks of parameter analysis 1 ₁ , 1 ₂ , …, 1 _N , each of which contains the second groups the inputs of the comparators 2 ₁ , 2 ₂ , …, 2 _L are connected to the corresponding L groups of the same name of the corresponding N external busses of the parameters of the channels IC1, IC2, …, ICN, as well as in each parameter analysis block 1 ₁ , 1 ₂ , …, 1 _N outputs comparators 2 ₁ , 2 ₂ , ..., 2 _L are connected to the corresponding element FROM, the outputs of which are the corresponding N bits S1, S2, ..., SN of the internal bus state of the channels S and connected to the corresponding inputs of the element OR-NOT 16, and also connected to inputs for enabling the operation of the same-name decoders from the group 4 ₁ , 4 ₂ , ..., 4 _N , the address inputs of which are connected to the external priority buses of the same name of the channels from the group IK1, IK2, ..., IKN,

the outputs of N decoders from the group 4 ₁ , 4 ₂ , ..., 4 _N are the corresponding M bits of the same-named N internal priority buses of the channels BZ1, BZ2, ..., BZN, while the M bits of each of which are connected to the corresponding like-named inputs of the same-named N blocks of readiness analysis channels 8 ₁ , 8 ₂ , …, 8 _N , and are also connected to the corresponding inputs of the same-name elements OR from the first group 6 ₀ , 6 ₁ , …, 6 _(M-1) , the outputs of which are the corresponding M bits of the internal bus of priority ranks BV , in which from the first digit to the (M-1) th digit are connected to the first direct inputs of the same-named elements of the first group from (M-1) prohibition elements AND with inverse inputs 7 ₁ , 7 ₂ , …, 7 _(M-1) , in which the inverse inputs of the j-th element 7j (j=1, 2, ..., (M-1)) are connected to the corresponding bits (k=0, 1, ..., (j-1)) of the internal bus of priority ranks BV ,

inputs of the same name M, (M+1), ..., (2M-2) of each of the N blocks of channels for analyzing the readiness of channels 8 ₁ , 8 ₂ , ..., 8 _N are interconnected and also connected to the corresponding outputs (M-1) elements, starting from the first to (M-1)-th element, from the first group of elements AND with inverse inputs 7 ₁ , 7 ₂ , …, 7 _(M-1) ,

the outputs of the AND elements of the first group of (M-1) prohibition elements AND with one inverse input 7 ₁ , 7 ₂ , …, 7 _(M-1) are the corresponding (M-1) outputs OZ1, OZ2, …, OZ(M- 1) the second group of M external outputs of pointers of the lowest priority rank in the channel, and the lowest zero output OZ0 is the output of the OR element 6 ₀ ,

in addition, from the first digit to the (M-2)-th digit of the internal bus of priority ranks BV are connected to the first inputs of the same-name elements OR from the second group 13 ₁ , 13 ₂ , ..., 13 _(M-2) , the second inputs of which, starting from the second 13 ₂ to (M-2)-th 13 _(M-2) elements are connected to the outputs of the corresponding previous (M-3) elements 13 ₁ , 13 ₂ , ..., 13 _(M-3) from the second group of OR elements, starting from the first 13 ₁ to (M-3)-th 13 _(M-3) elements, and the second input of the first element 131 from the second group of elements OR is connected to the zero bit of the internal bus of priority ranks BV,

moreover, the outputs (M-2) of the OR elements from the second group 13 ₁ , 13 ₂ , ..., 13 _(M-2) are the corresponding (M-2) bits of the internal bus of the multi-bit single code of the lowest priority BW, starting from the first to (M -2)-th bit, and the zero bit of the internal bus BW is connected to the zero bit of the internal bus of priority ranks BV,

the external priority bus of the input request IPR is connected to the group of address inputs of the input priority decoder 5, the outputs of which are the corresponding (M-1) bits of the internal priority bus BPR in a unitary code, which are connected to the first inputs of the same-named (M-1)-th elements AND the fourth groups 14 ₁ , 14 ₂ , ..., 14 _(M-1) , the second inputs of which are connected to the corresponding bits of the internal bus BW, starting from zero to (M-2)-th bits, and the outputs of all elements AND of the fourth group 14 ₁ , 14 ₂ , …, 14 _(M-1) are connected to the corresponding inputs of the second element OR 15, the output of which is connected to the first direct inputs of the prohibition elements AND with inverse inputs from the third group 11 ₁ , 11 ₂ , …, 11 _(N-1) and the first input of the second element AND 12, as well as the output of the second element OR 15 is an external ready flag QF,

in each of the N blocks 8 ₁ , 8 ₂ , ..., 8 _N readiness analysis of the channels (M-1) of the inputs of the block, starting from the first input to the (M-1) input, are connected to the corresponding first inputs of the same-name elements And from the second group of (M-1) elements AND 9 ₁ , 9 ₂ , ..., 9 _(M-1) of the block, in which the second inputs are connected to the corresponding inputs of the block, starting from the M-th input to the (2M-2)-th input, and the outputs of the second group of (M-1) elements AND 9 ₁ , 9 ₂ , ..., 9 _(M-1) of the block and the 0th input of the block are connected to the corresponding inputs of the first element OR 10, the output of which is the output of the corresponding block of readiness analysis channels channels 8 ₁ , 8 ₂ , ..., 8 _N , which are connected to N bits of the internal bus of the channels of the lowest priority VC,

moreover, the N-th bit of the internal bus of the channels of the lowest priority VC is connected to the second input of the second element And 12, the first (N-1) bits of the internal bus of the channels of the lowest priority of the VC, starting from the first digit to (N-1) digit, are connected to the first direct inputs of the corresponding identical (N-1) elements AND with inverse inputs from the third group 11 ₁ , 11 ₂ , …, 11 _(N-1) , in which the inverse inputs of the h-th element 11h (h=(1, 2, (N -1)) are connected to the corresponding Kp bits of the internal bus of the low-priority channels VC (p=(h+1), (h+2) , ..., N), while the outputs (N-1) of the AND elements with inverse inputs from the third groups 11 ₁ , 11 ₂ , ..., 11 _(N-1) are the least significant (N-1) bits of the first group of N external outputs of the channel indicators of the lowest priority QU1, QU2, ..., QU(N-1), and the highest N- The m digit of the QUN channel indicators is the output of the second element AND 12.

BRIEF DESCRIPTION OF THE DRAWINGS

In FIG. Figure 1 shows a diagram of the proposed arbiter of the task manager of a parallel structure for N task processing channels, input priority IPR and N external priority buses of channels IK1, IK2, ..., IKN containing binary codes of M priority ranks, input request bus IP and external buses IK1, IK2, ... , IКN parameters of N channels for processing tasks containing L groups of channel parameters (the highest rank has the highest priority number (M-1), the highest priority has the highest N-th channel).

In FIG. 1 and the following designations are introduced in the text:

N is the number of task processing channels;

IP - external bus of the input request, containing L groups of task parameters

IC1, IC2, …, ICN - external parameter buses of N task processing channels,

containing L groups of channel parameters;

IPR - external bus priority of the input request, containing m digits;

M - the number of priority ranks in the range from 0 to (M-1);

m - word length of priority rank, where m=] log2M [(] [- larger integer); (the highest priority rank has the highest number (M-1), the lowest rank at zero corresponds to the absence of an input request or the channel is not busy with service);

IK1, IK2, ..., IKN - N external busses of channel priorities, each of which contains m bits of the priority rank (lowest priority has the lowest first channel IK1, high priority has the highest Nth channel IKN);

BZ1, BZ2, ..., BZN - N internal busses of channel priorities in the unitary code "1 of M" (the highest priority rank has the lowest zero digit, the highest priority has the highest group BZN);

S1, S2, ..., S4 (SN) - N bits of the internal channel status bus;

BV - internal bus priority ranks containing M bits;

BW - internal bus multi-bit single code of lower priority, containing (M-1) bit;

BPR - internal bus input priority in a unitary code containing (M-1) bits;

VK - internal bus channels of lower priority, containing N digits;

QU1, QU2, ..., QUN - the first group of N external outputs of the low priority channel indicators in the code "1 of N",

QZ0, QZ1, ..., QZ(M-1) - the second group of M external outputs of indicators of the lowest priority rank in the channels in the code "1 of M",

QF - external ready flag;

QFS - external status flag;

E - input for enabling the decoder;

1 ₁ , 1 ₂ , …, 1 _N - group of N blocks of parameter analysis;

2 ₁ , 2 ₂ , …, 2 _L is a group of L comparators (COMP) of each block for analyzing parameters 1 ₁ , 1 ₂ , …, 1 _N ,

3 - the first element AND (AND) of each block of channels for analyzing parameters 1 ₁ , 1 ₂ , ..., 1 _N , 4 ₁ , 4 ₂ , ..., 4 _N - a group of N decoders (DC) with the input enable operation E;

5 - decoder (DC) input priority;

6 ₀ , 6 ₁ , ..., 6 _(M-1) - the first group of M elements OR (OR);

7 ₁ , 7 ₂ , …, 7 _(M-1) - the first group of (M-1)-th prohibition elements AND (AND) with inverse inputs;

8 ₁ , 8 ₂ , …, 8 _N - a group of N blocks of channel readiness analysis;

9 ₁ , 9 ₂ , …, 9 _(M-1) - the second group of (M-1) elements AND (AND) of each block of the analysis of the readiness of channels 8 ₁ , 8 ₂ , …, 8 _N ;

10 - the first element OR (OR) of each block for analyzing the readiness of channels 8 ₁ , 8 ₂ , ..., 8 _N ; 11 ₁ , 11 ₂ , …, 11 _(N-1) - the third group of (N-1) prohibition elements AND (AND) with inverse inputs;

12 - the second element AND (AND);

13 ₁ , 13 ₂ , ..., 13 _(M-2) - the second group of (M-2) elements OR (OR);

14 ₁ , 14 ₂ , ..., 14 _(M-1) - the fourth group of (M-1) elements AND (AND);

15 - second element OR (OR);

16 - element OR-NOT (NOR).

The proposed parallel structure task manager arbiter contains N task processing channels, an external bus of the input request IP and N external bus parameters of the channels IC1, IC2, ..., ICN, each of which consists of L groups of channel parameters, an external bus of the priority of the input request IPR, which contains m bits of setting the priority rank (where m=] log2M [(] [- greater integer), M is the number of priority ranks in the range from 0 to (M-1), the highest priority rank has the highest number (M-1)), N external priority buses of channels IK1, IK2, ..., IКN each of which contains m bits of priority rank (the lowest priority has the lowest first channel, the highest priority has the highest N-th channel), N internal priority buses of the channels BZ1, BZ2, ..., BZN in the unitary code "1 of M", N bits of the internal bus S of the state of the channels S1, S2, ..., SN, the internal bus of priority ranks BV, which contains M bits, the internal bus of the multi-bit single code of the lowest priority BW and the internal bus of the input priority in the unitary BPR code, each of which contain (M-1) bits, the internal bus of low-priority channels VC, which contains N bits, the first group of N external outputs QU1, QU2, ..., QUN of low-priority channel indicators in the code "1 of N ”, the second group of M external outputs QZ0, QZ1, ..., QZ(M-1) of indicators of the lowest priority rank in the channels in the “1 of M” code, the external ready flag QF and the external status flag QFS.

The proposed controller arbiter also contains a group of N blocks for analyzing parameters 1 ₁ , 1 ₂ , …, 1 _N , each of which contains a group of L comparators 2 ₁ , 2 ₂ , …, 2 _L and an AND element 3, a group of N decoders 4 ₁ , 4 ₂ , …, 4 _N , input priority decoder 5, the first group of M elements OR 6 ₀ , 6 ₁ , …, 6 _(M-1) , the first group of (M-1) prohibition elements AND with inverse inputs 7 ₁ , 7 ₂ , …, 7 _(M-1) , a group of N blocks for analyzing the readiness of channels 8 ₁ , 8 ₂ , …, 8 _N , each of which contains a second group of (M-1) elements AND 9 ₁ , 9 ₂ , …, 9 _(M-1) and the first element OR 10, the third group of (N-1) prohibition elements AND (AND) with inverse inputs 11 ₁ , 11 ₂ , …, 11 _(N-1) , the second element AND (AND) 12, the second group of (M-2) elements OR 13 ₁ , 13 ₂ , ..., 13 _(M-2) , the fourth group of (M-1) elements AND 14 ₁ , 14 ₂ , ..., 14 _(M-1) , the second OR element 15, and the OR NOT element 16.

Moreover, L groups of parameters of the task of the external bus of the input request IP are connected to the first groups of inputs of the corresponding comparators of the same name 2 ₁ , 2 ₂ , …, 2 _{L of} all N blocks for analyzing the parameters l ₁ , l ₂ , …, 1 _N , each of which contains the second groups the inputs of comparators 2 ₁ , 2 ₂ , …, 2 _L are connected to the corresponding L groups of the same name of the corresponding N external busses of the parameters of the channels IC1, IC2, …, ICN. Also, in each parameter analysis block 1 ₁ , 1 ₂ , …, 1 _N , the outputs of the comparators 2 ₁ , 2 ₂ , …, 2 _L are connected to the corresponding element I3, the outputs of which are the corresponding N bits S1, S2, …, SN of the internal status bus channels S and connected to the corresponding inputs of the OR-NOT element 16, and also connected to the inputs for enabling the operation of the decoders of the same name from the group 4 ₁ , 4 ₂ , ..., 4 _N , the address inputs of which are connected to the external priority buses of the same name channels from the group IK1, IK2 , …, IKN.

The outputs of N decoders from the group 4 ₁ , 4 ₂ , ..., 4 _N are the corresponding M bits of the same N internal priority buses of the channels BZ1, BZ2, ..., BZN, while the M bits of each of which are connected to the corresponding like-named inputs of the same-named N blocks of readiness analysis channels 8 ₁ , 8 ₂ , …, 8 _N , and are also connected to the corresponding inputs of the same-name elements OR from the first group 6 ₀ , 6 ₁ , …, 6 _(M-1) , the outputs of which are the corresponding M bits of the internal bus of priority ranks BV , in which from the first digit to the (M-1) th digit are connected to the first direct inputs of the same-named elements of the first group from (M-1) prohibition elements AND with inverse inputs 7 ₁ , 7 ₂ , …, 7 _(M-1) , in which the inverse inputs of the j-th element 7j (j=1, 2, ..., (M-1)) are connected to the corresponding k bits (k=0, 1, ..., (j-1)) of the internal bus of priority ranks BV .

The same-named inputs M, (M+1), ..., (2M-2) of each of the N blocks of channels for analyzing the readiness of channels 8 ₁ , 8 ₂ , ..., 8 _N are interconnected and also connected to the corresponding outputs (M-1) elements, starting from the first to (M-1)-th element, from the first group of elements AND with inverse inputs 7 ₁ , 7 ₂ , …, 7 _(M-1) .

The outputs of the AND elements of the first group of (M-1) prohibition elements AND with one inverse input 7 ₁ , 7 ₂ , ..., 7 _(M-1) are the corresponding (M-1) outputs OZ1, OZ2, ..., OZ(M- 1) the second group of M external outputs of indicators of the lowest priority rank in the channel, and the lowest zero output OZ0 is the output of the OR element 6 ₀ .

In addition, from the first digit to the (M-2)-th digit of the internal bus of priority ranks BV are connected to the first inputs of the same-name elements OR from the second group 13 ₁ , 13 ₂ , ..., 13 _(M-2) , the second inputs of which, starting from the second 13 ₂ to (M-2)-th 13 _(M-2) elements are connected to the outputs of the corresponding previous (M-3) elements 13 ₁ , 13 ₂ , ..., 13 _(M-3) from the second group of OR elements, starting from the first 13 ₁ to (M-3)-th 13 _(M-3) elements, and the second input of the first element 131 from the second group of elements OR is connected to the zero bit of the internal bus priority ranks BV.

Moreover, the outputs (M-2) of the OR elements from the second group 13 ₁ , 13 ₂ , ..., 13 _(M-2) are the corresponding (M-2) bits of the internal bus of the multi-bit single code of the lowest priority BW, starting from the first to (M -2)-th bit, and the zero bit of the internal bus BW is connected to the zero bit of the internal bus of priority ranks BV.

The external priority bus of the input request IPR is connected to the group of address inputs of the input priority decoder 5, the outputs of which are the corresponding (M-1) bits of the internal priority bus BPR in a unitary code, which are connected to the first inputs of the same-named (M-1)-th elements AND the fourth groups 14 ₁ , 14 ₂ , ..., 14 _(M-1) , the second inputs of which are connected to the corresponding bits of the internal bus BW, starting from zero to (M-2)-th bits. The outputs of all AND elements of the fourth group 14 ₁ , 14 ₂ , ..., 14(M-1) are connected to the corresponding inputs of the second element OR 15, the output of which is connected to the first direct inputs of the prohibition elements AND with inverse inputs from the third group 11 ₁ , 11 ₂ , ..., 11 _(N-1) and the first input of the second element AND 12, as well as the output of the second element OR 15 is an external ready flag QF.

In each of the N blocks 8 ₁ , 8 ₂ , ..., 8 _N readiness analysis channels (M-1) inputs of the block, starting from the first input to the (M-1) input, are connected to the corresponding first inputs of the same-name elements AND from the second group of (M-1) elements AND 9 ₁ , 9 ₂ , ..., 9 _(M-1) of the block, in which the second inputs are connected to the corresponding inputs of the block, starting from the M-th input to the (2M-2)-th input. The outputs of the second group of (M-1) elements AND 9 ₁ , 9 ₂ , ..., 9 _(M-1) of the block and the 0th input of the block are connected to the corresponding inputs of the first element OR 10, the output of which is the output of the corresponding block of readiness analysis channels channels 8 ₁ , 8 ₂ , ..., 8 _N , which are connected to N bits of the internal bus of the channels of the lowest priority VC.

Moreover, the N-th bit of the internal bus of the channels of the lowest priority VC is connected to the second input of the second element And 12, the first (N-1) bits of the internal bus of the channels of the lowest priority of the VC, starting from the first digit to (N-1) digit, are connected to the first direct inputs of the corresponding identical (N-1) elements AND with inverse inputs from the third group 11 ₁ , 11 ₂ , …, 11 _(N-1) , which have inverse inputs of the h-th element 11h (h=(1, 2, …, (N-1)) are connected to the corresponding Kp bits of the internal bus of the low-priority channels of the VC (p=(h+1), (h+2), ..., N). At the same time, the outputs of the (N-1) AND elements with inverse inputs from the third group 11 ₁ , 11 ₂ , ..., 11 _(N-1) are the least significant (N-1) bits of the first group of N external outputs of the low-priority channel indicators QU1, QU2, ..., QU(N-1), and the highest The N-th digit of the QUN channel indicators is the output of the second element AND 12.

DETAILED DESCRIPTION OF THE INVENTION

The principle of operation of the proposed device is as follows. In the proposed device, the input request on the external IP bus contains L groups of required parameters for the execution of the computational task - the amount of memory for input and output of information, the availability of appropriate programs for the algorithm for processing the computational task. The proposed task manager arbiter in N blocks of parameter analysis 1 ₁ , 1 ₂ , …, 1 _N checks the possibility of servicing requests by comparing L groups of required parameters for a task on the external IP bus and the corresponding L groups of parameters of task processing channels arriving via buses IC1, IC2 , …, ICN. If all the parameters of the L groups by channels correspond, single values are formed in the corresponding N bits of the internal bus of the state of the channels S1, S2, ..., SN or zero values if the parameters do not match. At zero values of all bits of the state bus of the channels S1, S2, ..., SN, a single value of the state flag QFS=1 is formed at the inverse output of the OR-NOT element 16 - the parameters of the input request IP do not correspond to the parameters in all N channels of processing requests.

At the same time, the binary priority numbers of the previous requests served are received via the external priority buses of N channels IK1, IK2, ..., IКN, which in the group 4 ₁ , 4 ₂ , ..., 4 _N of N decoders (DC) are converted into the corresponding unitary codes "1 from M ” (the highest priority rank has the highest number (M-1), the lowest rank at zero corresponds to a free channel not occupied by service), which are transmitted to the corresponding internal priority buses of the same name of the channels BZ1, BZ2, ..., BZN. In addition, the operation permission input E of each decoder 4 ₁ , 4 ₂ , ..., 4 _N is connected to the corresponding bit of the same name of the internal status bus of the channels S1, S2, ..., SN. Therefore, when the corresponding bit of the state bus of the channels S1, S2, ..., SN is zero, the outputs of all bits of the corresponding decoder are set to zero.

Further, at the outputs of the first group of elements OR 6 ₀ , 6 ₁ , …, 6 _(M-1), single values are formed corresponding to the numbers of the priority ranks of the served previous requests, which are transmitted to the corresponding bits of the internal bus of the priority ranks BV, according to which in the first group 7 ₁ , 7 ₂ , …, 7 _(M-1) from the (M-1)th prohibition elements AND (AND) with inverse inputs, the lowest priority (rank) is determined and the rank number is formed in the unitary code “1 from M”, which is transmitted to the second group of M external outputs of pointers of the lowest priority rank in channels QZ0, QZ1, …, QZ(M-1) or a zero code if the parameters of all channels do not correspond to the parameters of the input request IP.

Further, in accordance with the values of the bits of the internal bus of priority ranks BV, at the outputs of the second group 13 ₁ , 13 ₂ , 13 _(M-2) from (M-2) elements OR (OR), a number of single values are formed, which are transmitted to the internal bus BW of the multi-bit a single low priority code, starting from the bit corresponding to the low priority served up to (M-2) bit.

At the same time, the input priority binary code from the external IPR bus is converted on the input priority decoder (DC) 5 into a unitary code "1 of M", which is transmitted to the internal priority bus BPR, according to which in the fourth group 14 ₁ , 14 ₂ , ..., 14 (m-1) from (M-1) elements AND (AND) the input priority IPR is compared with the priority of serviced requests in channels from the internal bus BW and a single value is formed at the output of the corresponding element from the group 14 ₁ , 14 ₂ , ..., 14 _(M-1) if the input IPR priority exceeds the priority of serviced requests in the channels. In this case, a single value of the ready flag QF=1 is formed. If the value of the binary priority code of the input request IPR is equal to or less than the priority code of the serviced requests, then a zero value of the ready flag QF=0 is generated.

In the channels readiness analysis blocks 8 ₁ , 8 ₂ , …, 8 _N , on the basis of the lowest priority rank in the channel QZ0, QZ1, …, QZ(M-1), single values are formed at the outputs on the bits of the internal bus VC of the readiness of channels for servicing , which are used to search for _the service readiness channel with the lowest _priority in _the third group ) 12 (the highest priority has the highest N-th channel). In this case, with a single value of the ready flag QF=1, in the first group of external outputs of the low-priority channel indicators QU1, QU2, ..., QUN, the result is formed in the form of a unitary code "1 out of N" (a single value on one of the bits of the outputs). If the priority of the input request IPR is equal to or less than the priority code of the serviced requests, then the zero value of the ready flag QF=0 is generated, the operation of the third group 11 ₁ , 11 ₂ , …, 11 _(N-1) of (N-1) prohibition elements is prohibited AND (AND) with inverse inputs and the second element AND (AND) 12. and on the group of external outputs of the low-priority channel indicators QUI, QU2, ..., QUN zero values are formed.

The proposed device works as follows.

In the proposed device, the input request on the external priority bus of the input request IPR contains m bits of the binary code for setting the priority rank in the range from 0 to (M-1) (the highest priority rank has the highest number (M-1), the lower rank at zero corresponds to the absence input request). At the same time, L groups of required parameters of the input request for the execution of the computational task are sent to the external IP bus, and L groups of channel parameters are received from N processing channels via external buses IC1, IC2, ..., ICN - the amount of memory for input and output of information, the availability of appropriate programs for algorithm for processing a computational problem.

The proposed task manager arbiter in N blocks of parameter analysis 1 ₁ , 1 ₂ , …, 1 _N checks the possibility of servicing requests by comparing L groups of required parameters for a task on the external IP bus and the corresponding L groups of parameters of task processing channels arriving via buses IC1, IC2 , …, ICN. If all the parameters of the L groups by channels correspond, single values are formed in the corresponding N bits of the internal bus of the state of the channels S1, S2, ..., SN or zero values if the parameters do not match. If zero values are set in all bits of the state bus of channels S1, S2, ..., SN, then a single value of the state flag QFS=1 is formed at the inverse output of the NOR element 16 - the parameters of the input request IP do not correspond to the parameters in all N channels of processing requests.

At the same time, the binary priority numbers of the previous requests served are received via the external priority buses of N channels IK1, IK2, ..., IКN, which in the group 4 ₁ , 4 ₂ , ..., 4 _N of N decoders (DC) are converted into the corresponding unitary codes "1 from M ” (the highest priority rank has the highest number (M-1), the lowest rank at zero corresponds to a free channel that is not busy with service).

Table 1 shows test examples of the formation of the first group of outputs of indicators of the lowest priority channel QU1, QU2, ..., QU4 and the second group of outputs of indicators of the lowest priority rank QZ0, QZ1, ..., QZ3 for N=4 processing channels, each of which contains M=4 the level (rank) of the priority of processing applications (the lowest priority rank has the lowest zero digit QZ0, the highest priority has the highest 4th channel QU4).

In test No. 1, the values of the parameters of L groups of the input request IP do not correspond to the parameters of L groups of all channels IC1, IC2, ..., IC4, therefore, zero values are formed in all N=4 bits of the internal state bus of the channels S1, S2, ..., S4 and then formed a single value of the state flag QFS=T means that the parameters of the input request IP do not correspond to the parameters of all N channels for processing requests. At the same time, the corresponding binary values of the codes of the priority ranks are received in the channels of already served requests via the buses IK1, IK2, ..., IK4, for which, at zero values of the status bus bits of the channels S1, S2, ..., S4, at the outputs of the group 4 ₁ , 4 ₂ , …, 4 _N of N decoders (DC) are set to zero values, which are transmitted to the internal priority buses of the channels BZ1, BZ2, …, BZ4 and then to the internal bus of priority ranks BV[3-0]=0000, to the internal bus of the multi-bit single code lower priority BW[2-0]=000 and to the internal channel readiness bus for servicing VK[4-1]=0000. Further, zero values are formed on the second group of outputs of indicators of the lowest rank of priority QZ0, QZ1, ..., QZ3. For the input request priority IPR=2, a unitary code BPR[3-1]=010 is formed at the outputs of decoder 5, but with zero bits on the internal bus BW[2-0]=000 at the outputs of the fourth group 14 ₁ , 14 ₂ , 14 ₃ from (M-1)=3 elements AND (AND) zero values are also formed. Therefore, the external ready flag QF=0 is set to zero, which corresponds to the prohibition of access on all channels, and the code "0000" is also generated on the first group of external outputs of the low-priority channel indicators QUI, QU2, ..., QU4.

In test No. 2, the values of the parameters of L groups of the input request IP correspond to the parameters of L groups in all channels IC1, IC2, ..., IC4, therefore, single values are formed in all N=4 bits of the internal state bus of the channels S1, S2, ..., S4, and then zero value of the state flag QFS=0 - correspondence of the parameters of the IP input request to the parameters of the request processing channels. At the same time, zero values of the channel priority rank codes are received via the buses IK1, IK2, ..., IK4, which corresponds to the absence of processed applications in the channels. Further, at the outputs of group 4 ₁ , 4 ₂ , …, 4 ₄ of N decoders (DC), the codes “0001” are set, corresponding to zero priorities, which are transmitted to the internal priority buses of the channels BZ1, BZ2, …, BZ4. At the same time, the corresponding codes are formed on the internal bus of priority ranks BV[3-0]=0001, on the internal bus of the multi-bit single code of lower priority BW[2-0]=111, on the second group of outputs of pointers of lower priority rank QZ[3-0 ]=0001 and further, at the outputs of a group of N=4 blocks for analyzing the readiness of channels 8 ₁ , 8 ₂ , …, 8 ₄ and on the internal bus of the lower priority channels, the code VK[4-1]=1111 is set, corresponding to the possibility of processing the incoming request during all four channels. At the same time, for the priority of the input request IPR=0, the unitary code BPR[3-1]=000 is generated at the outputs of the decoder 5 - the absence of the input request. Therefore, at the outputs of the fourth group 14 ₁ , 14 ₂ , 14 ₃ of (M-1)=3 elements AND (AND) zero values are formed and the external ready flag QF=0 is set to zero, which corresponds to the prohibition of access through all channels, as well as the code "0000" is formed on the first group of external outputs of the low-priority channel indicators QU1, QU2, ..., QU4.

In test No. 3, the values of the parameters of L groups of the input request IP correspond to the parameters of L groups of all channels IC1, IC2, ..., IC4, therefore, single values are formed in all N=4 bits of the internal state bus of the channels S1, S2, ..., S4, and then zero is formed the value of the status flag QFS=0 - the correspondence of the parameters of the input request IP to the parameters of the channels for processing requests. At the same time, zero values of the channel priority rank codes are received via the buses IK1, IK2, ..., IK4, which corresponds to the absence of processed applications in the channels. Further, at the outputs of group 4 ₁ , 4 ₂ , …, 4 ₄ of N decoders (DC), the codes “0001” are set, corresponding to zero priorities, which are transmitted to the internal priority buses of the channels BZ1, BZ2, …, BZ4. In this case, the corresponding codes are further formed on the internal bus of priority ranks BV[3-0]=0001, on the internal bus of the multi-bit single code of lower priority BW[2-0]=111 and on the second group of outputs of pointers of lower priority rank QZ[3-0 ]=0001, corresponding to the zero priority rank. Further, at the outputs of a group of N=4 blocks for analyzing the readiness of channels 8 ₁ , 8 ₂ , …, 8 ₄ and on the internal bus of the lower priority channels, the code VK[4-1]=1111 is set, corresponding to the possibility of processing the incoming request in all four channels. At the same time, for the priority of the input request IPR=1, the unitary code BPR[3-1]=001 is generated at the outputs of the decoder 5. Therefore, further, a single value is formed at the output of the first element 14 ₁ of the fourth group 14 ₁ , 14 ₂ , 14 ₃ of (M-1)=3 elements AND (AND) and a single value of the ready flag QF=1 is set (since the priority code IPR= 1 of the input request is greater than the zero priority code of the serviced requests QZ[3-0]=0001) and at the outputs of the low-priority channel indicators QU1, QU2, ..., QU4, based on the code values from the internal bus of the low-priority channels VK[4-1]= 1111, the unitary code "1000" is generated (one value corresponds to the senior fourth channel QU4=1).

In test No. 4, the values of the parameters of L groups of the input request IP do not correspond to the parameters of L groups in the third channel S3=0 and correspond to the parameters in the first S1=1, second S2=1 and fourth S4=1 channels, and a zero value of the state flag QFS=0 is generated - correspondence of the parameters of the IP input request to the parameters of the request processing channels. At the same time, the corresponding values of the codes of the channel priority ranks are received via the buses IK1=0, IK2=1, IK3=0, IK4=3, which are transmitted to the group 4 ₁ , 4 ₂ , ..., 4 ₄ of N=4 decoders (DC), to the outputs of which form the corresponding unitary codes, which are then transmitted to the group of internal channels priority buses: BZ1[3-0]=0001, BZ2[3-0]=0010, BZ3[3-0]=0000, BZ4[3-0] =1000. At the same time, zero values are set on bus BZ3, since L groups of the input request IP do not correspond to the parameters of L groups in the third channel S3=0. At the same time, the corresponding codes are generated on the internal bus of priority ranks BV[3-0]=1011 (applications of zero, first and third priorities are served), on the internal bus of the multi-bit single code of the lowest priority BW[2-0]=111 and on the second group outputs of pointers of the lowest priority rank QZ[3-0]=0001, corresponding to the zero priority rank. Further, at the outputs of a group of N=4 blocks for analyzing the readiness of channels 8 ₁ , 8 ₂ , …, 8 ₄ and on the internal bus of the lower priority channels, the code VK[4-1]=0001 is set, corresponding to the possibility of processing the incoming request in the first channel. At the same time, for the priority of the input request IPR=2, the unitary code BPR[3-1]=010 is generated at the outputs of the decoder 5. Therefore, a single value is generated at the output of the second element 14 ₂ of the fourth group 14 ₁ , 14 ₂ , 14 ₃ of (M-1)=3 elements AND (AND) and a single value of the ready flag QF=1 is set (since the priority code IPR=2 of the input request is greater than the zero priority code of the serviced requests QZ[3-0]=0001) and at the outputs of the low-priority channel indicators QU1, QU2, ..., QU4, based on the code values from the internal bus of the low-priority channels VK[4-1]=0001 , the unitary code "0001" is formed (a single value corresponds to the lowest first channel QU1=1).

In test No. 5, the values of the parameters of L groups of the input request IP correspond to the parameters of L groups of all channels IC1, IC2, ..., IC4, therefore, single values are formed in all N=4 bits of the internal state bus of the channels S1, S2, ..., S4, and then zero is formed the value of the status flag QFS=0 - the correspondence of the parameters of the input request IP to the parameters of the channels for processing requests. At the same time, the corresponding values of the codes of the channel priority ranks are received via the buses 1K1=3, 1K2=1, 1K3=2, 1K4=2, which are transmitted to the group 4i, 42, 44 of N=4 decoders (DC), at the outputs of which the corresponding unitary codes that are further transmitted to the group of internal channel priority buses: BZ1[3-0]=1000, BZ2[3-0]=0010, BZ3[3-0]=0100, BZ4[3-0]=0100. At the same time, the corresponding codes are generated on the internal bus of priority ranks BV[3-0]=1110 (applications of the first, second and third priorities are served), on the internal bus of the multi-bit single code of the lowest priority BW[2-0]=110 and on the second group outputs of pointers of the lowest priority rank QZ[3-0]=0010 corresponding to the first priority rank. Further, at the outputs of a group of N=4 blocks for analyzing the readiness of channels 8 ₁ , 8 ₂ , …, 8 ₄ and on the internal bus of the lower priority channels, the code VK[4-1]=0010 is set, corresponding to the possibility of processing the incoming request in the second channel. At the same time, for the priority of the input request IPR=3, a unitary code BPR[3-1]=100 is generated at the outputs of the decoder 5. Therefore, a single value is generated at the output of the third element 14z of the fourth group 14 ₁ , 14 ₂ , 14 ₃ of (M-1)=3 elements AND (AND) and a single value of the ready flag QF=1 is set (since the priority code IPR=3 input requests are greater than the first priority code of the serviced requests QZ[3-0]=0010) and at the outputs of the low-priority channel indicators QU1, QU2, ..., QU4, based on the code values from the internal bus of the low-priority channels VK[4-1]=0010, a unitary code "0010" is formed (a single value corresponds to the second channel QU2=1).

In test No. 6, the values of the parameters of L groups of the input request IP do not correspond to the parameters of L groups in the first channel S1=0 and correspond to the parameters in the second S1=1, third S3=1 and fourth S4=1 channels, and a zero value of the state flag QFS=0 is generated - correspondence of the parameters of the IP input request to the parameters of the request processing channels. At the same time, the corresponding values of the codes of the channel priority ranks are received via the buses IK1=3, IK2=1, IK3=2, IK4=1, which are transmitted to the group 4 ₁ , 4 ₂ , ..., 4 ₄ of N=4 decoders (DC), to the outputs of which form the corresponding unitary codes, which are then transferred to a group of internal channels priority buses: BZ1 [3-0]=0000, BZ2[3-0]=0010, BZ3[3-0]=0100, BZ4[3-0] =0010. At the same time, zero values are set on bus BZ1, since L groups of the input request IP do not correspond to the parameters of L groups in the first channel S 1=0. At the same time, the corresponding codes are generated on the internal bus of priority ranks BV[3-0]=1110 (applications of the first, second and third priorities are served), on the internal bus of the multi-bit single code of the lowest priority BW[2-0]=110 and on the second group outputs of pointers of the lowest priority rank QZ[3-0]=0010 corresponding to the first priority rank. Further, at the outputs of a group of N=4 blocks for analyzing the readiness of channels 8 ₁ , 8 ₂ , …, 8 ₄ and on the internal bus of the lower priority channels, the code VK[4-1]=1010 is set, corresponding to the possibility of processing the incoming request in the second and fourth channels in which applications with the first rank are processed. At the same time, for the priority of the input request IPR=1, the unitary code BPR[3-1]=001 is generated at the outputs of the decoder 5. Therefore, a zero value is formed at the outputs of the fourth group 14 ₁ , 14 ₂ , 14 ₃ from (M-1)=3 elements AND (AND) and the zero value of the ready flag QF=0 is set (since the rank code of the input priority IPR=1 is, and not more than the lower rank of serviced requests QZ[3-0]=0010). Therefore, at the outputs of the low-priority channel indicators QU1, QU2, ..., QU4, a zero code “0000” is generated, which corresponds to the prohibition of data transmission.

Thus, in the proposed device, on the first group of external outputs of the low-priority channel indicators QU1, QU2, ..., QUN, the value of the corresponding unitary code "1 out of N" will be set and a single value of the ready flag QF=1 and a zero value of the status flag QFS=0 will be formed , if the parameters of L groups of the input request on the IP bus correspond to the parameters of L groups on the buses of the processing channels IC1, IC2, ..., ICN and the priority rank code of the input request IPR exceeds the lowest rank of requests served in the channels. If the priority rank code of the input request IPR does not exceed or is equal to the lower rank of requests served in the channels, then the zero code "0000" is generated at the outputs of the low priority channel indicators QU1, QU2, ..., QU4 and the zero value of the ready flag QF=0 - data transmission prohibition . In addition, if the values of the parameters of L groups of the input request IP do not correspond to the parameters of L groups in all channels IC1, IC2, ..., ICN, then a single value of the state flag QFS=T is generated - the parameters of the input request IP do not correspond to the parameters of all N channels of processing requests, at the same time, the zero value of the status flag QFS=0 and the zero code "0000" are also formed at the outputs of the low-priority channel indicators QU1, QU2, ..., QU4 - data transmission prohibition.

The above information allows us to conclude that the proposed arbiter of the task manager of the parallel structure has the regularity of nodes and connections and corresponds to the claimed technical result - expanding functionality in terms of the possibility of parallel detection of a processing channel with a minimum priority rank and comparison with the priority rank of the input task.

Claims (11)

The task manager arbiter of the parallel structure contains N task processing channels, an external bus of the input request IP and N external bus parameters of the channels IC1, IC2, ..., ICN, each of which consists of L groups of channel parameters, an external bus of the priority of the input request IPR, which contains m digits for setting the priority rank (where m=] log ₂ M [(] [- greater integer), M is the number of priority ranks in the range from 0 to (M-1), the highest priority rank has the highest number (M-1)), N external priority busses of channels IK1, IK2, …, IKN, each of which contains m bits of priority rank (lowest priority has the lowest first channel, highest priority has the highest N-th channel), N internal priority busses of channels BZ1, BZ2, … , BZN in the unitary code "1 of M", N bits of the internal bus S of the state of the channels S1, S2, ..., SN, the internal bus of the priority ranks BV, which contains M bits, the internal bus of the multi-bit single code of the lowest priority BW and the internal bus of the input priority in the unitary BPR code, each of which contains (M-1) bits, the internal bus of low priority channels VC, which contains N bits, the first group of N external outputs QU1, QU2, ..., QUN of low priority channel indicators in the code "1 out of N", the second group of M external outputs QZ0, QZ1, ..., QZ(M-1) of indicators of the lowest priority rank in the channels in the code "1 out of M", the external ready flag QF and the external status flag QFS, and also contains a group of N blocks for analyzing parameters 1 ₁ , 1 ₂ , …, 1 _N , each of which contains a group of L comparators 2 ₁ , 2 ₂ , …, 2 _L and an AND element 3, a group of N decoders 4 ₁ , 4 ₂ , …, 4 _N , input priority decoder 5, the first group of M OR elements 6 ₀ , 6 ₁ , …, 6 _(M-1) , the first group of (M-1) prohibition elements AND with inverse inputs 7 _{1 . _ _ _ _ _ _} , …, 9 _(M-1) and the first element OR 10, the third group of (N-1) prohibition elements AND (AND) with inverse inputs 11 ₁ , 11 ₂ , …, 11 _(N-1) , the second element AND (AND) 12, the second group of (M-2) elements OR 13 ₁ , 13 ₂ , ..., 13 _(M-2) , the fourth group of (M-1) elements AND 14 ₁ , 14 ₂ , ..., 14 _{( M-1)} , second element OR 15 and element OR NOT 16, moreover, L groups of parameters of the task of the external bus of the input request IP are connected to the first groups of inputs of the corresponding comparators of the same name 2 ₁ , 2 ₂ , …, 2 _L of all N blocks of parameter analysis 1 ₁ , 1 ₂ , …, 1 _N , each of which contains the second groups inputs of the comparators 2 ₁ , 2 ₂ , …, 2 _L are connected to the corresponding L groups of the same name of the corresponding N external busses of the parameters of the channels IC1, IC2, …, ICN, as well as in each parameter analysis block 1 ₁ , 1 ₂ , …, I _N outputs comparators 2 ₁ , 2 ₂ , ..., 2 _L are connected to the corresponding element AND, the outputs of which are the corresponding N bits S1, S2, ..., SN of the internal bus state of the channels S and connected to the corresponding inputs of the element OR-NOT 16, and also connected to inputs for enabling the operation of the same-name decoders from the group 4 ₁ , 4 ₂ , ..., 4 _N , the address inputs of which are connected to the external priority buses of the same name channels from the group IK1, IK2, ..., IKN, the outputs of N decoders from the group 4 ₁ , 4 ₂ , ..., 4 _N are the corresponding M bits of the same-named N internal priority buses of the channels BZ1, BZ2, ..., BZN, while the M bits of each of which are connected to the corresponding like-named inputs of the same-named N blocks of readiness analysis channels 8 ₁ , 8 ₂ , …, 8 _N , and are also connected to the corresponding inputs of the same-name elements OR from the first group 6 ₀ , 6 ₁ , …, 6 _(M-1) , the outputs of which are the corresponding M bits of the internal bus of priority ranks BV , in which from the first digit to the (M-1) th digit are connected to the first direct inputs of the same-named elements of the first group from (M-1) prohibition elements AND with inverse inputs 7 ₁ , 7 ₂ , …, 7 _(M-1) , in which the inverse inputs of the j-th element 7j (j=1, 2, ..., (M-1)) are connected to the corresponding k bits (k=0, 1, ..., (j-1)) of the internal bus of priority ranks BV , inputs of the same name M, (M+1) , ..., (2M-2) of each of the N blocks of channels for analyzing the readiness of channels 8 ₁ , 8 ₂ , ..., 8 _N are interconnected and also connected to the corresponding outputs (M-1) elements, starting from the first to (M-1)-th element, from the first group of elements AND with inverse inputs 7 ₁ , 7 ₂ , …, 7 _(M-1) , the outputs of the AND elements of the first group of (M-1) prohibition elements AND with one inverse input 7 ₁ , 7 ₂ , …, 7 _(M-1) are the corresponding (M-1) outputs OZ1, OZ2, …, OZ(M- 1) the second group of M external outputs of pointers of the lowest priority rank in the channel, and the lowest zero output OZ0 is the output of the OR element 6 ₀ , in addition, from the first digit to the (M-2)-th digit of the internal bus of priority ranks BV are connected to the first inputs of the same-name elements OR from the second group 13 ₁ , 13 ₂ , ..., 13 _(M-2) , the second inputs of which, starting from the second 13 ₂ to (M-2)-th 13 _(M-2) elements are connected to the outputs of the corresponding previous (M-3) elements 13 ₁ , 13 ₂ , ..., 13 _(M-3) from the second group of OR elements, starting from the first 13 ₁ to (M-3)-th 13 _(M-3) elements, and the second input of the first element 13 ₁ from the second group of elements OR is connected to the zero bit of the internal bus of priority ranks BV, moreover, the outputs (M-2) of the OR elements from the second group 13 ₁ , 13 ₂ , ..., 13 _(M-2) are the corresponding (M-2) bits of the internal bus of the multi-bit single code of the lowest priority BW, starting from the first to (M -2)-th bit, and the zero bit of the internal bus BW is connected to the zero bit of the internal bus of priority ranks BV, the external priority bus of the input request IPR is connected to the group of address inputs of the input priority decoder 5, the outputs of which are the corresponding (M-1) bits of the internal priority bus BPR in a unitary code, which are connected to the first inputs of the same-named (M-1)-th elements AND the fourth groups 14 ₁ , 14 ₂ , ..., 14 _(M-1) , the second inputs of which are connected to the corresponding bits of the internal bus BW, starting from zero to (M-2)-th bits, and the outputs of all elements AND of the fourth group 14 ₁ , 14 ₂ , …, 14 _(M-1) are connected to the corresponding inputs of the second element OR 15, the output of which is connected to the first direct inputs of the prohibition elements AND with inverse inputs from the third group 11 ₁ , 11 ₂ , …, 11 _(N-1) and the first input of the second element AND 12, as well as the output of the second element OR 15 is an external ready flag QF, in each of the N blocks 8 ₁ , 8 ₂ , ..., 8 _N readiness analysis of the channels (M-1) of the inputs of the block, starting from the first input to the (M-1) input, are connected to the corresponding first inputs of the same-name elements And from the second group of (M-1) elements AND 9 ₁ , 9 ₂ , ..., 9 _(M-1) of the block, in which the second inputs are connected to the corresponding inputs of the block, starting from the M-th input to the (2M-2)-th input, and the outputs of the second group of (M-1) elements AND 9 ₁ , 9 ₂ , ..., 9 _(M-1) of the block and the 0th input of the block are connected to the corresponding inputs of the first element OR 10, the output of which is the output of the corresponding block of readiness analysis channels channels 81, 82, 8n, which are connected to N bits of the internal bus of the channels of the lowest priority VC, moreover, the N-th bit of the internal bus of the channels of the lowest priority VC is connected to the second input of the second element And 12, the first (N-1) bits of the internal bus of the channels of the lowest priority of the VC, starting from the first digit to (N-1) digit, are connected to the first direct inputs of the corresponding identical (N-1) elements AND with inverse inputs from the third group 11 ₁ , 11 ₂ , …, 11 _(N-1) , which have inverse inputs of the h-th element 11 h (h=(l, 2, … , (N-1)) are connected to the corresponding Kp bits of the internal bus of the low-priority channels of the VC (p=(h+1), (h+2) , ..., N), while the outputs (N-1) of the AND elements with inverse inputs from the third group 11 ₁ , 11 ₂ , ..., 11 _(N-1) are the least significant (N-1) bits of the first group of N external outputs of the low priority channel indicators QU1, QU2, ..., QU(N-1), and the highest N-th digit of the QUN channel indicators is the output of the second element AND 12.

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