RU2296365C1 - Information finding device - Google Patents

Abstract

FIELD: electric communications, possible use for finding and quickly identifying information in multi-service digital data transfer networks with commutation of packets.

SUBSTANCE: device contains N generators of time intervals, N selection blocks, frequency divider, N temporary storage registers, N two-input AND elements, solving three-input element AND, N-input OR-NOT element, electronic key, mask storage register, n-input AND-NOT element, control block.

EFFECT: expanded area of possible use of device, increased speed of operation.

5 cl, 6 dwg

Description

The claimed technical solution relates to the field of telecommunications and can be used for search and operational identification of information in multiservice digital data networks with packet switching.

Known information retrieval devices - see, for example, Aut. USSR No. 1621049 "Information Search Device", IPC G 06 F 15/40, claimed 09.01.89, Autosv. USSR No. 1711185 "Information Search Device", IPC G 06 F 15/40, claimed 05.04.89.

Known analogues contain boundary registers, summing and subtracting counters, comparison circuits, memory blocks, calculation blocks and a number of other elements that allow you to search for information. When receiving a digital message and searching for a specific digital sequence in it, it is necessary to determine its parameters and the correspondence of the transmission sequence to the data exchange rules established for this protocol. Known analogues do not fully comply with these requirements.

In the first analogue, the definition of communication packets is implemented with a probability of correct recognition of less than 0.1, since recognition is performed in a statistical way and does not take into account the signs of sequential transmission of information.

In the second analogue, a significant drawback is the impossibility of obtaining an unambiguous solution due to the low level of reliability and probability of identification of the communication protocol (less than 0.3), since the search for information blocks is implemented by the dichotomous method without taking into account the presence of an acceptable sequence of packets.

Of the known closest analogue (prototype) in its technical essence to the claimed device is the device Patent of the Russian Federation No. 215952 "Information Search Device", IPC G 06 F 17/40, published on July 20, 98.

The prototype device includes a memory unit, a search strategy register and a subtracting counter, a frequency divider, a switch, first, second, third and fourth selection units, a time interval former and an indication unit.

Moreover, in the prototype device, the output of the frequency divider is connected to the first inputs of the memory block, subtracting the counter, the first, second, third and fourth blocks of selection, the search strategy register. The outputs of the memory block are connected respectively to the fourth to eleventh inputs of the switch, and the first output of the subtracting counter is connected to the tenth input of the memory block, the twelfth input of the switch, the eleventh input of the first selection block, the tenth inputs of the second, third, and fourth selection blocks, the third input of the search strategy register and is the command output of the device. The second output of the subtracting counter is connected to the eleventh inputs of the second, third and fourth selection blocks, and the third output of the subtracting counter is connected to the twelfth input of the first selection block. The outputs of the switch are connected to the second to ninth inputs of the first, second, third and fourth selection blocks, respectively, and the first and second outputs of the first selection block are connected respectively to the first and second inputs of the switch. The third output of the first selection block is connected to the fourth input of the search strategy register and the fourteenth input of the subtracting counter, and the fourth output of the first selection block is connected to the fifth input of the search strategy register, the fourteenth input of the subtracting counter and the input of the time interval shaper. The fifth output of the first selection block is connected to the third input of the switch. The sixth output of the first selection block and the first outputs of the second, third and fourth selection blocks, the output of the search strategy register are connected to the first input of the display unit, the tenth input of the first selection block and the fourteenth input of the subtracting counter. The second output of the second selection block is connected to the second input of the search strategy register, and the second output of the third selection block is connected to the third input of the search strategy register. In this case, the second output of the fourth selection block and the output of the shaper of the time intervals are connected to the second input of the display unit and the fourteenth input of the subtracting counter. The input of the frequency divider, the second to ninth inputs of the memory unit and the second to thirteenth inputs of the subtracting counter are, respectively, the input of the clock frequency, signal and information inputs of the device.

Such a scheme allows, in comparison with analogue devices, to make it possible to operate the device in a mode close to real-time mode and to ensure zero probability of skipping (in the case of a priori reliable information about the protocol) due to the syntactic recognition of the TFTP protocol based on the identification operation transmitted by packet channel and rules for exchanging them during a communication session.

However, this device has a significant drawback - a narrow scope, namely only for the analysis of the TFTP protocol. In addition, the identification of packets in the prototype device is carried out by the method of sequential structural analysis. An analysis of the packets of the protocol stack of packet data transmission showed that the identification of packets of different protocols is possible by comparing the values of the packet fields or their combinations with reference values unique to each protocol, and this comparison can be performed in parallel (Zolotov S. Internet Protocols. - St. Petersburg: BHV - St. Petersburg, 1998 .-- 304 p .: ill.). An analysis of networks built on the basis of the TCP / IP protocol stack showed that the overwhelming number of security breaches in this type of network is associated with accessibility attacks, which consist in the formation of a directed packet storm (for example, connection establishment requests) to the address of the attacked network node, causing unforeseen consumption of node resources, which leads to a decrease in the functioning efficiency, and sometimes to complete inaccessibility of its resources for network subscribers (Medvedovsky I.D. et al. Attack on the Internet. - M.: DMK, 1999. - 336 p.: il .). In this case, the sequence of receipt of these packets can fully comply with the rules for the exchange of information provided by the specifications for the corresponding protocol (for example, in the agreements adopted for the TCP / IP protocol stack, the number of consecutive incoming requests for establishing a connection is not limited). The prototype device allows you to parse the protocols without taking into account the possible abuse associated with the presence of a large number of duplicate packet types.

The purpose of the claimed technical solution is to develop an information retrieval device that expands its scope and improves performance by implementing parallel structural identification of packets of a wide range of packet data transfer protocols, as well as detecting sequences of repeated packets with control of their admissible intervals.

This goal in the claimed information retrieval device is achieved by the fact that in the known device for servicing subscriber requests of a computing system containing N shapers of time intervals, where N≥1, N selection blocks, a frequency divider, the input of which is the first clock input of the device, N registers are additionally introduced temporary storage, N two-input AND elements, allowing three-input AND element, N-input OR-NOT element, electronic key, mask storage register, N-input AND element and control unit.

Moreover, in the claimed device, the output of the frequency divider is connected to the second clock inputs of the shapers of time intervals. The corresponding bits of the K-bit inputs are “Storage time code”, where K≥1 is the bit length of the storage time code, time interval shapers are interconnected and are the corresponding bits of the K-bit input “Storage time code” of the device. Allowing inputs N of the shapers of time intervals and the first input of the enabling three-input element And are interconnected and are the enabling input of the device. The corresponding bits of M-bit information inputs, where M≥1 is the number of binary bits of the analyzed information block, N temporary storage registers, N selection blocks and electronic key are interconnected and are the corresponding bits of the first M-bit information input of the device. The “Initialization” inputs of N shapers of time intervals and the mask storage register are interconnected and are the “Initialization” input of the device. The output of the enabling three-input element And is connected to the inputs "Resolution" of the shapers of time intervals, an electronic key and is the output "Resolution" of the device. In this case, the i-th output of the "Select block" of the control unit, where i = 1, 2 ... N, is connected to the input "Select block" of the i-th shaper of time intervals. The output of the i-th two-input element AND is connected to the i-th input of the N-input element OR-NOT and the input "Result of comparison" of the i-th shaper of time intervals. The "Installation" output of the i-th time slot former is connected to the "Installation" input of the i-th temporary storage register. The “Status block” output of the i-th time slot driver is connected to the second input of the i-th two-input element And, the i-th input of the control unit and the i-th input of the N-input element AND-NOT. The output of the N-input element AND is NOT connected to the third input of the three-input element And is the output "Device Status" of the device. The bits of the M-bit input "Set mask" of the mask storage register are the corresponding bits of the M-bit input "Set mask" of the device. The bits of the M-bit output of the mask storage register are connected to the corresponding bits of the M-bit inputs of the "Mask" N selection blocks. The M-bit output of the i-th temporary storage register is connected to the second M-bit information input of the i-th selection block. The “Preliminary Result” output of the i-th selection block is connected to the first input of the i-th two-input element I. The inverse output of the N-input element OR is NOT connected to the second input of the enabling three-input element I. The M-bit information output of the electronic key is the third M- bit information output of the device.

The time interval shaper consists of the first, second, third and fourth two-input elements AND, the first and second two-input elements OR-NOT, the two-input element AND-NOT, the two-input OR element, RS-trigger and counter. In this case, the K-bit input of the counter is the K-bit input "Code of the storage time" of the shaper. The first input of the first two-input element And is connected to the second input of the two-input element AND NOT and is the input "Select block" of the shaper. The second input of the first two-input element And is the "Resolution" input of the driver, the output of the first two-input element And is connected to the first information input of the RS-trigger, the first input of the first two-input element OR-NOT and is the "Installation" output of the driver. The second input of the first two-input element OR-NOT is the input "Result of comparison" of the shaper. The inverse output of the first two-input element OR is NOT connected to the inverse installation input of the counter. The first input of the two-input element OR is the input "Initialization" of the shaper. The output of the two-input OR element is connected to the second information input of the RS-trigger. In this case, the output of the RS-trigger is connected to the first input of the third two-input element And, the second input of the second two-input element And and the first input of the fourth two-input element I. The output of the fourth two-input element And is the output "Block status" of the shaper. The first input of the second two-input element And is the second clock input of the shaper. The output of the second two-input element AND is connected to the counter input of the counter, and its inverse overflow output is connected to the second input of the second two-input element OR-NOT. The inverse output of the second two-input element OR is NOT connected to the second input of the third two-input element I. The output of the third two-input element AND is connected to the counter reset input and the second input of the two-input OR element. The inverse output of the two-input AND-NOT element is connected to the second input of the fourth two-input element I. The first input of the second two-input OR-NOT element is connected to the first input of the two-input AND element and is the enable input of the driver.

The selection block consists of the first and second groups of two-input elements And M elements in each group and a comparator. Moreover, the first input of the j-th two-input element And the first group of two-input elements And, where j = 1, 2 ... M, is the j-th bit of the first M-bit information input of the selection block. The first input of the j-th two-input element And the second group of two-input elements And is the j-th bit of the second M-bit information input of the selection block. The second input of the j-th two-input element And the first group of two-input elements And is connected to the second input of the j-th two-input element And the second group of two-input elements And is the j-th discharge of the M-bit input "Mask" of the selection block. The output of the j-th two-input element And the first group of two-input elements And is connected to the j-th information input of the first group of information inputs of the comparator. The output of the j-th two-input element And the second group of two-input elements And is connected to the j-th information input of the second group of information inputs of the comparator, and the output of the equality of the comparator is the output of the "Preliminary result" of the selection block.

The electronic key consists of M two-input elements I. Moreover, the first input of the j-th two-input element And is the j-th bit of the M-bit information input of the electronic key. The second inputs of the two-input elements And are interconnected and are the input "Resolution" of the electronic key. The output of the j-th two-input element And is the j-th bit of the M-bit information output of the electronic key.

второй группы инверторов из N инверторов, дешифратора. При этом i-й инверсный вход шифратора приоритетов является i-м входом "Статус блока" блока управления, а k-й инверсный выход шифратора приоритетов, где k=1, 2...P, соединен с входом k-го инвертора первой группы инверторов. Инверсный выход k-го инвертора первой группы инверторов соединен с k-м входом дешифратора, i-й инверсный выход дешифратора соединен с входом i-го инвертора второй группы инверторов. Инверсный выход i-го инвертора является i-м выходом "Выбор блока" блока управления.The control unit consists of a priority encoder, the first group of inverters from P inverters, where

the second group of inverters from N inverters, a decoder. In this case, the i-th inverse input of the priority encoder is the i-th input "Block Status" of the control unit, and the k-th inverse output of the priority encoder, where k = 1, 2 ... P, is connected to the input of the k-th inverter of the first group inverters. The inverse output of the k-th inverter of the first group of inverters is connected to the k-th input of the decoder, the i-th inverse output of the decoder is connected to the input of the i-th inverter of the second group of inverters. The inverse output of the i-th inverter is the i-th output of the "Select block" control unit.

The specified new set of essential features due to the introduction of N temporary storage registers, N two-input AND elements, allowing a three-input AND element, an N-input OR-NOT element, an electronic key, a mask storage register, an N-input AND element and a control unit provides an increase device performance, the possibility of expanding the spectrum of packet identification and the ability to detect a sequence of repeating packets with control of the allowable intervals of their succession, which leads to st of the inventive apparatus for protocol identification by package structural analysis and to protect against possible misuse associated with the presence of large number of repeating packet types.

The analysis of the prior art by the applicant made it possible to establish that there are no analogues that are characterized by sets of features identical to all the features of the claimed information retrieval device. Therefore, the claimed invention meets the condition of patentability "Novelty."

Search results for known solutions in this and related fields of technology in order to identify features that match the distinctive features of the claimed invention from the prototype have shown that they do not follow explicitly from the prior art. From the prior art determined by the applicant, the influence of the provided by the essential features of the claimed invention on the achievement of the specified technical result is not known. Therefore, the claimed invention meets the condition of patentability "Inventive step".

The claimed objects of the invention are illustrated by drawings, in which:

figure 1 - device information retrieval;

figure 2 - shaper time intervals;

figure 3 - block selection;

figure 4 - electronic key;

figure 5 - control unit;

figure 6 is a timing diagram of the operation of the device.

The device (see Fig. 1) consists of N shapers of time intervals 1.1-1.N, where N≥1, N selection blocks 3.1-3.N, a frequency divider 8, N temporary storage registers 2.1-2.N, N two-input elements And 4.1-4.N, allowing the three-input element And 6, the N-input element OR-NOT 5, the electronic key 7, the storage register mask 9, the N-input element AND-NOT 10, the control unit 11.

The elements are interconnected as follows (see figure 1). The input of the frequency divider 8 is the first clock input 18 of the device, and its output is connected to the second clock inputs 19 of the shapers of time intervals 1.1-1.N. The corresponding bits of the K-bit inputs are “Storage time code”, where K≥1 is the bit depth of the storage time code, shapers of time intervals 1.1-1.N are interconnected and are the corresponding bits of the K-bit input “Storage time code” 14 of the device. Allowing inputs 13 of the shapers of time intervals 1.1-1.N and the first input of the enabling three-input element And 6 are interconnected and are the enabling input 13 of the device. The corresponding bits of the M-bit information input, where M≥1 is the number of binary bits of the analyzed information block, N temporary storage registers 2.1-2.N, N selection blocks 3.1-3.N and electronic key 7 are interconnected and are the corresponding bits of the first M-bit information input 12 of the device. The inputs "Initialization" of the shapers of time intervals 1.1-1.N and the storage register of the mask 9 are interconnected and are the input "Initialization" 15 of the device. The output of the enabling three-input element And 6 is connected to the inputs "Resolution" 29 of the shapers of time intervals 1.1-1.N, the electronic key 7 and is the output "Resolution" 29 of the device. In this case, the output "Select block" 21.i of each control unit 11 is connected to the input "Select block" of the corresponding shaper of time intervals 1.i. The output of the i-th two-input element And 4.i is connected to the i-th input of the N-input element OR-NOT 5 and the input "Result of comparison" of the i-th shaper of time intervals 1.i. The output "Installation" 22.i of each shaper of time intervals 1.i is connected to the input "Installation" of the corresponding register of temporary storage 2.i. The output "Status block" 24 of each shaper time intervals 1.i is connected to the second input of the corresponding two-input element And 4.i, the i-th input of the control unit 11 and the i-th input of the N-input element AND NOT 10. The output of the N-input element AND-NOT 10 is connected to the third input of the enabling three-input element And 6 and is the output "Device Status" 20 of the device. The bits of the M-bit input "Set mask" 16 of the register for storing the mask 9 are the corresponding bits of the M-bit input "Set mask" 16 of the device. The bits of the M-bit output of the mask storage register 9 are connected to the corresponding bits of the M-bit inputs of the Mask 17 N selection blocks 3.1-3.N. The M-bit output of the i-th temporary storage register 2.i is connected to the second M-bit information input 25.i of the selection block 3.i. The output "Preliminary result" 26.1-26.N of each selection block 3.1-3.N is connected to the first input of the corresponding two-input element And 4.1-4.N. The inverse output of the N-input element OR NOT 5 is connected to the second input of the enabling three-input element And 6, and the M-bit information output of the electronic key 7 is the third M-bit information output 28 of the device.

Temporary storage registers 2.1-2.N are designed to save a copy of the received block of information. The mask storage register 9 is designed to store the bit mask needed to compare the significant bits of the information block. The description of the work and the scheme of such registers are known and are given, for example, in the book: P. P. Maltsev, N. S. Dolidze, etc. "Digital Integrated Circuits". Directory. - M .: "Radio and Communications", 1994, p. 57-62.

The frequency divider 8 is designed to generate a synchronizing sequence of pulses and can be built according to any known scheme. See, for example, P.P. Maltsev, N.S. Dolidze and others. Reference "Digital Integrated Circuits". - M .: "Radio and Communications", 1994, p. 62-74. In this case, the input of the divider will be the counter input of the counter, and the output of the divider will be one of the outputs of the counters.

Shapers of time intervals (FVI) 1.1-1.N are designed to control recording in the corresponding registers of temporary storage, control the expiration of the storage time and generate a signal about the status of the respective registers of temporary storage. FVI can be implemented according to any known scheme, taking into account the described functions. In particular, its circuit shown in figure 2, consists of the first 1.1, second 1.9, third 1.4 and fourth 1.10 two-input elements AND, the first 1.7 and second 1.3 two-input elements OR-NOT, two-input element AND-NOT 1.11, two-input element OR 1.6, RS-trigger 1.2, counter 1.8. In this case, the K-bit input of the counter 1.8 is the K-bit input "Storage time code" 14 FVI. The first input of the first two-input element AND 1.1 is connected to the second input of the two-input element AND-NOT 1.11 and is the input "Select block" 21 FVI. The second input of the first two-input element And 1.1 is the input "Resolution" 29 FVI. The output of the first two-input element AND 1.1 is connected to the first information input of the RS-flip-flop 1.2, the first input of the first two-input element OR-NOT 1.7 and is the output "Installation" 22 FVI. The second input of the first two-input element OR NOT 1.7 is the input "Result of comparison" 27 FVI. The inverse output of the first two-input element OR NOT 1.7 is connected to the inverse installation input of the counter 1.8. The first input of the two-input element OR 1.6 is the input "Initialization" 15 FVI. The output of the two-input element OR 1.6 is connected to the second information input of the RS-trigger 1.2. The output of the RS flip-flop 1.2 is connected to the first input of the third two-input element And 1.4, the second input of the second two-input element And 1.9 and the first input of the fourth two-input element And 1.10, the output of which is the block status output 24 FVI. The first input of the second two-input element And 1.9 is the second clock input 19 FVI. The output of the second two-input element And 1.9 is connected to the counting input of the counter 1.8. The counter overflow inverse output 1.8 is connected to the second input of the second two-input element OR NOT 1.3. The inverse output of the second two-input element OR NOT 1.3 is connected to the second input of the third two-input element AND 1.4. The output of the third two-input element AND 1.4 is connected to the reset input of the counter 1.8 and the second input of the two-input element OR 1.6. The first input of the second two-input element OR-NOT (1.3) is connected to the first input of the two-input element AND-NOT (1.11) and is the enabling input 13 of the FVI. The inverse output of the two-input AND element (1.11) is connected to the second input of the fourth two-input element AND (1.10).

RS-trigger 1.2 is designed to store a logical value that determines the operation mode of the PVI, and can be built according to any known scheme. See, for example, Integrated Circuits. Directory. Edited by Tarabrin - 2nd ed., Rev. - M .: "Energoatomizdat", 1985, p.197.

The counter 1.8 is designed to count the counting pulses arriving at its input, to generate a control signal determined by the initial filling code from the information inputs and the repetition period of the clock pulses, that is, it performs the function of a custom timer. The description of the operation and the circuit of such a counter are known and are given, for example, in the book: P. P. Maltsev, N. S. Dolidze, etc. "Digital Integrated Circuits: A Reference", - M.: "Radio and Communication", 1994, p. .64-65.

The selection blocks 3.1-3.N are intended for comparing the bits of a newly received information block with the bits of information blocks previously stored in the temporary storage registers 2.1-2.N (taking into account the mask) and generating the comparison result, and the comparison is performed taking into account the mask. The selection block can be implemented according to any known scheme, taking into account the described functions. In particular, its selection scheme shown in Fig. 3, the selection consists of the first and second groups of two-input elements And M elements in each group 3.1 ₁ -3.1 _M , 3.2 ₁ -3.2 _M and comparator 3.3. Moreover, the first input of the j-th two-input element And the first group of two-input elements And, where j = 1, 2 ... M, is the j-th bit of the first M-bit information input 12 of the selection block. The first input of the j-th two-input element And the second group of two-input elements And is the j-th bit of the second M-bit information input 25 of the selection block. The second input of the j-th two-input element And the first group of two-input elements And is connected to the second input of the j-th two-input element And the second group of two-input elements And is the j-th discharge of the M-bit input "Mask" 17 of the selection block. The output of the j-th two-input element And the first group of two-input elements And is connected to the j-th information input of the first group of information inputs of the comparator 3.3. The output of the j-th two-input element And the second group of two-input elements And is connected to the j-th information input of the second group of information inputs of the comparator 3.3. The output of the equality of the comparator is the output of the "Preliminary result" 26 block selection.

Comparator 3.3 is intended for comparing two M-bit binary codes installed on its inputs and generating a comparison result. The description of the work and the comparator circuit are given, for example, in the book: V.L.Shilo "Popular TTL microcircuits", - M .: "ARGUS", 1993, p.183-184.

The electronic key 7 is intended for switching an M-bit binary code arriving at its input to its output in the presence of an enable signal and can be implemented according to any known scheme taking into account the described function. In particular, its circuit shown in figure 4, consists of M two-input elements And 7.1. ₁ -7.1. _M. Moreover, the first input of the j-th two-input element And is the j-th bit of the M-bit information input of the electronic key. The second inputs of the two-input elements And are interconnected and are the input "Resolution" 29 of the electronic key. The output of the j-th two-input element And is the j-th bit of the M-bit information output of the electronic key.

где

- операция округления до ближайшего большего целого, второй группы инверторов из N инверторов 11.2₁-11.2_P, 11.4₁-11.4_N и дешифратора 11.3. При этом i-й инверсный вход шифратора приоритетов 11.1 является i-м входом "Статус блока" 24.i блока управления, а каждый инверсный выход шифратора приоритетов 11.1 соединен с входом соответствующего инвертора первой группы инверторов. Инверсный выход каждого инвертора первой группы инверторов соединен с соответствующим входом дешифратора 11.3. Каждый инверсный выход дешифратора 11.3 соединен с входом соответствующего инвертора второй группы инверторов. Инверсный выход i-го инвертора второй группы инверторов является i-м выходом "Выбор блока" 21 блока управления.The control unit 11 is designed to select from a variety of available for use FVI FVI with the lowest number and can be implemented according to any known scheme. In particular, its circuit shown in FIG. 5 consists of a priority encoder 11.1, a first group of inverters from P inverters, where

Where

- the operation of rounding to the nearest larger integer, the second group of inverters from N inverters 11.2 ₁ -11.2 _P , 11.4 ₁ -11.4 _N and decoder 11.3. In this case, the i-th inverse input of the priority encoder 11.1 is the i-th input "Block Status" 24.i of the control unit, and each inverse output of the priority encoder 11.1 is connected to the input of the corresponding inverter of the first group of inverters. The inverse output of each inverter of the first group of inverters is connected to the corresponding input of the decoder 11.3. Each inverse output of the decoder 11.3 is connected to the input of the corresponding inverter of the second group of inverters. The inverse output of the i-th inverter of the second group of inverters is the i-th output of the "Select block" 21 of the control unit.

The encoder 11.1 and the decoder 11.3 are designed to convert one or more low-level signals at one of the inputs of the encoder 11.1 into the binary code of the smallest of them at the output of the decoder 11.3. This conversion is carried out taking into account the priorities of the signals corresponding to the numbers of the inputs. Schemes for their implementation are known and are given, for example, in the book of V. L. Shilo "Popular Digital Microcircuits", M .: "Radio and Communication", 1987, p.147-148.

To explain the operation of the device, consider the following modes of its operation:

device initialization;

the operation of the device upon receipt of the first binary information block (BDI) to be analyzed;

device operation upon receipt of subsequent BDI.

дешифратора 11.3 не используется, поскольку в ситуации, когда все ФВИ заняты, на всех входах "Статус блока" 24₁-24_N блока управления 11 будут установлены логические нули, что приведет к установлению на выходе

дешифратора 11.3 логической единицы. Сигналы с инверсных выходов дешифратора инвертируются второй группой инверторов 11.4₁-11.4_N. Таким образом, на одном из выходов "Выбор блока" 21₁-21_N. блока управления 11, номер которого соответствует наименьшему номеру свободного и готового к работе ФВИ, будет установлена логическая единица, а на всех остальных - логический ноль. В результате инициализации устройства логическая единица установится на первом выходе "Выбор блока" 21₁ блока управления 11. Инициализация устройства заканчивается установкой на входе "Инициализация" 15 устройства логического нуля, который переводит в режим хранения регистр хранения маски 9, а также приводит к установке на выходе двухвходового элемента ИЛИ 1.6 ФВИ логического нуля, что переводит RS-триггер 1.2 ФВИ в режим хранения информации. Процедура инициализации устройства не предусматривает сброс регистров временного хранения 2₁-2_N и по ее завершении в указанных регистрах находится случайная информация.The initialization of the device is as follows. At the M-bit input "Set mask" 16, a bit mask is set whose bit capacity is equal to the bit depth of the analyzed BDI. The bit mask is intended to indicate significant bits of the BDI, through which it is identified. Moreover, the values of the logical unit in the bits of this mask correspond to the positions of the significant bits in the first M-bit information input 12 of the device. In all other positions, logical zero values must be set. At the K-bit input "Storage time code" 14 of the device, a code is set that sets the maximum storage time for a copy of the OBD in the device. The smallest storage time corresponds to the largest code, which is an addition to the maximum number represented in the K-bit code. At the enable input 13, a logical zero is set, and at the input "Initialization" 15 is a logical unit. The logical unit at the input “Initialization” 15 is supplied to the corresponding inputs of the PVI 1 ₁ -1 _N and to the input of the initialization of the mask storage register 9. The logical unit at the input of the initialization of the mask storage register 9 records the bit mask in the register, while the values of the bits are M-bit output 17 of the storage register mask 9 will correspond to the values of the corresponding bits of the mask. A logical zero at the enable input 13 of the device is supplied to the corresponding inputs of the PVI 1 ₁ -1 _N and the first input of the enable three-input element And 6. Moreover, a logical zero at the first input of the enable three-input element And 6 provides the formation of a logical zero at its output, regardless of logical values at its other entrances. Logical zero from the output of the three-input element And 6 goes to the output "Resolution" 29 of the device and the corresponding inputs of the PVI 1 ₁ -1 _N and to the corresponding input of the electronic key 7. Logical zero at the input "Resolution" 29 of the electronic key 7 goes to the corresponding inputs of the two-input elements 7.1 and ₁ -7.1 _M, which ensures the formation at their outputs, and accordingly, all bits of the third M-bit data output device 28 logical zeroes, irrespective of the values of bits of the first M-bit input information 12 apparatus. Logical zero at the output "Resolution" 29 of the device means the lack of information to read on the third M-bit information output 28 of the device. Logical zero at the enabling input 13 of the FVI is fed to the input of the two-input element AND-NOT 1.11, which leads to the appearance of a logical unit at its output, which, entering the second input of the fourth two-input element And 1.10, ensures that the logical value at the output of the fourth two-input element And 1.10 logical value at its first input. Logical zero at the input “Resolution” 29 FVI is fed to the input of the first two-input element And 1, which provides a value of logical zero at its output, which is fed to the input S of the RS-trigger 1.2 and to the output “Set” 22 FVI. The “Installation” output 22 of the FVI is designed to control the recording of information in the corresponding temporary storage register 2. A logical zero at the input S of the RS flip-flop 1.2 simultaneously with a logical unit at its input R coming from the input “Initialization” 15 through a two-input OR 1.6 element, to set the logic trigger 1.2 at the output of the RS flip-flop 1.2, which, in turn, blocks the arrival of 1.8 clock pulses from the second clock input 19 of the FVI to the counting input of the counter, generates a logic zero at the output of the "Block Status" of 24 FVI. The value of logical zero at the output "Status block" 24 FVI means that this FVI is free and ready to work, and in the corresponding register of temporary storage there is information that should not affect the logic of the device. If there is a logic zero at the outputs "Block Status" 24 ₁ -24 _{N of} all PVI 1 ₁ -1 _N at the corresponding inputs of the N-input element OR-NOT 5, control unit 11 and N-input element AND-NOT 10, logical zeros will be set . At the same time, a logical unit will be installed on the inverse output of the N-input element OR-NOT 5, which will go to the second input of the enabling three-input element And 6. At the inverse output of the N-input element AND-NOT 5, a logical unit will also be set, which will go to the third input of the enabling three-input element And 6 and the output "Device Status" 20 device. At the same time, the output of the enabling three-input element And 6 continues to be a logical zero, determined by the presence of a logical zero at its first input. Logical values at the output "Device Status" 20 have the following meaning: a logical unit at the specified output means that the device is ready for operation, and a logical zero - the device is busy. Logical zeros at the inputs "Status block" 24 ₁ -24 _N control unit 11 are supplied to the corresponding inverse inputs of the priority encoder 11.1. In accordance with the logic of work, the P-bit code is set at the output of the priority encoder 11.1, which corresponds to the input number with the highest priority among the inverse inputs on which the logic zero is set (the lower the number of the inverse input, the higher its priority). Next, the first group of inverters 11.2 ₁ -11.2 _P inverted code is converted into a direct and fed to the input of the decoder 11.3. In accordance with the logic of operation, the decoder 11.3 sets a logical zero on one of its N inverse outputs, the number of which corresponds to the code installed on the inputs of the decoder, while a logical unit will be set on the remaining inverse outputs of the decoder. In order to ensure the correct operation of the control unit, the output

the decoder 11.3 is not used, because in a situation where all the FIs are busy, logical zeros will be set at all inputs "Block Status" 24 ₁ -24 _N of the control unit 11, which will lead to the output being set

decoder 11.3 logical units. The signals from the inverted outputs of the decoder are inverted by the second group of inverters 11.4 ₁ -11.4 _N. Thus, at one of the outputs "Block Selection" 21 ₁ -21 _N. control unit 11, the number of which corresponds to the lowest number of free and ready for operation FVI, will be set to a logical unit, and on all others - a logical zero. As a result of initializing the device, the logical unit will be installed on the first output "Select block" 21 ₁ of the control unit 11. Initialization of the device ends with the installation of the logical zero device at the input "Initialization" 15, which translates mask storage register 9 into storage mode, and also leads to installation on the output of the two-input element OR 1.6 FVI logical zero, which puts the RS-trigger 1.2 FVI in the information storage mode. The device initialization procedure does not provide for the reset of the temporary storage registers 2 ₁ -2 _N and, upon its completion, random information is located in the indicated registers.

In the initial period when the BDIs to be analyzed are not received, logical zeros are set on the bits of the first M-bit information input 12, on the enable input 13, the input “Initialization” 15 of the device. The input of the frequency divider 8 through the first clock input 18 of the device from the external generator receives clock pulses. At the K-bit input "Storage time code" 14 of the device, a code is set that sets the maximum storage time for a copy of the OBD in the device. The output "Resolution" 29 of the device is set to logical zero. The output "Device Status" 20 of the device is set to a logical unit. Clock pulses from the second clock output 19 of the frequency divider 8 are supplied to the corresponding inputs of all FVI 1 ₁ -1 _N.

Upon receipt of the first BDI to be analyzed, the logical values corresponding to the values of the BDI bits are set at the first M-bit information input 12 of the device. The point in time corresponding to the installation of the BDI on the first M-bit information input 12 of the device, Fig.6 is designated as t ₁ . From the first M-bit information input 12 of the BDI device it goes to the M-bit information inputs of the temporary storage registers 2 ₁ -2 _N , the first M-bit inputs of the selection blocks 3 ₁ -3 _N and the M-bit input of the electronic key 7. In comparators 3.3 of each selection block 3 ₁ -3 _N , the significant bits of the received BDI are compared with the information in the corresponding temporary storage registers 2 ₁ -2 _N , which is fed to the second M-bit information input 25 of the corresponding selection blocks. Significant bits are allocated in the first and second groups of two-input elements AND 3.1 ₁ -3.1 _M , 3.2 ₁ -3.2 _M selection blocks 3 ₁ -3 _N based on the bit mask received at the M-bit input "Mask" 17. In case of equality of the compared values at the output "A = B" of the comparator 3.3, and, accordingly, at the output "Preliminary result" 26 of the selection block 3 will be set to logical unit, otherwise - logical zero. The receipt of logical values of the results of comparison from the outputs of the "Preliminary result" 26 ₁ -26 _N selection blocks 3 ₁ -3 _N to the inputs of the N-input element OR NOT 5 is regulated by the corresponding two-input elements AND 4 ₁ -4 _N based on the logical values of the outputs "Status block "24 ₁ -24 _N FVI 3 ₁ -3 _N. Moreover, if the output of the “Status block” of the FIW is set to logic zero, then the comparison result obtained in the corresponding selection block is considered invalid and should not affect the decision. Thus, the outputs “Comparison Result” 27 ₁ -27 _{N of} all two-input elements AND 4 ₁ -4 _N will be a logical zero, since in the case under consideration (the arrival of the first BDI), the outputs “Block Status” are 24 ₁ -24 _{N of} all FVI 1 ₁ -1 _N set to logic zero. The values of logical zero at the outputs "Comparison Result" 27 ₁ -27 _N will lead at time t ₂ (see Fig.6) to the formation at the output of the N-input element OR NOT 5 of the final result of comparing the significant bits of the received BDI with the information stored in each of the registers of temporary storage 2 ₁ -2 _N. In this case, the comparison result will be negative and a logical unit will be set at the output of the N-input element OR-NOT 5. The time t ₂ is defined as follows:

where ΔТ _3.1 is the delay time of the parallel operation of the two-input elements And 3.1 ₁ -3.1 _M and 3.2 ₁ -3.2 _M ;

ΔТ _3.3 - delay time of parallel operation of comparators 3.3;

ΔТ _4.1 - the delay time of the parallel operation of the two-input elements And 4 ₁ -4 _N ;

ΔT ₅ - response time of the N-input element OR NOT 5.

The final decision on the possibility of passing the received BDI to the output of the device is made by allowing the three-input element And 6 when the logical unit value from the allowing input 13 is received at its first input. To form an objective decision on the possibility of passing the received BDI to the output of the device, the logical unit at the resolving input 13 of the device is necessary set no earlier than time t ₂ . The logical unit from the enable input 13 of the device will go to the corresponding inputs of the PVI 1 ₁ -1 _N and the first input of the enable three-input element And 6. Moreover, given the presence of logical units at the second and third inputs of the enable three-input element And 6, the logical unit will be established at its output which will go to the output "resolution" device 29, inputs FVI January ₁ -1 _N and input "enable" electronic key 29 7. Logical unit output "Resolution" means the resolution of the device 29 to read the BIA and at time t ₃ is determined emomu like

where ΔТ ₆ is the delay time of the enabling three-input element And 6,

ΔT _7.1 - the delay time of the parallel operation of the two-input elements And 7.1 ₁ -7.1 _M ,

will allow BDI from the first M-bit information input 12 of the device to the third M-bit information output 28 of the device. Thus, the reading of the BDI from the third M-bit information output 28 of the device is possible only after the appearance of a logical unit at the output "Resolution" 29 and not earlier than time t ₃ .

счетчика 1.8 установится логическая единица, которая поступит на второй вход второго двухвходового элемента ИЛИ-НЕ 1.3 и в дальнейшем при отсутствии логической единицы на разрешающем входе 13 будет поддерживать на выходе двухвходового элемента ИЛИ-НЕ 1.3 логический нуль. Логическая единица на входе S RS-триггера 1.2 при наличии логического нуля на его входе R устанавливает на выходе RS-триггера логическую единицу, которая разрешает поступление тактовых импульсов с второго тактового входа 19 на счетный вход "+1" счетчика 1.8 через второй двухвходовый элемент И 1.9 и одновременно поступает на первый вход четвертого двухвходового элемента И 1.10. Логическая единица на выходе "Установка" 22₁ ФВИ 1₁, поступая на вход инициализации регистра временного хранения 2₁, обеспечивает запись в него копии БДИ.At the same time, the input of “Resolution” 29 FVI 1 ₁ -1 _N logical unit initiates the process of writing a copy of the OBD into the temporary storage register (for further comparison with the next incoming OBD) and the process of writing the code for the time of its storage in the counter. The BDI is recorded in the temporary storage register corresponding to the first free FVI. The first free FVI is determined by the control unit 11 by setting the corresponding FVI logical unit at the input "Select block" 21. In the considered mode of operation, the logical unit will be installed at the input "Block Selection" 21 ₁ FVI 1 ₁ . Logical units from the input "Select block" 21 ₁ and enable input 13 FVI 1 ₁ go to the corresponding inputs of the two-input element AND-NOT 1.11 and form a logical zero at its output, which goes to the second input of the fourth two-input element And 1.10. This ensures that the output "Status block" 24 ₁ FVI 1 ₁ logical zero, regardless of the state of the first input of the fourth two-input element And 1.10. In addition, the logical unit installed on the enable input 13 of the FVI 1 ₁ is fed to the first input of the second two-input element OR NOT 1.3, forming a logic zero at its output, which goes to the second input of the third two-input element AND 1.4. At the same time, the output of the third two-input element AND 1.4, regardless of the logical level at its first input, will be set to logical zero, which, if there is a logical zero at the input "Initialization" 15, will ensure the formation of a logical zero at the output of the two-input element OR 1.6, and, accordingly, at the input R RS flip-flop 1.2. The logical unit at the input "Resolution" 29 ₁ simultaneously with the logical unit at the input "Block Selection" 21 ₁ leads to the formation of a logical unit at the output of the first two-input element And 1.1, which is fed to the input S of the RS-trigger 1.2, the first input of the first two-input element OR -NO 1.7 and the output "Installation" 22 FVI. A logical unit at the first input of a two-input OR-NOT 1.7 element generates a logical zero at its output, which, entering the inverse of the write enable input from counter 1.8, writes the code from the K-bit input "Storage time code" 14 of the FVI to counter 1.8. At the same time, the inverse overflow output

counter 1.8, a logical unit will be established, which will go to the second input of the second two-input element OR-NOT 1.3 and subsequently, if there is no logical unit at the enable input 13, it will support a logic zero at the output of the two-input element OR-NOT 1.3. The logical unit at the input S of the RS-trigger 1.2 in the presence of a logical zero at its input R sets the logic unit at the output of the RS-trigger, which allows the receipt of clock pulses from the second clock input 19 to the counting input "+1" of counter 1.8 through the second two-input element And 1.9 and simultaneously enters the first input of the fourth two-input element And 1.10. The logical unit at the output of "Installation" 22 ₁ FVI 1 ₁ , fed to the input of the initialization of the temporary storage register 2 ₁ , provides a copy of the BDI.

To put the device in readiness for receiving the next BDI, it is necessary to set the value of logical zero at the enable input 13 and the bits of the first M-bit information input 12 of the device. Setting a logical zero at the enable input 13 of the device and logical values corresponding to the bits of the BDI on the first M-bit information input 12 of the device can be performed after reading the BDI from the third M-bit information output 28 of the device, but not earlier than time t ₄ , defined as the sum of t ₃ and the maximum of:

the delay time of recording a logical unit in the RS-trigger FVI;

the delay time for the end of the recording of the BDI copy in the temporary storage register;

the total delay time of the first two-input element OR NOT 1.7 and write to the counter 1.8.

Thus, the time t ₄ is determined:

where: ΔT _1.2 is the delay time of recording in the RS-trigger 1.2,

ΔT _2.1 - the delay time of writing to the temporary storage register 2.1,

ΔT _1.7 is the delay time of the first two-input element OR NOT 1.7,

ΔT _1.8 is the delay time for writing to the counter 1.8.

The moment of setting a logical zero at the enable input 13 of the device is indicated in Fig.6 as t ₅ . Logical zero from the enable input 13 of the device goes to the corresponding inputs of the PVI 1 ₁ -1 _N and the first input of the enable three-input element And 6. At the same time, the output of the enable three-input element And 6 sets a logical zero, which goes to the output "Resolution" 29 of the device, input electronic key 7 and the inputs of FVI 1 ₁ -1 _N. A logical zero at the input of the electronic key 7 sets a logical zero on all bits of the third M-bit information output 28 of the device. Logical zero at the enable input 13 of the FVI 1 ₁ will go to the first input of the second two-input element OR-NOT 1.3 and the first input of the two-input element AND-NOT 1.11. Moreover, due to the presence of a logical unit at the second input of the second two-input element OR-NOT 1.3, at its output, and, accordingly, at the output of the third two-input element AND 1.4, logical zero remains. Logical zero at the first input of the two-input element AND-NOT 1.11 leads to the formation of a logical unit at its output, which, entering the second input of the fourth two-input element And 1.10, ensures that the logical value at the output of the fourth two-input element And 1.10 corresponds to the logical value at its first input. Thus, the logical unit at the output of the RS-trigger 1.2 through the fourth two-input element And 1.10 goes to the output "Status block" 24 ₁ FVI. The logical unit from the output "Block Status" 24 ₁ FVI 1 ₁ goes to the second input of the corresponding two-input element And 4 ₁ and the corresponding input of the control unit 11 and the N-input element AND NOT 10. The logical unit at the second input of the two-input element And 4 ₁ in further allows the receipt of the result of comparing the saved copy of the BDI with the newly received BDI. Logical zero received at the input "Resolution" 29 FVI from the output of the enabling three-input element And 6, generates a logical zero at the output of the first two-input element And 1.1, which puts the RS-trigger 1.2 FVI 1 ₁ and the corresponding register of temporary storage 2 ₁ in storage mode. In addition, a logical zero at the output of the first two-input element AND 1.1 in the presence of a logical zero at the input "Comparison result" 27 ₁ FVI forms a logical unit at the inverse output of the first two-input element OR-NOT 1.7, which is fed to the inverse input of the write permission From counter 1.8 and finishes writing the storage time code. The logical unit received from the output "Block status" 24 ₁₄ FVI 1 ₁ to the corresponding input of the control unit 11, initiates the procedure for selecting the next free FVI. At time t ₆ , defined as:

where: ΔТ _1.11 is the delay time of the two-input element AND-NOT 1.11,

ΔT _1.10 - the delay time of the two-input element And 1.10,

ΔT _11.1 is the delay time of the priority encoder 11.1,

ΔT _11.2 - the delay time of the inverter 11.2,

ΔT _11.3 is the delay time of the operation of the decoder 11.3,

ΔT _11.4 - the delay time of the inverter 11.4,

at the output of "Select block" 21 ₂ corresponding to the first free FVI 1 ₂ , a logical unit will be generated, and at the output of "Select block" 21 ₁ corresponding to the considered FVI 1 ₁ , a logical zero will be formed, after which the device is ready to receive the next BDI. Thus, the next BDI can be installed on the first M-bit information input 12 of the device not earlier than time t ₆ .

Upon receipt of subsequent BDI, the operation of the device is as follows. The next BDI is installed at the first M-bit information input 12 of the device and at the inputs of the selection blocks 3 ₁ -3 _N , in which the significant bits of the next BDI are compared with the stored copies of the previously received and stored in the temporary storage registers 2 ₁ -2 _N BDI. The comparison results in the selection blocks 3 ₁ -3 _N are formed at the outputs of the corresponding two-input elements And 4 ₁ -4 _N as follows:

1) a logical zero at the output of the two-input element And will be set in two cases:

1.1) a copy of one of the previously received BDIs is located in the corresponding temporary storage register, but in the selection block there are no matches of significant bits of the received BDI with the stored copy (at the "Preliminary result" output of the corresponding selection block, a logical zero is set, at the "Block status" output of the corresponding FVI installed logical unit);

1.2) there is no information for comparison in the corresponding temporary storage register (the logical unit or logical zero is set at the “Preliminary result” output of the corresponding selection block, and the logical zero is set at the “Block status” output of the corresponding FVI).

2) the logical unit at the output of the two-input element And will be installed in only one case:

2.1) a copy of one of the previously received BDIs is located in the corresponding temporary storage register, and in the selection block, all significant bits of the received BDI match the stored copy (at the output "Preliminary result" of the corresponding block of selection the logical unit is set, at the output "Block Status" of the corresponding FVI installed logical unit).

The comparison results from the outputs of the two-input elements AND 4 ₁ -4 _N go to the corresponding inputs of the N-input element OR-NOT 5, at the output of which a logical unit will be formed only if all the inputs are set to logic zero. This means that there are no matches between the significant bits of the analyzed BDI and the copies of the previous BDI stored in the temporary storage registers. The logical value from the output of the N-input element OR-NOT 5 goes to the second input of the enabling three-input element And 6, which, after installing a logical unit at the enable input 13 of the device, generates a logical value at its output that determines the possibility of passing the analyzed BDI to the output of the device. In this case, the formation of a logical value at the output of the enabling three-input element And 6 occurs as follows:

1) the logical unit at the output of the enabling three-input element And 6 will be formed if there is a logical unit at the output "Device Status" 20 N-input element AND-NOT 10, the presence of a logical unit at the enable input 13 and the presence of a logical unit at the output of the N-input element OR NOT 5;

2) a logical zero at the output of the enabling three-input element And 6 will be formed in the case of a logical zero at any of its inputs.

The logical value generated at the output of the enabling three-input element And 6 after installing a logical unit at the enabling input of the device 13 determines not only the possibility of passing the analyzed BDI to the third M-bit information output 28 of the device, but also the further operation of the device associated with the processing of this BDI.

If a logical unit is established at the output of the enabling three-input element And 6, this will mean that the significant bits of the received BDI did not match any of the stored copies of the previous BDI and, in accordance with the logic of the device, a copy of the received BDI should be recorded in the first free temporary storage register determined by the control unit, and the storage time code must be recorded in the counter of the corresponding PVI. The operation of the device for recording a copy of the BDI and setting the storage time is carried out similarly to the above-described operation of the device upon receipt of the first BDI.

If the output of the enabling three-input element And 6 is set to logic zero, this will mean the coincidence of the significant bits of the received BDI with the significant bits of one of the stored copies of the previous BDI. In this case, in accordance with the logic of the device’s operation, the analyzed BDI should not go to the device’s output, and the countdown of the storage time of the corresponding copy of the BDI should be started from the moment of establishing the retry by overwriting the storage time code in the PVI corresponding to the temporary storage register in which it was found match significant bits. In this case, the operation of the device is as follows. The output "Resolution" 29 enabling three-input element And 6 continues to remain a logical zero, which prevents the newly received BDI from passing to the third M-bit information output 28 of the device. A logical unit is installed at the enable input 13 of all FVI 1 ₁ -1 _N , which prohibits the reset of counter 1.8 by blocking the logic zero from the overflow output P of counter 1.8 to the input of a two-input OR-NOT 1.3 element and simultaneously blocks the change of the logical value at the output "Block status "24 FVI. At the same time, at the input “Result of comparison” 27 FVI, corresponding to the register of temporary storage in which a match of significant bits was found, a logical unit will be set. The logical unit from the input “Result of comparison” 27 of the specified PVI is fed to the second input of the first two-input element OR NOT 1.7, at the inverse output of which a logical zero is formed. Logical zero from the inverse output of the first two-input element, OR NOT 1.7, goes to the inverse of the write enable input from counter 1.8, which leads to writing to the counter 1.8 the storage time code installed on the K-bit input "Storage time code" 14 of the FVI. Translation of the device in readiness to receive the next BDI is carried out by setting a logical zero at the enable input 13 of the device. Setting a logical zero at the enable input 13 of the device should be performed no earlier than time t ₄ (see Fig.6).

счетчика 1.8 формируется логический нуль, который поступает на второй вход второго двухвходового элемента ИЛИ-НЕ 1.3 и при условии наличия логического нуля на разрешающем входе 13 ФВИ формирует на инверсном выходе двухвходового элемента ИЛИ-НЕ 1.3 логическую единицу. Логическая единица на инверсном выходе двухвходового элемента ИЛИ-НЕ 1.3 в совокупности с логической единицей на выходе RS-триггера 1.2 формирует на выходе третьего двухвходового элемента И 1.4 логическую единицу, которая поступает на вход сброса R счетчика 1.8 и второй вход двухвходового элемента ИЛИ 1.6. Логическая единица на входе R счетчика 1.8 осуществляет его сброс. Логическая единица на втором входе двухвходового элемента ИЛИ 1.6 формирует на его выходе логическую единицу, которая поступает на вход R RS-триггера 1.2. При этом на выходе RS-триггера 1.2 формируется логический нуль, так как к моменту поступления на его вход R логической единицы на его входе S будет установлен логический нуль. Логический нуль с выхода RS-триггера 1.2 поступает на второй вход второго двухвходового элемента И 1.9, первый вход третьего двухвходового элемента И 1.4 и первый вход четвертого двухвходового элемента И 1.10. Логический нуль на втором входе второго двухвходового элемента И 1.9 блокирует поступление тактовых импульсов с второго тактового входа ФВИ на счетный вход счетчика 1.8. Логический нуль на первом входе третьего двухвходового элемента И 1.4 приводит к формированию на его выходе логического нуля, который поступает на вход R счетчика 1.8 и через двухвходовый элемент ИЛИ 1.6 на вход R RS-триггера 1.2. Логический нуль на входе R RS-триггера 1.2 совместно с логическим нулем на его S-входе переводит RS-триггер 1.2 в режим хранения информации. Логический нуль на первом входе четвертого двухвходового элемента И 1.10 приводит к безусловному формированию на его выходе, а соответственно, и на выходе "Статус блока" 24 ФВИ логического нуля. Логический нуль с выхода "Статус блока" 24 ФВИ поступает на соответствующий вход блока управления 11.After the time set for storing one or several copies of the BDI, they are destroyed by resetting the corresponding FVI and bringing them into a state of readiness to receive the next BDI. Resetting the PVI is possible only at time intervals when a logic zero is set at enable input 13, i.e. when the BDI analysis does not occur. After the expiration of the storage time of the BDI copy in the counter 1.8 of the corresponding FVI, overflow occurs. In this case, the overflow output

counter 1.8, a logical zero is generated, which is fed to the second input of the second two-input element OR-NOT 1.3 and, provided that there is a logical zero at the enable input 13, the FII forms a logical unit on the inverse output of the two-input element OR-NOT 1.3. The logical unit at the inverted output of the two-input element OR-NOT 1.3 together with the logical unit at the output of the RS-trigger 1.2 forms the logical unit at the output of the third two-input element AND 1.4, which is fed to the reset input R of counter 1.8 and the second input of the two-input element OR 1.6. The logical unit at the input R of counter 1.8 performs its reset. The logical unit at the second input of the two-input element OR 1.6 forms a logical unit at its output, which is fed to the input R of the RS-trigger 1.2. At the same time, a logic zero is formed at the output of the RS flip-flop 1.2, since by the moment R of a logical unit arrives at its input, a logical zero will be set at its input S. Logical zero from the output of the RS-trigger 1.2 goes to the second input of the second two-input element And 1.9, the first input of the third two-input element And 1.4 and the first input of the fourth two-input element And 1.10. Logical zero at the second input of the second two-input element And 1.9 blocks the receipt of clock pulses from the second clock input of the FVI to the counting input of the counter 1.8. Logical zero at the first input of the third two-input element And 1.4 leads to the formation of a logical zero at its output, which goes to the input R of the counter 1.8 and through the two-input element OR 1.6 to the input R of the RS-trigger 1.2. Logical zero at the input R of the RS-trigger 1.2 together with the logic zero at its S-input puts the RS-trigger 1.2 in the information storage mode. Logical zero at the first input of the fourth two-input element And 1.10 leads to the unconditional formation on its output, and, accordingly, at the output "Status block" 24 FVI logical zero. Logical zero from the output "Status block" 24 FVI is fed to the corresponding input of the control unit 11.

During the operation of the device, a situation may arise in which all the temporary storage registers 2 ₁ -2 _N will be used to store copies of previously received OBI. At the same time, at the outputs "Block Status" 24 ₁ -24 _{N of} all FVI 1 ₁ -1 _N, a logical unit will be set, which will lead to the formation of an inverse output of the N-input element AND-NOT 10 logical zero. Logical zero from the inverse output of the N-input element AND-NOT 10 is fed to the third input of the enabling three-input element And 6 and to the output "Device status" 20 of the device. Logical zero at the third input of the enabling three-input element And 6 will lead to the unconditional formation at its output, and, accordingly, at the output of "Resolution" 29 of a logical zero, which in turn blocks the passage of newly received BDI to the third M-bit information output 28 of the device through electronic key 7. In this case, the value of the logical zero at the output "Device Status" 20 will mean that the device is busy and not ready to receive the next BDI, and the value of the logical zero at the output "Resolution" 29 of the device is missing the presence on the third M-bit information output 28 of the information device for reading. Thus, blocking the passage of newly arriving BDI to the third M-bit information output 28 of the device will continue until the expiration of the storage time for one or more stored copies of the BDI. In this case, the operation of the device depends on the options for its use.

The first use case of the device is that the next BDIs do not supply to the first M-bit information input 12 of the device until the value at the output “Device Status” 20 of the device changes. Formation of the logical unit 20 at the inverted output of the N-input element AND-NOT 10, and, accordingly, at the output "Device Status" 20 after the expiration of the storage time of one or more copies of the BDI in the temporary storage and reset registers of the corresponding FVI.

The second use of the device is that the next BDI is fed to the first M-bit information input 12 of the device (together with a change in the values at input 13). In this case, each newly arriving BDI to the output of the device is not skipped, but significant bits are compared with the stored BDIs and, in the case of a positive result, the storage time code is overwritten in the corresponding FVI.

Thus, the proposed device performs the following functions to control incoming BDI:

Allows the entry to the output of the first BDI;

saves a copy of the BDI for a specified storage time of a copy of the BDI and allows you to change the storage time of a copy of the BDI during the operation of the device;

makes a decision on the arrival of the next BDI on the output of the device by comparing its significant bits with the corresponding bits of the stored copies of the BDI;

saves the position of significant bits and allows them to dynamically change during the operation of the device;

blocks the arrival of the next BDI to the output of the device when all the registers for temporary storage of the device are filled.

Claims (5)

1. An information retrieval device, comprising N time interval shapers, where N≥1, N selection blocks, a frequency divider whose input is a clock input of a device, characterized in that N temporary storage registers, N two-input elements AND, allowing a three-input element, are additionally introduced AND, N-input element OR-NOT, electronic key, mask storage register, N-input element NAND, control unit, while the output of the frequency divider is connected to the clock inputs of the shapers of time intervals corresponding to p the ranks of the K-bit inputs "Storage time code", where K≥1 is the bit length of the storage time code, time interval shapers are interconnected and are the corresponding bits of the K-bit input "Storage time code" of the device, allowing the inputs of N time interval shapers and the first the input of the enabling three-input element And are interconnected and are the enabling input of the device, the corresponding bits of M-bit information inputs, where M≥1 is the number of binary bits of the analyzed block inf rations, N registers of temporary storage, N blocks of selection and an electronic key are interconnected and are the corresponding bits of the first M-bit information input of the device, inputs “Initialization” of N shapers of the time interval and register of storage of the mask are interconnected and are the input of initialization of the device, output enabling three-input element And is connected to the inputs "Resolution" of the shapers of time intervals, an electronic key and is the output "Resolution" of the device, the i-th output is "Select lock ", where i = 1, 2 ... N, of the control unit is connected to the input" Select block "of the i-th driver of time intervals, the output of the i-th two-input element AND is connected to the i-th input of the N-input element OR NOT and the input "Result of comparison" of the i-th time slot former, the output "Installation" of the i-th time gap former is connected to the input "Installation" of the i-th temporary storage register, the output "Status block" of the i-th time interval former is connected to the second the input of the i-th two-input element And, the i-th input of the control unit and the i-th input of N-inputs of the NAND input element, the output of the N-input NAND input element is connected to the third input of the enabling three-input And element and is the output of the "Device Status" of the device, the bits of the M-bit input "Set mask" of the mask storage register are the corresponding bits of the M-bit input The “mask setting” of the device, and the bits of the M-bit output of the mask storage register are connected to the corresponding bits of the M-bit inputs of the “Mask” N selection blocks, the M-bit output of the i-th temporary storage register is connected to the second M-bit information input of the i-th selection block, the output of the "Preliminary result" of the i-th selection block is connected to the first input of the i-th two-input element And the output of the N-input element OR is NOT connected to the second input of the enabling three-input element And, and M-bit the electronic key information output is an M-bit information output of the device. 2. The device according to claim 1, characterized in that the shaper of the time intervals consists of the first, second, third and fourth two-input elements AND, the first and second two-input elements OR-NOT, two-input element AND-NOT, two-input element OR, RS-trigger , the counter, while the K-bit input of the counter is the K-bit input "Shorter storage code" for the shaper, the first input of the first two-input element AND is connected to the second input of the two-input element AND NOT and is the input "Select block" of the shaper, the second input is of the two-input element AND is the “Resolution” input of the driver, the output of the first two-input element AND is connected to the S-input of the RS-flip-flop, the first input of the first two-input element OR-NOT and is the output “Installation” of the driver, the second input of the first two-input element OR-NOT is input "Comparison Result" of the driver, the output of the first two-input element OR is NOT connected to the inverse installation input of the counter, the first input of the two-input element OR is the input "Initialization" of the driver, the output is two of the OR element is connected to the R-input of the RS-flip-flop, the output of which is connected to the first input of the third two-input element And, the second input of the second two-input element And and the first input of the fourth two-input element And, the output of which is the “Block status” output of the driver, the first input of the second the two-input element And is the clock input of the shaper, the output of the second two-input element And is connected to the counting input of the counter, the inverse overflow output of which is connected to the second input of the second two-input element that OR-NOT, the output of which is connected to the second input of the third two-input element And, the output of which is connected to the reset input of the counter and the second input of the two-input element OR, the output of the two-input element AND is NOT connected to the second input of the fourth two-input element And, and the first input of the second two-input element The OR-NOT element is connected to the first input of the two-input AND-NOT element and is the enable input of the driver. 3. The device according to claim 1, characterized in that the selection block consists of the first and second groups of two-input elements And M elements in each group and a comparator, while the first input of the j-th two-input element And the first group of two-input elements And, where j = 1, 2 ... M, is the j-th bit of the first M-bit information input of the selection block, the first input of the j-th two-input element And the second group of two-input elements And is the j-th bit of the second M-bit information input of the selection block, the second input of the j-th two-input element And the first group of two-input elements And is connected to the second input of the j-th two-input element And the second group of two-input elements And is the j-th bit of the M-bit input "Mask" of the selection block, the output of the j-th two-input element And the first group of two-input elements And is connected to the j-th information input of the first group of information inputs of the comparator, the output of the j-th two-input element And the second group of two-input elements And is connected to the j-th information input of the second group of information inputs of the comparator, and the output of the equality of comp Rathore is the output of "preview result" selection unit. 4. The device according to claim 1, characterized in that the electronic key consists of M two-input elements And, while the first input of the j-th two-input element And, where j = 1, 2 ... M, is the j-th discharge M- bit information input of the electronic key, the second inputs of the two-input elements And are interconnected and are the input "Resolution" of the electronic key, the output of the j-th two-input element And is the j-th bit of the M-bit information output of the electronic key. 5. The device according to claim 1, characterized in that the control unit consists of a priority encoder, the first group of inverters from P inverters, where

the second group of inverters from N inverters, a decoder, while the i-th inverse input of the priority encoder is the i-th input "Status block" of the control unit, the k-th inverse output of the priority encoder, where k = 1, 2 ... P, is connected with the input of the k-th inverter of the first group of inverters, the output of which is connected to the k-th input of the decoder, the i-th inverse output of which is connected to the input of the i-th inverter of the second group of inverters, and the output of which is the i-th output of the "Select block" block management.

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