CN111177057B

CN111177057B - Bus code transmitting circuit and method, bus transmission system

Info

Publication number: CN111177057B
Application number: CN201811348164.8A
Authority: CN
Inventors: 王江嵋; 崔明艳
Original assignee: Loongson Technology Corp Ltd
Current assignee: Loongson Technology Corp Ltd
Priority date: 2018-11-13
Filing date: 2018-11-13
Publication date: 2021-08-03
Anticipated expiration: 2038-11-13
Also published as: CN111177057A

Abstract

The invention provides a bus code sending circuit and method and a bus transmission system. The circuit includes: the phase sorting unit and the delay processing unit are connected in sequence. The phase arrangement unit may arrange the initial phases of the individual bits in the initial bus signal into the same phase. The delay processing unit groups each signal bit in the bus signal after being sorted according to the hopping direction of each signal bit in the initial bus signal to obtain a grouped bus signal which at least comprises two signal bit groups and the hopping direction of each signal bit in any signal bit group is the same, and then performs non-zero delay on all signal bit groups in the same hopping direction in the grouped bus signal according to a preset delay mode to obtain a delayed bus signal, and sends the delayed bus signal to a bus decoding receiving circuit. The invention eliminates the worst crosstalk condition and reduces the transmission delay caused by crosstalk on the premise of not changing the wiring resource requirement.

Description

Bus code transmitting circuit and method, bus transmission system

Technical Field

The invention relates to the technical field of microelectronics, in particular to a bus code sending circuit and method and a bus transmission system.

Background

In an integrated circuit design, when a signal of multiple bits, such as a 16-bit data signal or a 32-bit data signal, is transmitted, a bus method is often used for transmission. Since a bus is a set of signal lines, one signal line transmits one bit of data, and therefore, a signal of multiple bits of data can be transmitted through one set of signal lines, which is generally referred to as a bus signal.

Different from the transmission mode of a signal of one bit of data, the arrangement of each signal wire for transmitting the bus signal is relatively dense and neat, the lengths of the signal wires are equivalent, the surrounding electromagnetic environments are similar, the bus signal can reach a plurality of receiving ends at the same time after being sent from a sending end, and the bus signal transmission method has consistency. However, in a group of signal lines, as the distance between adjacent signal lines and the aspect ratio of the signal line are reduced, the coupling capacitance Ci between adjacent signal lines is close to or even much larger than the ground capacitance Cl, and the increasing coupling capacitance Ci may cause a phase of a signal bit (herein, one signal bit refers to one bit of data) transmitted on the adjacent signal lines to jump, thereby generating serious crosstalk. The crosstalk, especially the worst case crosstalk, has become a main factor affecting the timing and clock cycle of the bus signal, and the crosstalk occurring in the timing and clock cycle of the bus signal is liable to cause the function degradation and function error of the integrated circuit; at the same time, the crosstalk also increases power consumption and noise of data transmitted on the respective signal lines. The worst case crosstalk refers to both 1+3 λ and 1+4 λ, λ is a delay constant introduced by crosstalk, and λ ═ Ci/Cl. Thus, eliminating the effects of worst-case crosstalk on the delay, power consumption, and noise of data transmitted on individual signal lines is a problem that must be considered in the design of high-performance integrated circuits.

In the prior art, three coding methods, namely, increasing line spacing, spatial coding and bus coding are often adopted to eliminate the worst crosstalk. The method comprises the following steps that the distance between adjacent signal lines is increased, so that the coupling capacitance can be reduced, further the crosstalk can be reduced, specifically, the distance between each signal line can be forcibly regulated in the wiring process, but too much wiring resources can be occupied, and the method is not suitable for integrated circuits with wiring resource limitation; the spatial coding is that a shielding line is arranged in parallel at two sides of each signal line to block crosstalk invasion of other signal lines, but coupling capacitance still exists between the signal lines and the shielding lines; bus coding is usually based on the worst vector theory, an encoder is added at a sending end, the worst vector (namely, the situation that signal bits respectively transmitted by adjacent signal lines jump reversely at the same time) which can occur in the process of transmitting bus signals of the encoder is processed into a non-worst vector in a bus coding mode, but redundant signal lines can still be added while bus crosstalk is eliminated in the bus coding mode, and further excessive wiring resources are occupied.

Therefore, a need exists for a bus coding transmission method that can reduce crosstalk without increasing routing resources.

Disclosure of Invention

The invention provides a bus coding transmitting circuit and method and a bus transmission system, which can reduce the influence of crosstalk among signal bits and transmission delay caused by the crosstalk and the like on the premise of not increasing wiring resources.

In a first aspect, the present invention provides a bus encoding transmission circuit, including: the phase sorting unit and the delay processing unit are connected in sequence;

the phase sorting unit is used for sorting the initial phases of all signal bits in the initial bus signal into the same phase; sending the bus signal after being sorted to the delay processing unit;

the delay processing unit is used for grouping each signal bit in the bus signal after the arrangement according to the hopping direction of each signal bit in the initial bus signal to obtain a grouped bus signal; the grouped bus signals comprise at least two signal bit groups, the hopping direction of each signal bit hopped in any signal bit group is the same, and the hopping direction of any signal bit group is the same as that of any signal bit hopped in any signal bit group;

the delay processing unit is further configured to delay all signal bit groups in the same hopping direction in the grouped bus signals according to a preset delay manner, so as to obtain delayed bus signals; and sending the delayed bus signal to a bus decoding receiving circuit; the preset delay mode is a mode that the delay time length corresponding to each signal bit in all the signal bit groups in the same hopping direction is set to be nonzero.

Optionally, the delay durations corresponding to the signal bits in all the signal bit groups in the same hopping direction are set to be the same or different.

Optionally, the delay processing unit includes: a jump judging unit, a signal bit grouping unit and a phase delay unit;

the signal bit grouping unit is respectively connected with the phase sorting unit, the phase sorting unit and the phase delay unit;

the jump judging unit is used for receiving the initial bus signal; judging whether the hopping direction of each signal bit in the initial bus signal is a target hopping direction or not to obtain a judgment result;

the signal position grouping unit is used for receiving the bus signals after being arranged and sent by the phase arranging unit and receiving the judging results sent by the jump judging unit; grouping each signal position in the bus signal after being sorted according to the judgment result to obtain the grouped bus signal;

the phase delay unit is configured to delay all signal bit groups in the same hopping direction in the grouped bus signals according to the preset delay manner, so as to obtain the delayed bus signals;

the phase delay unit is further configured to send the delayed bus signal to the bus decoding receiving circuit.

Optionally, the signal bit grouping unit is specifically configured to divide signal bits in the initial bus signal, where a hopping direction of the initial bus signal is the same as the target hopping direction, into a first signal bit group corresponding to signal bits in the sorted signal bit group, and divide remaining signal bits in the sorted bus signal into a second signal bit group, so as to obtain the grouped bus signal; wherein, the second signal bit group comprises signal bits in the initial bus signal, the hopping direction of which is opposite to the target hopping direction, and the signal bits in the bus signal after arrangement and the signal bits in the initial bus signal, which do not hop, correspond to the signal bits in the bus signal after arrangement respectively; alternatively, the first and second electrodes may be,

dividing signal bits in the initial bus signal, of which the hopping direction is opposite to the target hopping direction, into a first signal bit group corresponding to the signal bits in the organized signal bit group respectively, and dividing the remaining signal bits in the organized bus signal into a second signal bit group to obtain the grouped bus signals; wherein, the second signal bit group comprises signal bits in the initial bus signal, the hopping direction of which is the same as the target hopping direction, and the signal bits in the bus signal after the arrangement and the signal bits in the initial bus signal, which do not hop, correspond to the signal bits in the bus signal after the arrangement respectively; alternatively, the first and second electrodes may be,

dividing the signal bits in the initial bus signal, which have the same hopping direction as the target hopping direction, into a first signal bit group corresponding to the signal bits in the organized signal bit group respectively, dividing the signal bits in the initial bus signal, which have the hopping direction opposite to the target hopping direction, into a second signal bit group corresponding to the signal bits in the organized signal bit group respectively, and dividing the signal bits in the initial bus signal, which do not hop, into a third signal bit group corresponding to the signal bits in the organized signal bit group respectively.

Optionally, the delay time length corresponding to each signal bit in all the signal bit groups in the same hopping direction has an association relationship with a preset time length, and the preset time length is obtained according to a formula (1);

Δ T ═ [ (β - α) × λ ] × T + γ formula (1);

wherein Δ T is the preset time duration, T is the clock cycle of the initial bus signal, α is the ratio of the interval time duration between the initial time and the delayed initial time of the clock signal to T, the clock signal is a signal for controlling the grouped bus signal transmission, β is the ratio of the interval time duration between the initial time and the delayed termination time of the clock signal to T, γ is a correction value, and λ is a delay constant.

In a second aspect, the present invention provides a bus encoding and transmitting method, including:

arranging the initial phases of all signal bits in the initial bus signal into the same phase to obtain an arranged bus signal;

grouping each signal bit in the bus signal after being sorted according to the hopping direction of each signal bit in the initial bus signal to obtain a grouped bus signal; the grouped bus signals comprise at least two signal bit groups, the hopping direction of each signal bit hopped in any signal bit group is the same, and the hopping direction of any signal bit group is the same as that of any signal bit hopped in any signal bit group;

delaying all signal bit groups in the same jumping direction in the grouped bus signals according to a preset delay mode to obtain delayed bus signals; the preset delay mode is a mode that delay time lengths corresponding to all signal bits in all signal bit groups in the same hopping direction are set to be nonzero;

and sending the delayed bus signal to a bus decoding receiving circuit.

Optionally, before the grouping, according to the hopping direction of each signal bit in the initial bus signal, each signal bit in the sorted bus signal to obtain a grouped bus signal, the method further includes:

judging whether the hopping direction of each signal bit in the initial bus signal is a target hopping direction or not to obtain a judgment result;

the grouping each signal bit in the bus signal after the arrangement according to the hopping direction of each signal bit in the initial bus signal to obtain a grouped bus signal includes:

and grouping each signal bit in the bus signal after the arrangement according to the judgment result to obtain the grouped bus signal.

Optionally, the grouping, according to the determination result, each signal bit in the sorted bus signal to obtain the grouped bus signal includes:

dividing signal bits in the initial bus signal, the hopping direction of which is the same as the target hopping direction, into a first signal bit group corresponding to the signal bits in the organized signal bit group, and dividing the remaining signal bits in the organized bus signal into a second signal bit group to obtain the grouped bus signals; wherein, the second signal bit group comprises signal bits in the initial bus signal, the hopping direction of which is opposite to the target hopping direction, and the signal bits in the bus signal after arrangement and the signal bits in the initial bus signal, which do not hop, correspond to the signal bits in the bus signal after arrangement respectively; alternatively, the first and second electrodes may be,

Δ T ═ [ (β - α) × λ ] × T + γ formula (1);

In a third aspect, the present invention provides a bus transmission system, including: a bus decoding receiving circuit and a bus encoding transmitting circuit as described in the first aspect.

In a fourth aspect, the present invention provides a computer-readable storage medium having stored thereon a computer program which, when executed by a processor, implements the bus code transmission method of the second aspect.

In a fifth aspect, the present invention provides an electronic device, comprising:

a processor; and

a memory for storing executable instructions of the processor;

wherein the processor is configured to perform the bus encoded transmission method of the second aspect via execution of the executable instructions.

On one hand, the initial phases of all signal bits in the initial bus signal are arranged into the same phase through the phase arranging unit to obtain the arranged bus signal, so that the arranged bus information is convenient to perform corresponding operation subsequently, and the phenomenon that the signal bits are simultaneously subjected to reverse jump due to different initial phases of all the signal bits and the subsequent operation loses the original effect because the signal bits are directly acted on the initial bus signal and the phenomenon that the signal bits are simultaneously subjected to reverse jump due to different initial phases of all the signal bits is avoided; on the other hand, the delay processing unit groups each signal bit in the bus signal after being sorted according to the jumping direction of each signal bit in the initial bus signal, divides each signal bit into at least two signal bit groups, and obtains the grouped bus signal. Because the hopping directions of the signal bits hopped in any signal bit group are the same, and the hopping direction of any signal bit group is the same as that of any signal bit hopped in any signal bit group, the delay processing unit selects all signal bit groups in any hopping direction from the grouped bus signals, and carries out non-zero delay on all signal bit groups in the same hopping direction according to a preset delay mode to obtain a delayed bus signal, so that the signal bits hopped in the reverse direction at the same time can be transmitted in a time-sharing manner, and the delay processing unit can send the delayed bus signal to the bus decoding receiving circuit. In the invention, the signal bits which simultaneously generate reverse jump are transmitted in a time-sharing way, so that the occurrence of worst crosstalk is eliminated, the transmission delay influence caused by the crosstalk is reduced, no additional wiring resource is required to be added, and the resource and the power consumption of a corresponding part of circuits are saved.

Drawings

In order to clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

Fig. 1 is a schematic structural diagram of a bus encoding transmission circuit provided in the present invention;

FIG. 2 is a schematic structural diagram of a bus encoding transmission circuit according to the present invention;

FIG. 3 is a flow chart of a bus code transmission method provided by the present invention;

FIG. 4 is a schematic structural diagram of a bus transmission system according to the present invention;

fig. 5 is a schematic diagram of a hardware structure of the electronic device provided by the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments obtained by persons of ordinary skill in the art based on the embodiments of the present invention without any creative efforts shall fall within the protection scope of the embodiments of the present invention.

Fig. 1 is a schematic structural diagram of a bus code transmitting circuit provided in the present invention, and as shown in fig. 1, a bus code transmitting circuit 10 of the present embodiment includes: a phase sorting unit 11 and a delay processing unit 12 connected in sequence.

The phase arrangement unit 11 is configured to arrange the initial phases of the signal bits in the bus signal into the same phase; and sends the collated bus signal to the delay processing unit 12.

The delay processing unit 12 is configured to group each signal bit in the sorted bus signal according to a hopping direction of each signal bit in the initial bus signal, so as to obtain a grouped bus signal; the grouped bus signals comprise at least two signal bit groups, the jumping direction of each signal bit jumping in any signal bit group is the same, and the jumping direction of any signal bit group is the same as that of any signal bit jumping in any signal bit group.

The delay processing unit 12 is further configured to delay all signal bit groups in the same hopping direction in the grouped bus signals according to a preset delay manner, so as to obtain delayed bus signals; and the delayed bus signal is sent to a bus decoding receiving circuit; the preset delay mode is a mode of setting the delay time length corresponding to each signal bit in all signal bit groups in the same jump direction to be nonzero.

Specifically, as those skilled in the art will readily understand, no matter what type of wiring is used in the integrated circuit, if the delay constant introduced by crosstalk is λ, λ is Ci/Cl, Ci is a coupling capacitor, and Cl is a ground capacitor, the adjacent signal bits in the bus signal will jump differently, and the delay introduced by crosstalk will be different. In the following, referring to table 1, taking the rising edge jump of the K-th signal bit in the bus signal as an example, where K is a positive integer, when the K-1-th signal bit and the K + 1-th signal bit jump in different directions or do not jump, different crosstalk delays caused by the K-th signal bit are indicated. Wherein, "meshed" represents a rising edge transition direction, "↓" represents a falling edge transition direction, and "-" represents a non-occurrence transition direction.

TABLE 1

Specifically, when the K-1 th signal bit and the K +1 th signal bit jump in the same direction as the K-th signal bit, the delay time length coefficient causing the K-th signal bit crosstalk is 1, which may reduce the signal transmission delay. And when any one of the K-1 signal position and the K +1 signal position jumps in the same direction with the K signal position at the same time and the other signal position does not jump, the time delay duration coefficient causing the crosstalk of the K signal position is 1+ lambda. When the K-1 signal position and the K +1 signal position do not hop, the K signal position hops, or any one of the K-1 signal position and the K +1 signal position hops with the K signal position at the same time, and meanwhile, when another signal position is compared with any one of the signal positions to hop reversely, the time delay time length coefficient causing the K signal position to crosstalk is 1+2 lambda. When the K-1 signal position does not hop, the K +1 signal position and the K signal position simultaneously reversely hop, or the K +1 signal position does not hop, and the K-1 signal position and the K signal position simultaneously reversely hop, the time delay duration coefficient causing the K signal position to crosstalk is 1+3 lambda. When the K-1 signal position and the K +1 signal position hop in the same direction at the same time and the K signal position is compared with the K-1 signal position or the K +1 signal position and hops in the opposite direction, the time delay duration coefficient causing the K signal position to have crosstalk is the largest and the size is 1+4 lambda.

Therefore, except for the condition that adjacent signal bits in the bus signal jump in the same direction at the same time, the coupling effect is larger in other conditions, and the influence of the caused signal transmission delay is larger. Therefore, for the above situation causing the worst case crosstalk, in this embodiment, the bus code transmitting circuit 10 performs time-sharing transmission on signal bits with opposite hopping directions in the sorted bus signals through the phase sorting unit 11 and the delay processing unit 12, so as to eliminate the occurrence of the worst case crosstalk, slow down the transmission delay influence caused by the worst case crosstalk, and eliminate the need to add extra routing resources and determine the occurrence and direction of each signal bit hopping, thereby saving resources and power consumption consumed by corresponding parts of circuits.

Specifically, the phase arrangement unit 11 may obtain the initial phase of each signal bit in the initial bus signal first, and arrange the initial phase of each signal bit into the same phase, so as to ensure that the initial phase of each signal bit after arrangement is the same, avoid directly acting on the initial bus signal and easily cause the phenomenon that each signal bit simultaneously generates reverse jump due to the difference of the initial phase of each signal bit, and thereby the bus signal after arrangement is convenient for subsequent various operations.

The phase sorting unit 11 may be an integrated chip, an integrated circuit with a phase sorting function built by a plurality of components, or a processor, which is not limited in this embodiment. For example, the phase sorting unit 11 may be a phase sorter.

Further, after receiving the initial bus signal, the delay processing unit 12 can determine the transition direction of each signal bit in the initial bus signal. Generally, any bit in the initial bus signal may or may not have a transition. And when the signal bit jumps, the jump direction of the signal bit is the jump direction of the rising edge or the jump direction of the falling edge.

Further, the delay processing unit 12 may also receive the collated bus signal sent by the phase collating unit 11. Furthermore, the delay processing unit 12 may group each signal in the received sorted bus signals according to the transition direction of each signal bit in the initial bus signal, so as to obtain the grouped bus signals. And the grouped bus signal comprises at least two signal bit groups, the jumping direction of each signal bit jumping in any signal bit group is the same, and the jumping direction of any signal bit group is the same as the jumping direction of any signal bit jumping in any signal bit group. Wherein, there is the one-to-one correspondence in the signal position in the initial bus signal and the signal position in the bus signal after the arrangement, for example, contain signal position 1 in the initial bus signal, signal position 2 and signal position 3, arrange into the same phase to the initial phase of each signal position in the initial bus signal, be about to signal position 1 arrangement for signal position 1', signal position 2 arrangement for signal position 2', arrange signal position 3 for signal position 3', make and contain signal position 1', signal position 2' and signal position 3' in the bus signal after the arrangement, at this moment, signal position 1 and signal position 1' are the corresponding relation, signal position 2 and signal position 2' are the corresponding relation, signal position 3 and signal position 3' are the corresponding relation.

In this embodiment, the number of groups included in the grouped bus signals is not limited, and it is only necessary that the hopping directions of the signal bits that hop in any signal bit group are the same.

The following description will be given by way of example to the operation of the bus code transmission circuit 10: the method comprises the following steps that an initial bus signal is assumed to comprise a signal bit 1, a signal bit 2, a signal bit 3, a signal bit 4, a signal bit 5, a signal bit 6, a signal bit 7 and a signal bit 8 which are adjacent to each other, wherein the hopping directions of the signal bit 1, the signal bit 2, the signal bit 3 and the signal bit 4 are the same, the hopping directions of the signal bit 5, the signal bit 6, the signal bit 7 and the signal bit 8 are the same, and the hopping directions of the signal bit 1 and the signal bit 5 are different; correspondingly, arrange in order the initial phase of signal position 1 and obtain signal position 1', arrange in order the initial phase of signal position 2 and obtain signal position 2', arrange in order the initial phase of signal position 3 and obtain signal position 3', arrange in order the initial phase of signal position 4 and obtain signal position 4', arrange in order the initial phase of signal position 5 and obtain signal position 5', arrange in order the initial phase of signal position 6 and obtain signal position 6', arrange in order the initial phase of signal position 7 and obtain signal position 7', arrange in order the initial phase of signal position 8 and obtain signal position 8'. Therefore, the delay processing unit 12 can divide the signal bits 1', 2', 3', and 4' in the sorted bus signals into one group, and divide the signal bits 5', 6', 7', and 8' in the sorted bus signals into one group; the delay processing unit 12 may also divide the signal bits 1 'and 2' in the arranged bus signal into one group, divide the signal bits 3 'and 4' in the arranged bus signal into one group, divide the signal bits 5 'and 6' in the arranged bus signal into one group, and divide the signal bits 7 'and 8' in the arranged bus signal into one group; and so on. However, the delay processing unit 12 cannot divide any one of the signal bits 1', 2', 3', and 4' of the bus signal after the arrangement into one group with any one of the signal bits 5', 6', 7', and 8'.

In addition, when the initial bus signal includes a non-hopping signal bit, the non-hopping signal bit does not hop regardless of delay, and therefore the delay processing unit 12 can randomly divide the non-hopping signal bit into signal bit groups, which is not limited in this embodiment.

The following description will be given by way of example to the operation of the bus code transmission circuit 10: the initial bus signal is assumed to include adjacent signal bit 1, signal bit 2, signal bit 3, signal bit 4, signal bit 5, signal bit 6, signal bit 7 and signal bit 8, wherein the hopping directions of the signal bit 1, the signal bit 2 and the signal bit 3 are the same, the hopping directions of the signal bit 5, the signal bit 6 and the signal bit 7 are the same, the hopping directions of the signal bit 1 and the signal bit 5 are different, and the signal bit 4 and the signal bit 8 do not hop; correspondingly, arrange in order the initial phase of signal position 1 and obtain signal position 1', arrange in order the initial phase of signal position 2 and obtain signal position 2', arrange in order the initial phase of signal position 3 and obtain signal position 3', arrange in order the initial phase of signal position 4 and obtain signal position 4', arrange in order the initial phase of signal position 5 and obtain signal position 5', arrange in order the initial phase of signal position 6 and obtain signal position 6', arrange in order the initial phase of signal position 7 and obtain signal position 7', arrange in order the initial phase of signal position 8 and obtain signal position 8'. Therefore, the delay processing unit 12 can divide the signal bits 1', 2', 3', and 4' in the sorted bus signals into one group, and divide the signal bits 5', 6', 7', and 8' in the sorted bus signals into one group; the delay processing unit 12 may also divide the signal bits 1', 2', 3', 4', and 8 'in the sorted bus signals into one group, and divide the signal bits 5', 6', and 7' in the sorted bus signals into one group; the delay processing unit 12 may also divide the signal bits 1', 2', and 3 'in the sorted bus signal into one group, and divide the signal bits 4', 5', 6', 7', and 8' in the sorted bus signal into one group; and so on. However, the delay processing unit 12 cannot divide any one of the signal bit 1', the signal bit 2', and the signal bit 3 'in the sorted bus signal into a group with any one of the signal bit 5', the signal bit 6', and the signal bit 7'.

Further, in the grouped bus signals, the hopping direction of each signal bit which hops in any signal bit group is the same, and the hopping direction of any signal bit group is the same as the hopping direction of any signal bit which hops in any signal bit group, so that the delay processing unit 12 may delay all signal bit groups in the same hopping direction in the grouped bus signals according to a preset delay manner. That is, according to the signal bits that jump in the same direction in the initial bus signal, all signal bit groups in the same jump direction in the packet bus signal can be determined, all signal bit groups may include one or more signal bit groups, and then all signal bit groups in the same jump direction are delayed according to a preset delay manner, and the delay time lengths of the signal bits in all signal bit groups in the same jump direction are all not zero, so as to obtain a delayed bus signal, that is, the delayed bus signal includes a delay group and a non-delay group, the delay group may include one or more signal bit groups, the non-delay group may include one or more signal bit groups, and there is no signal bit in the delay group that is the same as the jump direction of the non-delay group, so that each signal bit in the delay group can be delayed according to the preset delay manner, and each signal bit in the non-delay group is normally output, the delay time length corresponding to each signal bit in a certain hopping direction (hopping sent in the initial bus signal) in the grouped bus signals is different from the delay time length corresponding to each signal bit in the opposite hopping direction, so that the signal bits with the reverse hopping simultaneously cannot be transmitted simultaneously, and the signal bits with the reverse hopping simultaneously can be transmitted in a time-sharing manner.

Based on the description in table 1, at the same time, when two signal bits adjacent to any signal bit do not simultaneously generate reverse hopping, that is, the maximum value of hopping crosstalk of each signal bit in the delayed bus signal is reduced from 1+4 λ to 1+2 λ, the worst case crosstalk phenomenon is avoided, no extra routing resource needs to be added, and the worst case crosstalk phenomenon is avoided.

The delay processing unit 12 may be an integrated chip, an integrated circuit with grouping and delay functions built by multiple components, or a processor, which is not limited in this embodiment.

The following description will be given by way of example to the operation of the bus code transmission circuit 10: assuming that the grouped bus signal comprises a first signal bit group, a second signal bit group and a third signal bit group, the first signal bit group comprising signal bit 1', signal bit 2', signal bit 3 'and signal bit 4', the second signal bit group comprising signal bit 5', signal bit 6', signal bit 7 'and signal bit 8', the third signal bit group comprising: signal bit 9', signal bit 10', signal bit 11 'and signal bit 12', and signal bit 1, signal bit 2, signal bit 3, signal bit 4, signal bit 5, signal bit 6, the jump direction that signal bit 7 and signal bit 8 correspond respectively in the initial bus signal all is rising edge jump direction, signal bit 9 in the initial bus signal, the jump direction that signal bit 10 and signal bit 11 correspond respectively all is falling edge jump direction, then delay processing unit 12 delays the signal bit group of rising edge jump direction or falling edge jump direction (the jump that sends in the initial bus signal) in the bus signal after the grouping according to preset delay mode, obtain the bus signal after the delay, delay processing unit 12 promptly can delay each signal bit in first signal bit group and the second signal bit group according to preset delay mode, delay processing unit 12 also can delay each signal bit in the third signal bit group according to preset delay mode.

Further, the delay processing unit 12 may obtain the delayed bus signal based on the above process, and may transmit the delayed bus signal to the bus decoding receiving circuit in a time-sharing manner according to the delay time duration corresponding to each signal bit, so that the worst-case hopping crosstalk influence of each signal bit in the delayed bus signal is reduced without increasing routing resources.

The bus coding transmitting circuit that this embodiment provided, on the one hand, arrange into the same phase place through the initial phase arrangement of each signal bit in the phase place arrangement unit in with initial bus signal, obtain bus signal after the arrangement, be convenient for follow-up carry out corresponding operation to bus information after the arrangement, avoid direct action to initial bus signal and arouse easily because the initial phase difference of each signal bit leads to each signal bit phenomenon that reverse jump takes place simultaneously, lead to follow-up operation to lose original effect. On the other hand, the delay processing unit groups each signal bit in the bus signal after being sorted according to the jumping direction of each signal bit in the initial bus signal, divides each signal bit into at least two signal bit groups, and obtains the grouped bus signal. Because the hopping directions of the signal bits hopped in any signal bit group are the same, and the hopping direction of any signal bit group is the same as the hopping direction of any signal bit hopped in any signal bit group, the delay processing unit selects all signal bit groups in the same hopping direction from the grouped bus signals, and carries out non-zero delay on all the signal bit groups in the same hopping direction according to a preset delay mode to obtain a delayed bus signal, so that the signal bits hopped in the opposite directions can be transmitted in a time-sharing manner, and the delay processing unit can send the delayed bus signal to the bus decoding receiving circuit. In the embodiment, the signal bits which are simultaneously subjected to reverse hopping are transmitted in a time-sharing manner, so that the worst crosstalk is eliminated, the transmission delay influence caused by crosstalk is reduced, additional wiring resources are not required to be added, and the resources and power consumption consumed by corresponding partial circuits are saved.

On the basis of the above-described embodiment of fig. 1, the preset delay manner may include various implementation manners. Optionally, the preset delay mode is a mode in which delay time lengths corresponding to all signal bits in all signal bit groups with the same hopping direction are set to be non-zero; and the delay time lengths corresponding to all signal bits in all signal bit groups with the same hopping direction are set to be the same or different.

Specifically, for any one hopping direction, in one or more signal bit groups of the hopping direction, the delay processing unit 12 may set the delay time lengths corresponding to the signal bits to be different, and ensure that the delay time lengths corresponding to the signal bits are not zero, so that the delay time lengths corresponding to the signal bits of the hopping direction are all changed. Therefore, the time delay corresponding to the signal bit with the opposite hopping direction is not changed, so that the signal bit with the opposite hopping direction can not be transmitted simultaneously, and the signal bit with the opposite hopping direction can be transmitted in a time-sharing manner.

Further, to simplify the operation process of the delay processing unit 12, for any one of the hopping directions, in one or more signal bit groups of the hopping direction, the delay processing unit 12 may set the delay time duration corresponding to each signal bit to be the same, and ensure that the delay time duration corresponding to each signal bit is not zero, so that the delay time durations corresponding to the signal bits of the hopping direction are all changed. Therefore, the time delay duration corresponding to the signal bit with the opposite hopping direction is not changed, so that the signal bit with the reverse hopping simultaneously is transmitted in a time-sharing manner, and the signal bit with the reverse hopping simultaneously is transmitted simultaneously.

Furthermore, no matter which of the above manners, based on the description in table 1, at the same time, when two signal bits adjacent to any signal bit do not generate reverse hopping with the signal bit at the same time, it is indicated that the hopping crosstalk of the signal bit in the delayed bus signal is reduced from 1+4 λ to 1+2 λ, the occurrence of the worst case crosstalk is eliminated, the transmission delay influence caused by the worst case crosstalk is alleviated, no additional wiring resource needs to be added, the occurrence and the direction of each signal bit hopping do not need to be determined, and the resource and the power consumption consumed by the corresponding part of circuits are saved.

On the basis of the above embodiment, a detailed description is given of the specific structure of the delay processing unit 12 in the embodiment of fig. 1 with reference to fig. 2.

Fig. 2 is a schematic structural diagram of a bus code transmitting circuit provided by the present invention, and as shown in fig. 2, on the basis of the bus code transmitting circuit 10 in the embodiment of fig. 1, optionally, the delay processing unit 12 includes: transition discrimination section 121, signal bit grouping section 122, and phase delay section 123.

The signal bit grouping unit 122 is connected to the phase sorting unit 11, the transition discrimination unit 121, and the phase delay unit 123, respectively.

A jump judging unit 121, configured to receive an initial bus signal; and judging whether the hopping direction of each signal bit in the initial bus signal is the target hopping direction or not to obtain a judgment result. And the target hopping direction is a rising edge hopping direction or a falling edge hopping direction.

A signal bit grouping unit 122, configured to receive the bus signal after being sorted and sent by the phase sorting unit 11, and receive the decision result sent by the transition decision unit 121; and according to the judgment result, grouping each signal bit in the bus signal after being sorted to obtain a grouped bus signal.

And the phase delay unit 123 is configured to delay all signal bit groups in the same hopping direction in the grouped bus signals according to a preset delay manner, so as to obtain a delayed bus signal.

The phase delay unit 123 is further configured to send the delayed bus signal to the bus decoding receiving circuit.

Specifically, the jump judging unit 121 may receive the initial bus signal sent by the phase sorting unit 11, and judge whether a jump direction of each signal bit in the initial bus signal is a target jump direction, to obtain a judgment result, where the target jump direction is a rising edge jump direction or a falling edge jump direction, and the judgment result may be marked in the form of an identifier or a code.

The hopping determination unit 121 may be an integrated chip, an integrated circuit with a phase sorting function built by a plurality of components, or a processor, which is not limited in this embodiment. For example, the transition discriminating unit 121 may transition a discriminator.

Further, the transition discrimination unit 121 transmits the discrimination result to the signal bit grouping unit 122. Because the discrimination result carries the specific situation of the hopping direction of each signal bit in the initial bus signal and the one-to-one correspondence relationship between the signal bit in the initial bus signal and the signal bit in the sorted bus signal, the signal bit grouping unit 122 can group each signal bit in the received sorted bus signal according to the discrimination result, can divide the signal bits in different hopping directions into one signal bit group or a plurality of signal bit groups, and obtain the grouped bus signal.

Further, since there may be a signal bit in which no transition occurs in the initial bus signal and a signal bit in a different transition direction, for convenience of description, a specific case in which the signal bit grouping unit 122 groups each signal bit in the sorted bus signal according to the determination result will be described in detail below.

Optionally, the signal bit grouping unit 122 is specifically configured to divide signal bits in the initial bus signal, where a hopping direction of the initial bus signal is the same as a target hopping direction, into a first signal bit group corresponding to signal bits in the organized signal bit group, and divide remaining signal bits in the organized bus signal into a second signal bit group, so as to obtain a grouped bus signal; the second signal bit group comprises signal bits in the initial bus signals, wherein the hopping directions of the signal bits in the initial bus signals are opposite to the target hopping directions and respectively correspond to the signal bits in the bus signals after arrangement, and the signal bits which do not hop in the initial bus signals respectively correspond to the signal bits in the bus signals after arrangement; alternatively, the first and second electrodes may be,

dividing signal bits in the initial bus signal, of which the hopping direction is opposite to the target hopping direction, into a first signal bit group corresponding to signal bits in the organized signal bit group respectively, and dividing residual signal bits in the organized bus signal into a second signal bit group to obtain grouped bus signals; the second signal bit group comprises signal bits in the initial bus signals, wherein the signal bits in the initial bus signals, the hopping direction of which is the same as the target hopping direction, correspond to the signal bits in the bus signals after arrangement respectively, and the signal bits in the initial bus signals, which do not hop, correspond to the signal bits in the bus signals after arrangement respectively; or

Dividing signal bits in the initial bus signal, the hopping direction of which is the same as the target hopping direction, into a first signal bit group corresponding to the signal bits in the organized signal bit group respectively, dividing signal bits in the initial bus signal, the hopping direction of which is opposite to the target hopping direction, into a second signal bit group corresponding to the signal bits in the organized signal bit group respectively, and dividing signal bits in the initial bus signal, which do not hop, into a third signal bit group corresponding to the signal bits in the organized signal bit group respectively.

Specifically, when the bit grouping unit 122 determines the target transition direction as the grouping basis, it may determine the bits with the same transition direction as the target transition direction from the transition directions of the bits in the initial bus signal, and then use the bits corresponding to the sorted bits in the bus signal as one or more signal bit groups, i.e., a first signal bit group, and use the remaining bits in the sorted bus signal as one or more signal bit groups, i.e., a second signal bit group.

When the signal bit grouping unit 122 determines that the hopping direction opposite to the target hopping direction is the grouping basis, signal bits with the hopping direction opposite to the target hopping direction are determined from the hopping directions of the signal bits in the initial bus signal, the signal bits corresponding to the organized bus signals are used as one or more signal bit groups, namely, a first group of signal bits, and the remaining signal bits in the organized bus signals are used as one or more signal bit groups, namely, a second group of signal bits.

When the signal bit grouping unit 122 determines that the target hopping direction and the hopping direction opposite to the target hopping direction are grouping bases, signal bits with the hopping direction opposite to the target hopping direction are determined from the hopping directions of the signal bits in the initial bus signal, and then the signal bits in the bus signal corresponding to the sorted signal bits are used as one or more signal bit groups, namely a first group of signal bits; determining signal bits with the hopping direction opposite to the target hopping direction from the hopping direction of each signal bit in the initial bus signal, and taking the signal bits in the bus signal with the hopping direction corresponding to the sorting as one or more signal bit groups, namely a second group of signal bits; and determining signal bits which do not hop from the hopping direction of each signal bit in the initial bus signal, and taking the signal bits in the bus signal which are corresponding to the arrangement of the signal bits as one or more signal bit groups, namely a third group of signal bits.

Further, the signal bit grouping unit 122 may divide the signal bits in which the target hopping direction occurs and the hopping direction opposite to the target hopping direction occurs into different signal bit groups (i.e., a first signal bit group and a second signal bit group), so that the signal bits in which the reverse hopping occurs are separated, and then the signal bits in which the hopping does not occur are randomly allocated to the first group of signals and/or the second group of signals, thereby implementing a grouping process of the bus signals after being sorted, and avoiding a possibility that the signal bits in the same group of signal bits in which the reverse hopping occurs simultaneously.

The signal bit grouping unit 122 may be an integrated chip, an integrated circuit with a phase sorting function built by a plurality of components, or a processor, which is not limited in this embodiment. For example, the signal bit grouping unit 122 may be a dynamic grouper.

Further, in order to ensure that each signal bit in the grouped signal bus can be stably transmitted, the phase delay unit 123 needs to set a delay time duration corresponding to each signal bit. In this embodiment, the specific size of the delay duration corresponding to each signal bit is not limited.

Optionally, the delay time length corresponding to each signal bit in all signal bit groups in the same hopping direction has an association relationship with the preset time length, and the preset time length is obtained according to the formula (1);

Δ T ═ [ (β - α) × λ ] × T + γ formula (1);

wherein, Δ T is a preset time length, T is a clock period of the initial bus signal, α is a ratio of an interval time length between an initial time and a delay initial time of the clock signal to T, the clock signal is a signal for controlling the grouped bus signal transmission, β is a ratio of an interval time length between the initial time and a delay termination time of the clock signal to T, γ is a correction value, and λ is a delay constant.

Specifically, the initial delay time is the initial time for delaying the grouped bus signals, the termination delay time is the termination time for delaying the grouped bus signals, the setting of α and β stipulates the effective duration of the delayed bus signal transmission, and provides reliable guarantee for stable transmission of the delayed bus signals, the setting of γ can be used for correcting the effective duration of the grouped bus signal transmission again, and provides reliable dual guarantee for stable transmission of the delayed bus signals. In general, α is 10%, β is 80% < β < 95%, γ is 0 ≦ 1, λ is 5% < λ < 90%, and preferably λ is between 40% and 60%.

Further, in the formula (1), the preset time Δ t takes into account both the total number of signal bits in the initial bus signal and the clock cycle of the initial bus signal, that is, the performance of the initial bus signal, and the delay time corresponding to each signal bit in any signal bit group has an association relationship with the preset time, so that in all signal bit groups in the same hopping direction, the delay time corresponding to each signal bit can be equal to the preset time, a positive correlation coefficient can exist between the delay time and the preset time, and the positive correlation coefficient can be any natural number.

Further, based on the grouping of the signal bit grouping unit 122, the phase delay unit 123 may set the delay time lengths corresponding to all signal bit groups in the same hopping direction, respectively, based on the delay time length obtained by the formula (1).

The phase delay unit 123 may be an integrated chip, an integrated circuit with grouping and delay built by components, or a processor, which is not limited in this embodiment.

For example, the phase delay unit 123 may be a phase retarder. In practical application, the phase delayer is composed of a delay time configuration module, a delay pulse generator and a delay latch. After the delay control signal (a group of coded data) and the delay trigger signal (i.e. the signal indicating that any signal bit is triggered to be delayed) enter the delay time configuration module together, firstly the delay control signal is decoded into a signal corresponding to the required delay time (i.e. indicating the specific size of the delay time corresponding to any signal bit), under the control of the signal, the corresponding stage number of the delay inverter chain (belonging to the delay time configuration module) is opened, the delay trigger signal obtains a signal delayed by the delay time through the inverter chain, and the delayed signal and the original delay trigger signal are sent into the delay pulse generator together to obtain a sampling pulse which is sent into the delay latch. The input of the delay latch is connected to the signal bit group corresponding to any transition direction in the grouped signals output by the delay pulse generator and the signal bit grouping unit 122, the signal bit group corresponding to any transition direction in the grouped bus signals is output in a delayed manner under the control of the sampling pulse, and the remaining signal bits in the grouped bus signals are directly output.

In the present invention, the bus code transmitting circuit 10 may be divided into functional blocks according to the above method, for example, each functional block may be divided according to each function, or two or more functions may be integrated into one processing block. The integrated module can be realized in a hardware mode, and can also be realized in a software functional module mode. It should be noted that the division of the modules in the embodiments of the present invention is schematic, and is only a logical function division, and there may be another division manner in actual implementation.

Fig. 3 is a flowchart of a bus code transmitting method provided in the present invention, and as shown in fig. 3, the bus code transmitting method of the present embodiment includes:

s101, arranging the initial phases of all signal bits in the initial bus signal into the same phase to obtain an arranged bus signal.

S102, grouping each signal bit in the bus signal after being sorted according to the hopping direction of each signal bit in the initial bus signal to obtain a grouped bus signal; the grouped bus signals comprise at least two signal bit groups, the jumping direction of each signal bit jumping in any signal bit group is the same, and the jumping direction of any signal bit group is the same as that of any signal bit jumping in any signal bit group.

S103, delaying all signal bit groups in the same jumping direction in the grouped bus signals according to a preset delay mode to obtain delayed bus signals; the preset delay mode is a mode of setting the delay time length corresponding to each signal bit in all signal bit groups in the same jump direction to be nonzero.

And S104, sending the delayed bus signal to a bus decoding receiving circuit.

Specifically, referring to fig. 1, the present embodiment uses a bus code transmitting circuit 10 as an execution main body, wherein the bus code transmitting circuit 10 includes: a phase sorting unit 11 and a delay processing unit 12 connected in sequence. The phase arrangement unit 11 may arrange the initial phases of the signal bits in the initial bus signal into the same phase, and send the arranged bus signal to the delay processing unit 12. The delay processing unit 12 may group each signal bit in the sorted bus signal according to the hopping direction of each signal bit in the initial bus signal, so as to obtain a grouped bus signal; the grouped bus signals comprise at least two signal bit groups, the jumping direction of each signal bit jumping in any signal bit group is the same, and the jumping direction of any signal bit group is the same as that of any signal bit jumping in any signal bit group. The delay processing unit 12 delays all signal bit groups in the same hopping direction in the grouped bus signals according to a preset delay mode to obtain delayed bus signals; the preset delay mode is a mode in which the delay time duration corresponding to each signal bit in all signal bit groups in the same hopping direction is set to be non-zero, and further, the delay processing unit 12 sends the delayed bus signal to the bus decoding receiving circuit.

Optionally, the delay time lengths corresponding to the signal bits in all the signal bit groups in the same hopping direction are set to be the same or different.

The bus code transmission method of this embodiment corresponds to a technical solution that can be used to implement the embodiment of the apparatus shown in fig. 1, and the implementation principle thereof is similar, and is not described herein again.

On the basis of the above embodiment of fig. 3, in combination with fig. 1 and 2, the present embodiment takes a bus code transmitting circuit 10 as an execution subject, where the bus code transmitting circuit 10 includes: a phase sorting unit 11 and a delay processing unit 12 connected in sequence. The delay processing unit 12 includes: transition discrimination section 121, signal bit grouping section 122, and phase delay section 123. The signal bit grouping unit 122 is connected to the phase sorting unit 11, the transition discrimination unit 121, and the phase delay unit 123, respectively.

Before grouping each signal bit in the bus signal after the sorting according to the transition direction of each signal bit in the initial bus signal in the S102 embodiment, the bus code sending method according to this embodiment may further include:

and judging whether the hopping direction of each signal bit in the sorted bus signal is the target hopping direction or not to obtain a judgment result.

In the S102 embodiment, grouping the signal bits in the arranged bus signal according to the hopping direction of each signal bit in the arranged bus signal to obtain a grouped bus signal may include:

and according to the judgment result, grouping each signal bit in the bus signal after being sorted to obtain a grouped bus signal.

Wherein, according to the result of the determination, grouping each signal bit in the bus signal after the arrangement to obtain the grouped bus signal, may include:

optionally, dividing signal bits in the initial bus signal, which have the same hopping direction as the target hopping direction, into a first signal bit group corresponding to signal bits in the sorted signal bit group, and dividing remaining signal bits in the sorted bus signal into a second signal bit group to obtain grouped bus signals; the second signal bit group comprises signal bits in the initial bus signals, wherein the hopping directions of the signal bits in the initial bus signals are opposite to the target hopping directions and respectively correspond to the signal bits in the bus signals after arrangement, and the signal bits which do not hop in the initial bus signals respectively correspond to the signal bits in the bus signals after arrangement; alternatively, the first and second electrodes may be,

Δ T ═ [ (β - α) × λ ] × T + γ formula (1);

The bus code transmission method of this embodiment is applicable to the technical solutions for implementing the embodiments of the apparatuses shown in fig. 1-2, and the implementation principles thereof are similar and will not be described herein again.

Fig. 4 is a schematic structural diagram of a bus transmission system provided in the present invention, and as shown in fig. 4, the bus transmission system 40 of the present embodiment includes: a bus decoding receiving circuit 41 and a bus encoding transmitting circuit 42 as in fig. 1-2.

The bus transmission system provided in this embodiment includes the above bus code transmission circuit, and can execute the above embodiments shown in fig. 1 to fig. 2, and for concrete implementation principles and technical effects, reference may be made to the above embodiment of the bus code transmission method shown in fig. 3, which is not described herein again.

Fig. 5 is a schematic diagram of a hardware structure of the electronic device provided by the present invention. As shown in fig. 5, the electronic device 50 includes: a memory 51 and a processor 52;

a memory 51 for storing a computer program;

a processor 52 for executing the computer program stored in the memory to implement the bus code transmission method in the above embodiments. Reference may be made in particular to the description relating to the method embodiments described above.

Alternatively, the memory 51 may be separate or integrated with the processor 52.

When the memory 51 is a device separate from the processor 52, the electronic device 50 may further include:

a bus 53 for connecting the memory 51 and the processor 52.

The electronic device provided in this embodiment may be used to execute the bus code sending method, and the implementation manner and the technical effect thereof are similar, and this embodiment is not described herein again.

The present invention also provides a computer-readable storage medium including a computer program for implementing the bus code transmission method as in the above embodiments.

In the embodiments provided in the present invention, it should be understood that the disclosed apparatus and method may be implemented in other ways. For example, the above-described embodiments of the apparatus are merely illustrative, and for example, the division of modules is only one logical division, and other divisions may be realized in practice, for example, a plurality of modules may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or modules, and may be in an electrical, mechanical or other form.

Modules described as separate parts may or may not be physically separate, and parts displayed as modules may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of the present embodiment.

In addition, functional modules in the embodiments of the present invention may be integrated into one processing unit, or each module may exist alone physically, or two or more modules are integrated into one unit. The unit formed by the modules can be realized in a hardware form, and can also be realized in a form of hardware and a software functional unit.

The integrated module implemented in the form of a software functional module may be stored in a computer-readable storage medium. The software functional module is stored in a storage medium and includes several instructions to enable a computer device (which may be a personal computer, a server, or a network device) or a processor (processor) to execute some steps of the methods according to the embodiments of the present application.

It should be understood that the Processor may be a Central Processing Unit (CPU), other general purpose Processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), etc. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like. The steps of a method disclosed in connection with the present invention may be embodied directly in a hardware processor, or in a combination of the hardware and software modules within the processor.

The memory may comprise a high-speed RAM memory, and may further comprise a non-volatile storage NVM, such as at least one disk memory, and may also be a usb disk, a removable hard disk, a read-only memory, a magnetic or optical disk, etc.

The bus may be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, an Extended ISA (EISA) bus, or the like. The bus may be divided into an address bus, a data bus, a control bus, etc. For ease of illustration, the buses in the figures of the present application are not limited to only one bus or one type of bus.

The computer-readable storage medium may be implemented by any type or combination of volatile or non-volatile memory devices, such as Static Random Access Memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic or optical disks. A storage media may be any available media that can be accessed by a general purpose or special purpose computer.

Those of ordinary skill in the art will understand that: all or a portion of the steps of implementing the above-described method embodiments may be performed by hardware associated with program instructions. The program may be stored in a computer-readable storage medium. When executed, the program performs steps comprising the method embodiments described above; and the aforementioned storage medium includes: various media that can store program codes, such as ROM, RAM, magnetic or optical disks.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A bus encoded transmit circuit, comprising: the phase sorting unit and the delay processing unit are connected in sequence;

the delay processing unit is further configured to delay all signal bit groups in the same hopping direction in the grouped bus signals according to a preset delay manner, so as to obtain delayed bus signals; and sending the delayed bus signal to a bus decoding receiving circuit; the preset delay mode is a mode that delay time lengths corresponding to all signal bits in all signal bit groups in the same hopping direction are set to be nonzero, wherein the delay time lengths corresponding to all the signal bits in a certain hopping direction in the grouped bus signals are different from the delay time lengths corresponding to all the signal bits in the opposite hopping direction.

2. The circuit of claim 1, wherein the delay time duration corresponding to each bit in all the groups of bits in the same transition direction is set to be the same or different.

3. The circuit according to claim 1 or 2, wherein the delay processing unit comprises: a jump judging unit, a signal bit grouping unit and a phase delay unit;

the signal bit grouping unit is respectively connected with the phase sorting unit, the jump judging unit and the phase delay unit;

4. The circuit according to claim 3, wherein the bit grouping unit is specifically configured to divide bits in the initial bus signal having a same transition direction as the target transition direction into a first bit group corresponding to bits in the sorted bit group, and divide remaining bits in the sorted bus signal into a second bit group to obtain the grouped bus signal; wherein, the second signal bit group comprises signal bits in the initial bus signal, the hopping direction of which is opposite to the target hopping direction, and the signal bits in the bus signal after arrangement and the signal bits in the initial bus signal, which do not hop, correspond to the signal bits in the bus signal after arrangement respectively; alternatively, the first and second electrodes may be,

5. The circuit according to claim 1 or 2, wherein the delay time duration corresponding to each signal bit in all the signal bit groups in the same hopping direction has an association relationship with a preset time duration, and the preset time duration is obtained according to formula (1);

Δ T ═ [ (β - α) × λ ] × T + γ formula (1);

6. A bus code transmission method is characterized by comprising the following steps:

grouping each signal bit in the bus signal after being sorted according to the hopping direction of each signal bit in the initial bus signal to obtain a grouped bus signal; the grouped bus signals comprise at least two signal bit groups, and the hopping direction of any signal bit group is the same as the hopping direction of any signal bit which hops in any signal bit group;

delaying all signal bit groups in the same jumping direction in the grouped bus signals according to a preset delay mode to obtain delayed bus signals; the preset delay mode is a mode that delay time lengths corresponding to all signal bits in all signal bit groups in the same hopping direction are set to be nonzero, wherein the delay time lengths corresponding to all the signal bits in a certain hopping direction in the grouped bus signals are different from the delay time lengths corresponding to all the signal bits in the opposite hopping direction;

and sending the delayed bus signal to a bus decoding receiving circuit.

7. The method according to claim 6, wherein the delay time duration corresponding to each bit in all the groups of bits in the same hopping direction is set to be the same or different.

8. The method according to claim 6 or 7, wherein before the grouping the bits in the consolidated bus signal according to the transition direction of the bits in the initial bus signal to obtain the grouped bus signal, the method further comprises:

9. The method according to claim 8, wherein the grouping the signal bits in the sorted bus signals according to the determination result to obtain the grouped bus signals comprises:

10. The method according to claim 6 or 7, wherein the delay time duration corresponding to each signal bit in all the signal bit groups in the same hopping direction has an association relationship with a preset time duration, and the preset time duration is obtained according to formula (1);

Δ T ═ [ (β - α) × λ ] × T + γ formula (1);

11. A bus transmission system, comprising: a bus decoding receiving circuit and a bus encoding transmitting circuit as claimed in any one of claims 1 to 5.

12. A computer-readable storage medium, on which a computer program is stored, which, when being executed by a processor, implements the bus code transmission method according to any one of claims 6 to 10.

13. An electronic device, comprising:

a processor; and

a memory for storing executable instructions of the processor;

wherein the processor is configured to perform the bus encoded transmission method of any of claims 6-10 via execution of the executable instructions.