CN113111614B

CN113111614B - Method, device, equipment and medium for determining class bus grouping

Info

Publication number: CN113111614B
Application number: CN202110658341.8A
Authority: CN
Inventors: 丁柯; 张崇茜; 张薇
Original assignee: Beijing Core Vision Software Technology Co ltd
Current assignee: Beijing Core Vision Software Technology Co ltd
Priority date: 2021-06-15
Filing date: 2021-06-15
Publication date: 2021-09-28
Anticipated expiration: 2041-06-15
Also published as: CN113111614A

Abstract

The embodiment of the application provides a method, a device, equipment and a medium for determining a generic bus packet. The method comprises the following steps: obtaining circuit diagram data of a target digital circuit, wherein the circuit diagram data comprises: a plurality of unit signals transmitted between the logic devices of the target digital circuit and a plurality of association relations corresponding thereto; grouping the plurality of unit signals according to a preset bus signal grouping rule based on the circuit diagram data to obtain a plurality of groups; and sequencing all unit signals in each group aiming at each group to obtain a bus-like group consisting of all the unit signals. According to the technical scheme provided by the embodiment of the application, the multiple unit signals which are preliminarily divided into the bus signals but have undetermined bit sequences can be accurately divided.

Description

Method, device, equipment and medium for determining class bus grouping

Technical Field

The present application relates to the field of circuit technologies, and in particular, to a method, an apparatus, a device, and a medium for determining a bus-like packet.

Background

With the rapid development of circuit technology, the technology of Electronic Design Automation (EDA) is also emerging. EDA technology can be based on large-scale programmable devices, with calculators as tools, to achieve a hardware description of digital circuits. For example, the digital circuit may be analyzed reversely according to the input chip information, code information, and the like.

In the reverse analysis process of the digital circuit, it is necessary to analyze which unit signals in the circuit belong to the same signal bus and determine the correct bus bit sequence. In the prior art, after a plurality of unit signals belonging to the same bus are divided, the bit sequence of the unit signals needs to be determined, and then the bus signal composed of the unit signals can be determined.

However, if the bit sequence of the unit signals cannot be determined, the signal units cannot be divided correctly.

Disclosure of Invention

The embodiment of the application provides a method, a device, equipment and a medium for determining a category bus group, which can accurately divide a plurality of unit signals which are preliminarily divided into a bus signal but cannot determine a bit sequence.

In a first aspect, an embodiment of the present application provides a method for determining a generic bus packet, including:

obtaining circuit diagram data of a target digital circuit, wherein the circuit diagram data comprises: a plurality of unit signals transmitted between the logic devices of the target digital circuit and a plurality of corresponding relations corresponding to the unit signals;

grouping the plurality of unit signals according to a preset bus signal grouping rule based on the circuit diagram data to obtain a plurality of groups;

and sequencing all unit signals in each group aiming at each group to obtain a bus-like group consisting of all the unit signals.

In a second aspect, an embodiment of the present application provides an apparatus for determining a generic bus packet, where the apparatus includes:

a data acquisition module, configured to acquire circuit diagram data of a target digital circuit, where the circuit diagram data includes: a plurality of unit signals transmitted between the logic devices of the target digital circuit and a plurality of corresponding relations corresponding to the unit signals;

the grouping module is used for grouping the unit signals according to a preset bus signal grouping rule based on circuit diagram data to obtain a plurality of groups;

and the sequencing module is used for sequencing all the unit signals in each group aiming at each group to obtain a bus-like group consisting of all the unit signals.

In a third aspect, there is provided a device for determining a generic bus packet, comprising:

a processor and a memory storing computer program instructions;

the processor reads and executes the computer program instructions to implement the method for determining class bus packets provided by the first aspect or any of the alternative embodiments of the first aspect.

In a fourth aspect, a computer storage medium is provided, on which computer program instructions are stored, which when executed by a processor implement the method for determining a bus-like packet provided in the first aspect or any optional implementation manner of the first aspect.

According to the method, the device, the equipment and the medium for determining the similar bus group, after the unit signals belonging to one bus signal in the plurality of unit signals of the circuit diagram data are preliminarily divided into one group according to the preset bus signal group rule, under the condition that the bit sequence of the unit signals in each group is not obtained, the unit signals in the group can be divided into one similar bus group by sequencing. The unit signals in each class of bus group are orderly arranged and belong to one bus signal, so that the characteristics of correlation and orderliness among the unit signals of the bus signals are reflected, and the unit signals without the bit sequences can be accurately divided.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed to be used in the embodiments of the present application will be briefly described below, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

FIG. 1 is a schematic diagram of first exemplary circuit diagram data provided by an embodiment of the present application;

FIG. 2 is a logic diagram of a determination scheme of a generic bus packet according to an embodiment of the present application;

fig. 3 is a schematic flowchart of a method for determining a first kind of bus packet according to an embodiment of the present application;

fig. 4 is a schematic flowchart of a method for determining a second kind of bus packet according to an embodiment of the present application;

fig. 5 is a schematic flowchart of a third method for determining a bus packet of the present application according to an embodiment of the present application;

FIG. 6 is a second exemplary circuit diagram data diagram provided by an embodiment of the present application;

fig. 7 is a flowchart illustrating a fourth method for determining a bus packet of the class according to an embodiment of the present application

FIG. 8 is a block diagram illustrating exemplary logical functional blocks provided in an embodiment of the present application;

FIG. 9 is a schematic diagram of a third circuit diagram data provided by an embodiment of the present application;

FIG. 10 is a diagram illustrating fourth exemplary circuit diagram data provided by an embodiment of the present application;

fig. 11A is a schematic diagram of an exemplary creating class bus packet provided in an embodiment of the present application;

fig. 11B is a schematic diagram of another exemplary creation class bus packet provided in the embodiment of the present application;

fig. 12 is a schematic flowchart of a method for determining a fifth kind of bus packet according to an embodiment of the present application;

fig. 13 is a schematic flowchart of a method for determining a sixth kind of bus packet according to an embodiment of the present application;

FIG. 14 is a schematic diagram of fifth exemplary circuit diagram data provided by an embodiment of the present application;

FIG. 15 is a schematic diagram of a sixth exemplary circuit diagram data provided by an embodiment of the present application;

FIG. 16 is a diagram illustrating seventh exemplary circuit diagram data provided by an embodiment of the present application;

FIG. 17 is a diagram of eighth exemplary circuit diagram data provided by an embodiment of the present application

FIG. 18 is a schematic diagram of ninth exemplary circuit diagram data provided by an embodiment of the present application;

FIG. 19 is a diagram illustrating tenth exemplary circuit diagram data provided by an embodiment of the present application;

FIG. 20 is a schematic diagram of eleventh exemplary circuit diagram data provided by an embodiment of the present application;

fig. 21 is a schematic flowchart of a method for determining a seventh type of bus packet according to an embodiment of the present application;

FIG. 22 is a diagram of a twelfth exemplary circuit diagram data provided by an embodiment of the present application;

FIG. 23 is a schematic diagram of a thirteenth exemplary circuit diagram data provided by an embodiment of the present application;

FIG. 24 is a diagram illustrating a fourteenth exemplary circuit diagram data provided by an embodiment of the present application;

fig. 25 is a schematic structural diagram of an apparatus for determining generic bus packets according to an embodiment of the present application;

fig. 26 is a schematic diagram illustrating a hardware structure of a device for determining a class bus packet according to an embodiment of the present invention.

Detailed Description

Features and exemplary embodiments of various aspects of the present application will be described in detail below, and in order to make objects, technical solutions and advantages of the present application more apparent, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are intended to be illustrative only and are not intended to be limiting. It will be apparent to one skilled in the art that the present application may be practiced without some of these specific details. The following description of the embodiments is merely intended to provide a better understanding of the present application by illustrating examples thereof.

It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.

Electronic Design Automation (EDA) is a design method for completing processes of functional design, Integration, verification, physical design (including layout, wiring, layout, design rule check, etc.) of a Very Large Scale Integration (VLSI) chip by using Computer Aided Design (CAD) software.

Because of the large number of buses in the digital circuit, analyzing and clearing the bus signals helps to better clear the construction of the digital circuit. Therefore, when performing inverse digital circuit analysis using EDA software, it is necessary to sort scattered unit signals into bus signals and determine the bit sequence of each unit signal in the bus signals.

In a related art, in an initial analysis of a circuit, the number of unit signals in a bus can be determined, but the bit order of the unit signals in the bus signal cannot be determined. It is necessary to use these logic structures to determine the bit sequence of each unit signal in the bus signal when it is sorted into the logic structures such as counters, accumulators, etc. However, if the exact bit sequence of these unit signals cannot be determined, such signals cannot be correctly grouped. For example, when the logical structure features such as counters, accumulators, etc. are not obvious, the bus can only be named first. However, it is difficult to determine the correct bus bit sequence simultaneously, and when the bus signal bit sequence is found to be incorrect, it takes a lot of time to revise the bit sequence of each bus signal, so that the efficiency of determining the bus is low due to the incorrect classification. Alternatively, when the bit sequences of the unit signals cannot be determined, the signals are regarded as independent unit signals, but the unit signals often have high correlation, and when the unit signals are regarded as unit signals, the correlation of the signals cannot be accurately reflected.

Therefore, a technical solution capable of classifying the unit signals whose order cannot be determined is required.

Based on this, the embodiments of the present application provide a method, an apparatus, a device, and a medium for determining a bus-like packet, which may be applied to an application scenario for managing bus signals. The method can be particularly applied to a specific application scene of arranging the bus signals by using EDA software. Compared with the related art, the scheme provided by the embodiment of the application can preliminarily divide the unit signal belonging to one bus signal in the plurality of unit signals of the circuit diagram data into one group according to the preset bus signal grouping rule. And in the case that the bit sequence of the unit signals in each packet is not obtained, the unit signals in the packet can be divided into one bus-like packet by sorting the unit signals. The unit signals in each class of bus group are orderly arranged and belong to one bus signal, so that the characteristics of correlation and orderliness among the unit signals of the bus signals are reflected, and the unit signals without the bit sequences can be accurately divided. In one embodiment, the ordering of the unit signals in the bus-like packet may be randomly ordered first, and when the preset logic function unit is encountered, the ordering may be adjusted according to the input signal or the output signal of the preset logic function module. It should be noted that, in addition to the random ordering mode, the unit signals in the bus-like packet may be ordered according to a preset rule, and the specific ordering mode is not specifically limited in this embodiment of the application.

For better understanding of the present application, the embodiments of the present application specifically explain concepts of circuit diagram data, unit signals, bus-like packets, and the like in turn.

(1) The circuit diagram data is used for representing basic logic gates (combinational logic gates such as AND, OR, NOT, sequential logic gates such as flip-flops and the like) of the digital circuit and the connection and formation relationship between the basic logic gates and the sequential logic gates, and the basic logic gates and the connection and formation relationship between the basic logic gates and the sequential logic gates can reflect the logic structure of circuits in a chip through a circuit structure or a variable-expression structure and the like.

Illustratively, fig. 1 is a schematic diagram of exemplary circuit diagram data provided by an embodiment of the present application. As shown in fig. 1, the circuit diagram data includes a plurality of independent logic devices of a digital circuit or a simple structure composed of a plurality of logic devices. Such as an and gate, a not gate, an or gate, etc.

The circuit diagram data may further include: a plurality of unit signals (not shown in fig. 1) transmitted between logic devices of a target digital circuit. For example, the unit signal may be an input signal, an output signal, a clock signal, or the like of each logic device.

In addition, the circuit diagram data may further include a plurality of association relations corresponding to the plurality of unit signals, wherein each association relation is an association relation between at least two unit signals. Specifically, if a unit signal is affected by the state values of N unit signals, the unit signal and the N unit signals have a correlation, where N is a positive integer. In one example, the correlation may be reflected by the circuit structure, for example, if the circuit diagram data includes a not gate, there is a correlation between an input signal and an output signal of the not gate. In another example, the association relationship between the unit signals may be expressed according to a "variable-expression" structure.

(2) A unit signal, i.e. a signal which is transmitted between logic devices in the circuit diagram data, i.e. data which occupies one bit during transmission. Illustratively, the unit signal may be an input signal, an output signal, a control signal, or the like of the logic device. The control signal may include a clock signal, etc.

(3) Bus signals (Bus), a common communication line that transfers information between various functional units, may provide data transfer and logic control for each logic device/functional unit in a common manner, transferring multiple bits of data. In particular, the data on the bus signal may be transferred in multi-bit bits, that is, the bus signal is a multi-bit signal. Different bits of the bus signal represent different unit signals, and accordingly, the bus signal can be regarded as a plurality of unit signals arranged in a certain bit sequence. Illustratively, for the bus signal counter4B <1:0>, if its bit width is 2, its 0 th bit represents one unit signal counter4B <0 >. The 1 st bit represents a unit signal counter4B <1 >.

(4) Buslike-like packets (Buslike), a packet representation of a unit signal. After determining that the plurality of unit signals belonging to the bus signal are grouped into one group, they may be sorted, and then the sorted plurality of unit signals may be grouped as one bus-like group.

It should be noted that the bus-like group in the embodiment of the present application mainly indicates a grouping method, that is, a grouping method in which a plurality of unit signals belonging to the same bus signal are grouped into one group and the unit signals in the group are sorted. That is, the bus-like packets define a loose collection of signals, and the signals in the packets can be considered as a whole while retaining their unique characteristics. In some embodiments, the unit signals in the bus-like packet may be sorted first according to a preset rule, a random form, and the like, and when a preset logic function unit is encountered, the sorting may be adjusted according to an input signal or an output signal of the preset logic function module.

After the above concepts are introduced, before the method for determining the class bus packet provided in the embodiment of the present application is specifically described, for convenience of understanding, the following portions of the embodiment of the present application will be specifically described with reference to the inventive concept of the determination scheme of the class bus packet shown in fig. 2.

Fig. 2 is a logic diagram of a determination scheme of a class bus packet according to an embodiment of the present application. As shown in fig. 2, the left solid-line box in fig. 2 represents circuit diagram data including a plurality of independent unit signals 11.

In the embodiment of the present application, the circuit diagram data may be obtained first. After grouping a plurality of unit signals 11 in the circuit diagram data, and determining the order of the unit signals in each group, a plurality of class bus groups 12 are obtained, wherein one dashed box in fig. 2 corresponds to one class bus group 12, and one class bus group 12 may be composed of 1 or more unit signals 11.

Furthermore, in some embodiments, with continued reference to fig. 2, after determining the bit order of the unit signals in each class bus packet 12, the class bus packet 12 may be converted into a bus signal 13. The bus signal is a multi-bit signal, and the bit width of the bus signal is the same as the number of the single signals in the bus signal.

After the inventive concepts of the determination scheme of the generic bus packet are introduced, for better understanding of the present application, the following detailed description will be made of a determination method, an apparatus, a device and a medium of the generic bus packet according to embodiments of the present application, with reference to the accompanying drawings, and it should be noted that these embodiments are not intended to limit the scope of the present disclosure.

Fig. 3 is a flowchart illustrating a method for determining a first kind of bus packet according to an embodiment of the present application. As shown in fig. 3, the determination method of the class bus packet includes S310 to S330.

S310, circuit diagram data of the target digital circuit is acquired.

In S310, the specific content of the circuit diagram data may refer to the related description of the above-mentioned portion of the embodiment of the present application, and is not described herein again.

In S310, the target digital circuit may be represented as a digital circuit that needs to be analyzed using EDA technology. In one example, the relevant data of the target digital circuit can be used as input to an EDA tool, and then the logic circuit structure of the target digital circuit can be analyzed using EDA techniques.

In S310, the circuit diagram data includes: a plurality of unit signals transmitted between the logic devices of the target digital circuit, and a correlation corresponding to the plurality of unit signals. Specifically, the specific contents of the circuit diagram data can be referred to the above-mentioned part of the embodiments of the present application in conjunction with the related description of fig. 1, and are not repeated here.

And S320, grouping the plurality of unit signals according to a preset bus signal grouping rule based on the circuit diagram data to obtain a plurality of groups.

In S320, a bus signal grouping rule is preset for grouping unit signals belonging to the same bus signal, wherein one group may include one or more unit signals. Since the coupling degree between a plurality of unit signals belonging to the same bus signal is often high, the preset bus signal grouping rule can be used for grouping signals with high correlation degrees in a plurality of signal units.

In one embodiment, the preset bus signal grouping rule may include: and dividing the unit signals of which the correlation parameters meet the preset correlation condition into a group. For convenience of explanation, the unit signals divided into one group by this rule are referred to as a first packet in the subsequent section of the embodiments of the present application.

In another embodiment, the preset bus signal grouping rule may include: and dividing the related unit signals of the unit signals of one group into one group, wherein the related unit signals and the unit signals of each first group have a correlation relationship. For convenience of explanation, the unit signals divided into one group by this rule are referred to as a second packet in the subsequent section of the embodiments of the present application.

In one embodiment, the specific grouping manner in S320 may include: first, a first packet is determined according to the correlation parameter.

Specifically, the specific grouping manner is explained below in conjunction with fig. 4.

Fig. 4 is a flowchart illustrating a method for determining a second kind of bus packet according to an embodiment of the present application. Fig. 4 differs from fig. 3 in that S320 specifically includes S321 and S32.

S321 determines a correlation parameter for each of the plurality of unit signals based on the circuit diagram data.

In one example, the correlation parameter of at least part of the unit signals can be obtained by sorting the circuit diagram data. The following describes a specific manner of how to obtain the correlation parameter with reference to fig. 5.

Fig. 5 is a flowchart illustrating a method for determining a third type of bus packet according to an embodiment of the present application. Specifically, fig. 5 differs from fig. 4 in that S321 specifically includes S3211 and S3212.

And S3211, processing the circuit diagram data to obtain target data.

In S3211, the circuit diagram data may be sorted by computer algorithm mining or manual intervention. For example, the circuit diagram data may be automatically mined according to the topological or logical characteristics of the circuit, or may be combed and sorted in a manually specified manner.

In one embodiment, fig. 6 is an exemplary circuit diagram data diagram provided by an embodiment of the present application. Accordingly, the target data is obtained by reading and analyzing the circuit diagram data shown in fig. 6 using a computer automated algorithm, which is shown in table 1 below. Wherein the target data may be displayed in a list. It should be noted that the target data may also be displayed in other forms according to specific scenarios and actual requirements, and the specific form of the target data is not limited in the embodiments of the present application.

TABLE 1

Wherein the symbol "&" represents an and operation, the symbol "|" represents an or operation, and the symbol "|" represents an xor operation.

As can be seen from table 1, each line of the target data is used for recording the relevant content of one unit signal. For example, the target data may record one or more of a Name (Name), a Width (Width), a type (reg), a tag (Flags), a Group (Group), an association (Expression), a Clock signal (Clock), and a Reset signal (Reset) of the unit data. Before the signals are not grouped, the original name of each unit signal is recorded in the name column of the target data.

Here, the original name may be a name of a unit signal in the circuit diagram data of S310.

S3212, the correlation parameter of each of the plurality of unit signals is found in the target data.

Continuing with table 1, the value in the column of the Group (Group) is the correlation parameter of each unit signal. Illustratively, taking the unit signal X1825_ Q in table 1 as an example, the correlation parameter thereof may be represented as Cr135: 4.

S322, in the plurality of unit signals, the unit signals whose correlation parameters satisfy the preset correlation condition are grouped into a group, so as to obtain at least one first group.

In one embodiment, the preset correlation condition may be that the correlation parameters are equal or that the difference between the correlation parameters is within a certain value range. Illustratively, continuing with table 1 as an example, the correlation parameter of the four unit signals X3160_ Q, X3324_ Q, X1241_ Q and X1825_ Q is Cr135:4, and the four unit signals X3160_ Q, X3324_ Q, X1241_ Q and X1825_ Q may be regarded as a packet, such as may be named a tmp packet.

In addition to the correlation parameter satisfying the correlation condition for the 4 unit signals, there are other parameters satisfying the correlation condition, for example, if the correlation parameter of X2116_ Q and other unit signals is cr141:3, the unit signals having the correlation parameter of cr141:3 can be divided into 1 group.

In addition, as can be seen from table 1, the Group (Group) column of the partial signals, such as the unit signals X34588_ ZN in table 1, has no correlation parameter, and the Group (Group) column thereof is empty, and the partial signals cannot be grouped by S322, and at this time, the grouping of the unit signals other than the first Group may be continued by using S323.

In another embodiment, after the first packet is determined according to the correlation parameter, the second packet may be derived and constructed based on the association relationship between the unit signal in the first packet and other unit signals. For example, the second packet may be derived and sorted out step by step from the first packet toward the driving direction or the load direction.

Accordingly, the plurality of packets in S320 includes at least one first packet and at least one second packet. At this time, fig. 7 is a schematic flowchart of a fourth method for determining a bus packet of the class according to the embodiment of the present application. Fig. 7 is different from fig. 4 in that S323 may be further included after S322.

S323, among the plurality of unit signals, the unit signals associated with the first packet are grouped into one group to obtain at least one second packet.

In S323, the related unit signal is first specifically described below.

The associated unit signal and the unit signal of the first packet have an association relationship.

In some embodiments, the associated unit signal may be determined according to the circuit structure shown in the circuit diagram data and each unit signal, for example, there is an association relationship between the input signal, the output signal, and the clock signal of the logic device or the logic function module, and accordingly, there is an associated unit signal between the input signal, the output signal, and the clock signal of the logic device or the logic function module. Alternatively, it is determined that a certain unit signal X is affected by one or more unit signals, and that one or more unit signals X are associated with one or more unit signals X, when the certain unit signal X is associated with one or more unit signals, based on the circuit configuration shown in the circuit diagram data and the unit signals at the respective connection terminals of the logic device.

Illustratively, fig. 8 is a schematic structural diagram of an exemplary logic function module provided in an embodiment of the present application. The logic function block shown in fig. 8 consists of one nand gate and one nor gate. As shown in fig. 8, four unit signals of X3160_ Q, X3324_ Q, X1241_ Q and X1825_ Q are input to a nand gate, the unit signal output by the nand gate is denoted as X265841_ ZN, X265841_ ZN and X42149_ ZN are input to a nor gate, and the signal output by the nor gate is denoted as X44480_ ZN. Since the value of X44480_ ZN is affected by the four unit signals X3160_ Q, X3324_ Q, X1241_ Q and X1825_ Q, X44480_ ZN can be regarded as the associated unit signal of the four unit signals X3160_ Q, X3324_ Q, X1241_ Q and X1825_ Q, or can be said to be the associated unit signal of a tmp packet.

In other embodiments, whether the signals are related unit signals or not can be determined according to the relationship of the variable-expression structure shown by the circuit diagram data. Specifically, the unit signals of the variable part of a certain correlation and the unit signals of the expression part of the correlation are correlated unit signals. Or at least two unit signals of the expression part of a certain association relation are associated with each other.

Exemplarily, the association relationship of the logic function modules shown in fig. 8 is shown in table 2.

TABLE 2

It should be noted that, in the embodiment of the present application, the association relationship in the form of the association relationship such as in table 2, that is, the association relationship in the form of the "variable-expression" may be obtained by converting circuit diagram data.

Continuing with Table 2, the unit signals X3324_ Q, X1241_ Q, X1825_ Q, X3160_ Q, X42149_ ZN in the association relationship of the variable X44480_ ZN are all associated with X44480_ ZN.

Next, after introducing the concept of the related unit signal, the following section of the embodiment of the present application will specifically describe the specific implementation of S323.

In some embodiments, if the clock signal is not considered, for N target units, such as N logic devices or N logic function modules, if the N target units include multiple inputs, if the input signal of each target unit has a unit signal belonging to the first group, then the output signals of the N target units are determined to be a second group.

In one example, fig. 9 is a schematic diagram of exemplary circuit diagram data provided by an embodiment of the present application. As shown in fig. 9, if each of the 4 logic units 41 to 44 has two inputs, one input signal of the 4 logic units, for example, four unit signals X3160_ Q, X1825_ Q, X1241_ Q and X3324_ Q, is a first packet, for example, denoted as a tmp packet. And the other input signals of the 4 logic units are the same and are all X3034_ Q, the output signals X5557_ Z, X5561_ Z, X5526_ Z and X5518_ Z of the 4 logic units can be regarded as a second packet, for example, the second packet can be represented as tmp _ zn.

In addition, the correlation between 4 unit signals of X5557_ Z, X5526_ Z, X5561_ Z and X5518_ Z can be shown in table 3 below.

TABLE 3

In other embodiments, if a particular input of a logic device is associated with all or a portion of the signals of the first group, the output signals of the logic device may be divided into a first second group.

FIG. 10 is a schematic diagram of another exemplary circuit diagram data provided by an embodiment of the present application. As shown in fig. 10, eight unit signals, namely X2188_ Q, X2945_ Q, X3192_ Q, X3398_ Q, X1347_ Q, X1445_ Q, X1486_ Q and X1581_ Q, are output signals of the output terminals Q of the 8 flip-flops respectively. Since the subset of three unit signals of tmp group, i.e. the three unit signals X1241_ Q, X3160_ Q and X1825, affects the eight unit signals X2188_ Q, etc. as the selection signal, the output signals of the eight flip-flops X2188_ Q, etc. may be divided into a second group, for example, the second group in which the output signals of the eight flip-flops X2188_ Q, etc. are located is named as rega. It should be noted that the naming of the second packet is used to distinguish different packets, and the naming of the second packet may be set according to specific scenarios and actual requirements, which is not limited herein.

It should be noted that the association relationship between the eight unit signals X2188_ Q, X2945_ Q, X3192_ Q, X3398_ 3598 _ Q, X1347_ Q, X1445_ Q, X1486_ Q and X1581_ Q can be shown in table 4 below.

TABLE 4

In addition, eight signals of X3139_ Q, X2838_ Q, X2295_ Q, X2835_ Q, X2499_ Q, X3304_ Q, X1125_ Q and X2111_ Q in fig. 10 may also be taken as one second packet. Illustratively, the naming of this second packet may be regb.

It should be noted that, in addition to the grouping method using the correlation parameter or the association relationship shown in S320, the specific grouping method may be another grouping method capable of determining that a plurality of unit signals belong to the same bus signal, and this is not particularly limited in the embodiment of the present application.

S330, for each group, all the unit signals in each group are sorted to obtain a bus-like group composed of all the unit signals in each group.

In S330, the unit signals may be sorted according to specific scenarios and actual requirements, in one example, the sorting for each group may be a random sorting, and the random sorting result may represent a temporary order of each unit signal within the bus-like group. In another example, the sorting may be performed according to a preset sorting rule. The embodiment of the present application does not limit the specific sorting manner.

First, for sorting, in some embodiments, if the sorted packets and the signals in the unsorted packets respectively correspond to each other one by one, the sorting result of the unit signals in the unsorted packets may be consistent with the sorting result of the sorted packets for the unit signals corresponding to the sorted packets. Illustratively, taking the rega packet and the regb packet shown in connection with fig. 10 as an example, X1581_ Q in the rega packet corresponds to X2111_ Q in the regb packet, and if X1581_ Q is first in the rega packet, X2111_ Q is correspondingly first in the regb packet. Alternatively, the result of sorting the unit signals in the unsorted packet may not match the result of sorting the unit signals corresponding to the unsorted packet, and the embodiment of the present application does not limit this result.

Next, a specific display mode of the unit signal in the bus-like packet is described below. In one example, if four unit signals of X3160_ Q, X3324_ Q, X1241_ Q and X1825_ Q may be grouped by 1, the four unit signals may be displayed in the manner shown in table 5.

TABLE 5

Accordingly, if the packet is named a tmp packet and the signals are sorted, the sequence number may be as shown in table 6 below.

TABLE 6

Referring to table 6, two new pieces of information may be added to each unit signal, one is the group name of the group to which it belongs, and one is the sorting result of the unit signal.

It should be noted that the sorting of each signal may be arbitrarily set, and accordingly, the sequence numbers of the above 4 signals may be other schemes than the sorting result shown in table 6, and the embodiment of the present application does not specifically limit the sorting result.

Second, the specific way to generate class bus packets.

In some embodiments, the bus-like packet may be created by modifying the original name of the unit signal within a packet. Illustratively, fig. 11A is a schematic diagram of an exemplary creating class bus packet provided in an embodiment of the present application. As shown in fig. 11A, the original name of the unit signal of the tmp packet in the association relationship in the circuit diagram form may be modified into a uniform format, such as an attribute name composed of a packet identifier and a sequence number of each unit signal. For example, X3324_ Q is modified to tmp $ 0. The specific content of the attribute name will be described in detail in the following section of the present application in conjunction with S340. For another example, with continued reference to fig. 11A, the original name of the unit signal of the tmp _ zn packet may be uniformly modified to an attribute name. For example, X5518_ Z is modified to tmp _ zn $ 0. For another example, the original name of the unit signal of the tmp packet in the "variable-expression" structure shown in tables 2 to 4 may be modified into a uniform format to create a bus-like packet.

In other embodiments, the bus-like packet may be created by adding the attribute names of the unit signals, while preserving the original names of the unit signals within the packet. For example, an attribute name may be added near the original name of each unit signal. Illustratively, fig. 11B is a schematic diagram of another exemplary creation class bus packet provided in this embodiment of the application. As shown in FIG. 11B, an attribute name of the unit signal, such as tmp _ zn $0, may be added adjacent to X5518_ Z. As another example, an attribute name, tmp $3, may be added adjacent to X3160_ Q.

It should be noted that, in some embodiments, in addition to the attribute names and the port names of the logical devices, the attribute names, the original names, and the port names of the logical devices may be displayed. For example, the port names of the two inputs of the logic devices 41 to 44 may be "A1N" and "a 2", and the port names of the outputs of the logic devices 41 to 44 may be "ZN". With reference to fig. 11B, taking the logic device 41 as an example, the port name of the input terminal corresponding to X3160_ Q may be "A1N", the port name of the input terminal corresponding to X3034_ Q may be "a 2", and the port name of the output terminal corresponding to X5557_ Z may be "ZN".

It should also be noted that the port name of each logic device may also be in other forms, which is not described in this embodiment.

In some embodiments, this may be accomplished by adding a Group (Group) parameter to the target data shown in Table 1. The specific structure of the group parameter of each unit signal may be represented by "packet name $ serial number of the unit signal".

TABLE 7

It should be noted that, in the embodiment of the present application, the group parameter may also be implemented in other forms capable of grouping names and serial numbers of unit signals, and this is not particularly limited.

In the method for determining a bus-like group according to the embodiment of the present application, after a unit signal belonging to a bus signal in a plurality of unit signals of circuit diagram data is preliminarily divided into a group by using a preset bus signal grouping rule, the unit signals in the group can be divided into a bus-like group by sorting the unit signals in the group without obtaining a bit sequence of the unit signal in each group. The unit signals in each class of bus group are arranged and belong to one bus signal, so that the correlation among the unit signals of the bus signals is reflected, and the unit signals without the bit sequences can be accurately divided.

In addition, the number of unit signals in circuit diagram data can be reduced by a determination method of the bus-like grouping, and the functional analysis of the circuit can be assisted. In some embodiments of the present application, even when the bit sequence of a group of cell signals is not determined, the group of cell signals may be created as a bus-like signal, so that a related person can know that the group of cell signals belongs to a group of bus signals according to the name of the bus-like signal. In the subsequent process, after the correct bit sequence of the class bus signal of a certain group is determined, the bit sequence of the related class bus signal can be automatically propagated according to the bit sequence of the class bus signal, and the class bus signal with the determined bit sequence can be converted into the bus signal.

In some embodiments, after the class bus packet is determined, the present application may also name the unit signals within the class bus packet. Specifically, the following section of the embodiment of the present application will specifically explain the content of naming the unit signal in the bus-like packet by using fig. 12.

Fig. 12 is a flowchart illustrating a method for determining a fifth kind of bus packet according to an embodiment of the present application. Fig. 12 is different from fig. 3 in that after S330, S340 may be further included.

S340, naming each unit signal according to a preset signal naming rule aiming at each class bus group to obtain an attribute name of each unit signal.

In S340, the preset signal naming rule is: the name of each unit signal includes a packet identification and a sequence number of each unit signal.

In one example, taking X3160_ Q, X3324_ Q, X1241_ Q and X1825_ Q in the tmp packet shown in table 6 as an example, if four unit signals are X3324_ Q, X1241_ Q, X1825_ Q and X3160_ Q in sequence from low to high, and the sequence numbers of the four unit signals are 0, 1, 2, and 3, the attribute name of X3324_ Q may be represented as "tmp $ 0", the attribute name of X1241_ Q may be represented as "tmp $ 1", the attribute name of X1825_ Q may be represented as "tmp $ 2", and the attribute name of X3160_ Q may be represented as "tmp $ 3".

It should be noted that the serial numbers of the unit signals are not limited to the specific manner of starting with 0 and being arranged from small to large, and the serial numbers of the unit signals may be set according to the actual scene and the actual requirements, which is not described in detail herein. In another example, taking the tmp _ zn packet shown in conjunction with fig. 11A and 11B as an example, if the unit signals in the packet are sequentially X5518_ Z, X5526_ Z, X5561_ Z, X5557_ Z in descending order and the sequence numbers of the four unit signals are sequentially 0, 1, 2, and 3, the attribute name of X5518_ Z may be represented as "tmp _ zn $ 0", the attribute name of X5526_ Z may be represented as "tmp _ zn $ 1", the attribute name of X5561_ Z may be represented as "tmp _ zn $ 2", and the attribute name of X5557_ Z may be represented as "tmp _ zn $ 3".

In yet another example, taking the rega packet shown in connection with fig. 10 as an example, if the unit signals within the packet are X1581_ Q, X1486_ Q, X1445_ Q, X1347_ Q, X3398_ Q, X3192_ Q, X2945_ Q and X2188_ Q in descending order and the serial numbers of the eight unit signals are 0 to 7 in descending order, the attribute name of X1581_ Q may be represented as "rega $ 0", the attribute name of X1486_ Q may be represented as "rega $ 1", the attribute name of X1445_ Q may be represented as "rega 2", the attribute name of X1347_ Q may be represented as "rega $ 3", the attribute name of X3398_ Q may be represented as "rega $ 4", the attribute name of X3192_ Q may be represented as "rega $ 5", the attribute name of X2945_ Q may be represented as "rega $ 6", and the attribute name of X3192_ Q may be represented as "2187".

In yet another example, taking the regb packet shown in fig. 10 as an example, if the unit signals within the packet are X2111_ Q, X1125_ Q, X3304_ Q, X2499_ Q, X2835_ Q, X2295_ Q, X2838_ Q and X3139_ Q in order from low to high in rank, and the sequence numbers of the eight unit signals are 0 to 7 in order, the attribute name of X2111_ Q may be represented as "regb $ 0", the attribute name of X1125_ Q may be represented as "regb $ 1", the attribute name of X3304_ Q may be represented as "regb $ 2", the attribute name of X2499_ Q may be represented as "regb $ 3", the attribute name of X2835_ Q may be represented as "regb $ 4", the attribute name of X2295_ Q may be represented as "regb $ 5", the attribute name of X2838_ Q may be represented as "regb $ 6", and the attribute name of X2295_ Q may be represented as "regb $ 3137".

According to the embodiment of the application, each unit signal is represented by the attribute name, the grouping relation among the unit signals can be directly embodied from the name of the signal, and the signal in the target digital circuit can be identified more intuitively and simply. The representation of at least part of the data in the circuit diagram data is simplified compared to the prior art.

In some embodiments, since the circuit diagram data further includes a plurality of association relations, after the attribute name of the unit signal is obtained, the association relations in the circuit diagram data may be further expressed based on the attribute name. The following section of the embodiments of the present application will specifically describe the expression of the association relationship with reference to fig. 13 to 20.

Fig. 13 is a flowchart illustrating a method for determining a sixth kind of bus packet according to an embodiment of the present application. Fig. 13 differs from fig. 12 in that S350 may be further included after S340.

S350, for each class bus packet, an association relation with respect to each unit signal of each class bus packet is determined among the plurality of associations of the circuit diagram data.

First, regarding the association relationship, the association relationship is used to express the association relationship between the unit signals. In some embodiments, the association relationship may be expressed in at least one of the following two ways.

In a first expression, namely, in a circuit diagram form, input signals, output signals and control signals of logic devices or logic function modules in circuit diagram data may be marked at corresponding positions of icons of the logic devices or the logic function modules to express the association relationship, for example, the circuit diagrams shown in fig. 8 to 10 are intended to express the association relationship. In this expression, if a unit signal a1 of a bus-like packet is an input signal, an output signal, or a control signal of a target logic structure, the remaining signals of the target logic structure are all related to the unit signal a 1.

The second expression mode, namely the expression mode of the structure of the variable + expression, can obtain the incidence relation of the variable + expression form after analyzing the circuit diagram data. Such as the representations shown in tables 2 to 4. Accordingly, the association relationship may be composed of two parts, namely, a variable and an expression. The variable part may be an original name of one unit signal, and the expression part may be composed of one or more original names of unit signals and logical operators.

If a certain unit signal a2 of a certain type of bus packet exists in the variable part of a certain association or the expression part of a certain association, the unit signal a2 is related to the association.

And S360, aiming at each class bus group, modifying the association relation related to each unit signal of each class bus group by using a preset representation rule to obtain a target relation.

First, a specific implementation of S360 is described below.

For the first expression, the target relationship may be obtained by modifying the name of the signal on the corresponding logic circuit diagram or logic device diagram. That is, in this representation, names of input signals, output signals, and control signals of the logic device or the logic function module may be directly modified, so as to modify the association relationship.

Aiming at the second expression mode, the target relation is obtained by changing the variable part and the expression part, so that the modification of the incidence relation is realized.

It should be noted that, after the circuit diagram data in the circuit diagram form is modified by the first representation method, the class bus packet representation in the circuit diagram form can be realized. If the circuit diagram data of the variable-expression structure is modified by the second expression mode, the bus-like grouping expression in the form of the variable expression can be realized.

Next, in order to fully understand the preset expression rule, the following section of the embodiment of the present application will specifically describe the preset expression rule in conjunction with the specific implementation of S360.

In S360, the preset presentation rule includes at least one of the rules a to C.

Rule a replaces the original name of the unit signal in the association with the respective attribute name.

The following will specifically describe the rule a by combining the first expression described above through two examples.

In a first example, fig. 14 is a schematic diagram of fifth exemplary circuit diagram data provided in an embodiment of the present application. As shown in fig. 14, since the partial signals of the logic devices 21 to 26 and 31 to 34 all belong to the tmp packet, the original names of the unit signals within the tmp packet may be replaced with the respective attribute names.

Accordingly, fig. 15 is a schematic diagram of a sixth exemplary circuit diagram data provided in an embodiment of the present application. The association relationship in fig. 14 is modified to obtain the target relationship in fig. 15. Specifically, as can be seen by comparing fig. 14 and 15, the unit signals in the tmp packet are represented by their respective attribute names.

It should be noted that, for specific contents of the unit signal of the tmp packet and the corresponding attribute name, reference may be made to the relevant description of the foregoing section in conjunction with S340 in the embodiment of the present application, and details of this embodiment of the present application are not repeated.

In a second example, fig. 16 is a schematic diagram of seventh exemplary circuit diagram data provided in an embodiment of the present application. Fig. 16 can be obtained by modifying the expression relationship of the tmp packet in fig. 9. As can be seen from comparison between fig. 9 and fig. 16, the unit signals in the tmp packet are represented by their respective attribute names. Optionally, fig. 17 is a schematic diagram of eighth exemplary circuit diagram data provided in an embodiment of the present application. If the tmp _ zn packet of fig. 9 is modified continuously, fig. 17 can be obtained. As can be seen by comparing fig. 9 and 17, all unit signals within the tmp packet and the tmp _ zn packet are represented as respective attribute names.

It should be noted that this example shows a case where the first packet and the second packet, i.e., the tmp packet and the tmp _ zn packet, are modified in order. In other embodiments, the first packet and the second packet may also be modified simultaneously, and the modification order of the first packet and the second packet is not particularly limited in this embodiment.

After the rule a is introduced in the first expression, the following section of the embodiments of the present application will specifically describe the rule a by combining the second expression with two examples.

Continuing with table 7 as an example, for the variable and expression part in table 7, after modifying the original name of the unit signal of the tmp packet into the corresponding attribute name, the target relationship is as shown in table 8.

TABLE 8

In the second example, if the original names of the unit signals of the tmp groups in the representation relationship shown in table 3 are modified to the respective attribute names, the modified representation relationship is shown in table 9 below.

TABLE 9

Alternatively, if the original names of the unit signals of the tmp _ zn groups in the representation relationship shown in table 3 are continuously modified into the respective attribute names, the modified representation relationship is as shown in table 10 below.

Watch 10

Rule B, representing the operational relationship among all unit signals belonging to one packet in the association relationship as a first expression, the first expression including: and a packet indicator of a packet to which all the unit signals belong. Illustratively, the packet designator may include a packet name, the number of unit signals within the packet, and a state value of each unit signal when a particular logical operation is performed. For example, the state value of each unit signal when the specific logical operation is performed may include information such as the state value of each unit signal in the packet when the state value of the variable is equal to 1. As still another example, the state value of each unit signal when the specific logical operation is performed may include information such that the state value of the variable is equal to the state value of each unit signal within the 0 packet. Note that, the information such as the state value of each unit signal in the packet may be in other forms of the state value of the variable, for example, in the form of "00, 01, 11", and the like, and this is not particularly limited.

In one example, rule B will be specifically described in conjunction with the second expression described above.

With continued reference to FIG. 8, it can be seen from FIG. 8 that unit signal X44480_ ZN is associated with each of the 4 unit signals of the tmp packet, wherein the corresponding expression of FIG. 8 can be found in Table 2.

Since the state value of X44480_ ZN is 1 when the state values of all unit signals in the tmp packet are 1 and the state value of X42149_ ZN is 0, if table 2 is modified according to rule B, the modified relation can be shown in table 11.

TABLE 11

As can be seen from comparison between table 2 and table 11, the modified representation relationship in the embodiment of the present application can simplify the representation manner of the association relationship, and table 11 can visually represent the relationship between the state values of the unit signals of the X44480_ ZN and the tmp packet.

It should be noted that, although the modification manner of table 2 corresponding to fig. 8 may be according to rule B, the modification for fig. 8 may also be according to rule a. Fig. 18 is a schematic diagram of ninth exemplary circuit diagram data provided in an embodiment of the present application. Fig. 18 is a modification made to fig. 8, and as can be seen from a comparison of fig. 8 and fig. 18, the original names of the plurality of unit signals grouped by tmp in fig. 8 are modified to the attribute names in fig. 18.

A rule C representing an operational relationship between partial unit signals belonging to one packet in the association relationship as a second expression, the second expression including: a sub-packet indicator of a sub-packet to which the partial unit signal belongs. Illustratively, the sub-packet designator may include a sub-packet name, the number of unit signals within the sub-packet, and a state value of each unit signal when performing a particular logical operation. For example, the state value of each unit signal when the specific logical operation is performed may include information such as the state value of each unit signal in the sub-packet when the state value of the variable is equal to 1. For another example, the state value of each unit signal when the specific logical operation is performed may include information such as the state value of each unit signal in the sub-packet when the state value of the variable is equal to 0. Note that, the information such as the state value of each unit signal in the packet may be in other forms of the state value of the variable, for example, in the form of "00, 01, 11", and the like, and this is not particularly limited.

In one example, rule C will be specifically described in conjunction with the second expression described above.

With continued reference to fig. 10, X1241_ Q, X3160_ Q and X1825_ Q affect the output results of the 8 flip-flops, X1241_ Q, X3160_ Q and X1825_ Q may be treated as a sub-packet, such as may be represented as tmp $3_ 1.

If the state values of X3160_ Q, X1825_ Q and X1241_ Q are 101 or 010, the state value of X114_ Z is 1. If table 4 is modified according to rule C, the modified relationship can be shown in table 12.

TABLE 12

As can be seen from comparison between table 4 and table 12, the modified representation relationship in the embodiment of the present application can simplify the representation manner of the association relationship, that is, (X1241_ Q & 3 ' 60_ Q) is reduced to (tmp $3_1= =3 ' b101) i (tmp $3_1= = =3 ' b 010). And, the relationship between the state values of the output signal and the unit signals of the tmp $3_1 sub-packet can be visually expressed by the table 12.

It should be noted that, although the modification manner of table 4 corresponding to fig. 10 may be according to rule C, the modification for fig. 10 may also be according to rule a. Fig. 19 is a schematic diagram of tenth exemplary circuit diagram data provided in an embodiment of the present application. Fig. 19 is a modification of the tmp packet based on fig. 10, and it can be seen from a comparison between fig. 10 and fig. 19 that the original names of the unit signals of the tmp packet of fig. 10 are modified to the attribute names of fig. 19.

Alternatively, if the names of the unit signals of the rega packet and the regb packet are continuously modified. Fig. 20 is a schematic diagram of eleventh exemplary circuit diagram data provided in an embodiment of the present application. As can be seen from comparison between fig. 10 and fig. 20, the unit signals of the tmp packet, the rega packet, and the regb packet in fig. 10 are all modified by the rule a.

Accordingly, if the second expression is used, table 12 may be further modified to table 13.

Watch 13

After the above section of the embodiment of the present application specifically describes how to modify the association relationship, the following section of the embodiment of the present application specifically describes how to further determine the relevant scheme of the bus signal based on the bus-like packet.

In some embodiments, fig. 21 is a flowchart illustrating a method for determining a bus packet of the seventh type according to an embodiment of the present application. Fig. 21 differs from fig. 3 in that after S330, steps of determining bus signals, i.e., S370 and S380, may be further included.

S370, the bit order of all the unit signals in each class bus packet is determined.

In some embodiments, the bit sequence of the unit signals in each bus-like packet may be determined according to the actual connection relationship of the logic devices or logic function modules in the circuit diagram data or the characteristics of the target digital circuit. Specifically, the bit sequence may be determined by a computer algorithm, or by human intervention, or the like.

In some embodiments, embodiments of S370 include: and determining the bit sequence of all unit signals in each bus-like group according to a preset bit sequence determination rule.

The preset bit sequence determination rule comprises a rule D or a rule E.

And rule D, if the unit signal of the class bus packet is the input signal or the output signal of the preset logic function module, determining the bit sequence of each unit signal in the class bus packet according to the high and low bits of the unit signal of the class bus packet.

In one example, the trigger order of each unit signal may be determined according to a counter, accumulator, or the like. For example, after a 4-bit counter is determined according to the actual connection relationship of the circuit, if the tmp packet corresponds to the output signal of the 4-bit counter, the bit sequence of the 4 unit signals in the tmp packet may be determined to be X1825_ Q, X3160_ Q, X1241_ Q and X3324_ Q in sequence by the counter circuit principle.

Rule E, the bit sequence of each unit signal within a class bus packet is the bit sequence of the associated unit signal for each unit signal.

In one example, for the association shown in fig. 9, since X5518_ Z, X5561_ Z, X5557_ Z and X5526_ Z correspond one-to-one to X3324_ Q, X1825_ Q, X3160_ Q and X1241_ Q, respectively. Wherein, each group of corresponding signals are respectively associated unit signals. Accordingly, the bit order of the unit signal in the tmp _ zn packet is X5561_ Z, X5557_ Z, X5526_ Z and X5518_ Z in this order.

Compared with the scheme that unit signals need to be modified one by one when the bit sequence of other units is determined by using units such as a counter and the like, the embodiment of the application can automatically propagate to other unit signals (second-type bus groups) according to the bit sequence (first group) of the counter, and the bus determination efficiency is improved.

And S380, adjusting the unit signals in each class bus packet according to the bit sequence of all the unit signals in each class bus packet, and determining the bus signals based on the adjusted class bus packet.

First, with respect to the adjustment process of the signal unit, the following description is made with reference to a specific example.

In one case, the order of the signal units within the bus-like packet may be adjusted. The sequence adjustment process will be specifically described below by two examples.

In one example, fig. 22 is a schematic diagram of a twelfth exemplary circuit diagram data provided by an embodiment of the present application. As can be seen from a comparison of fig. 9 and 22, the order of each unit signal in the tmp packet in the bus-like packet is adjusted according to the bit order of the unit signal.

In fig. 22, the unit signal X1825_ Q is denoted as "tmp $ 0", the unit signal X3160_ Q is denoted as "tmp $ 1", the unit signal X1241_ Q is denoted as "tmp $ 2", and the unit signal X3324_ Q is denoted as "tmp $ 3".

Accordingly, the "variable-expression" shown in connection with table 8, which corresponds to fig. 22, can be adjusted.

The adjusted "variables-expressions" can be as shown in table 14.

TABLE 14

In one example, fig. 23 is a schematic diagram of thirteenth exemplary circuit diagram data provided by an embodiment of the present application. As can be seen from comparison between fig. 17 and 23, by changing the order of the logical units, it is found that the order of the unit signals in the tmp packet and the tmp _ zn packet is adjusted in accordance with the bit order of the unit signals in the tmp packet.

As can be seen from fig. 23, the unit signals in the tmp packets and the unit signals in the tmp _ zn packets on both sides of the same logic device correspond to each other in sequence number.

Accordingly, the "variable-expression" shown in connection with table 11, which corresponds to fig. 23, can be adjusted.

The adjusted "variables-expressions" can be as shown in table 15.

Watch 15

As can be seen from fig. 17 and 23, the random ordering result of the tmp-type packet signal is not correct bit sequence. In this case, the sequence number of each packet needs to be readjusted. For example, if the random order of a signal is 3, which is denoted as "packet name $ 3", and the bit order thereof is 1, the attribute name thereof may be re-denoted as "packet name $ 1". In addition, there are also cases where the randomly ordered structure of the unit signals in the packet signal happens to be its correct bit sequence, and there is no need to readjust its sequence number and its attribute name.

In another case, the number of unit signals in the bus-like packet may be adjusted. For example, if a certain type of bus packet includes 5 unit signals, the bit sequence of 4 of the unit signals can be determined, and the 5 th unit signal, for which the bit sequence cannot be determined, can be used as an independent unit signal to generate a bus signal using the 4 unit signals, for which the bit sequence can be determined.

Next, after the adjustment process of the unit signal is introduced, the embodiment of the present application will specifically describe the determination process of the bus signal.

In one example, continuing with the tmp grouping example, the four unit signals shown in table 5 may be created as one multi-bit signal after the bit order of the four unit signals X3160_ Q, X3324_ Q, X1241_ Q and X1825_ Q in the bus. The multi-bit signal corresponds to a bus signal in a Register-Transfer Level (RTL).

TABLE 16

As shown in table 16, bus signals of all unit signals of the tmp packet are generated, and the bit width of the bus signals is 4. Wherein, counter < i > represents a unit signal with sequence number i in the tmp packet after the sequence number adjustment, and i is 0, 1, 2 or 3. Illustratively, counter <0> corresponds to tmp $0, i.e., X1825_ Q.

In one example, the circuit diagram data shown in fig. 22 may be re-represented by a bus signal.

Fig. 24 is a schematic diagram of fourteenth exemplary circuit diagram data provided in an embodiment of the present application. As shown in fig. 24, the bus signals may be represented in the form of the circuit diagram shown in the figure.

As can be seen from a comparison between fig. 22 and fig. 24, the unit signal with sequence number i in the tmp packet after the sequence number adjustment can be represented by counter < i >, and i is 0, 1, 2 or 3. Illustratively, counter <0> corresponds to tmp $0, i.e., X1825_ Q.

By the bus signal representation mode provided by the example, the relation between signals in the logic circuit diagram can be simply and clearly represented.

It should be noted that the specific display manner of the bus signal can refer to the relevant contents in conjunction with fig. 11A and fig. 11B, and is not described herein again.

Based on the same application concept, the embodiment of the application provides a determination device of the class bus packet corresponding to the determination method of the class bus packet.

The following describes a device for determining generic bus packets according to an embodiment of the present application in detail with reference to the accompanying drawings.

Fig. 25 is a schematic structural diagram of a device for determining generic bus packets according to an embodiment of the present application. As shown in fig. 25, the apparatus 2500 for determining class bus packets includes a data acquisition module 2510, a grouping module 2520, and a sorting module 2530.

A data obtaining module 2510, configured to obtain circuit diagram data of the target digital circuit. Wherein the circuit diagram data includes: a plurality of unit signals transferred between logic devices of a target digital circuit.

The grouping module 2520 is configured to group the plurality of unit signals according to a preset bus signal grouping rule based on the circuit diagram data to obtain a plurality of groups.

And the sorting module 2530 is configured to, for each packet, sort all unit signals in each packet to obtain a bus-like packet composed of all unit signals.

In some embodiments, the apparatus 2500 for determining the class bus packet further includes a bit order determining module and an order adjusting module.

And the bit sequence determining module is used for determining the bit sequence of each unit signal in each class bus group according to a preset bit sequence determining rule.

And the order adjusting module is used for adjusting the unit signal in the class bus packet according to the bit order of each unit signal in each class bus packet and determining the bus signal based on the adjusted class bus packet.

Specifically, the preset bit sequence determination rule includes: and if the unit signal of the class bus packet is the input signal or the output signal of the preset logic function module, determining the bit sequence of each unit signal in the class bus packet according to the high and low bits of the input signal or the output signal of the preset logic function module.

Or,

the bit order determination rule includes: the bit sequence of the associated unit signal of each unit signal is determined according to the bit sequence of each unit signal in the bus-like packet.

In some embodiments, the apparatus 2500 for determining class bus packets further comprises a signal naming module.

The signal naming module is used for naming each unit signal according to a preset signal naming rule aiming at each class bus group to obtain an attribute name of each unit signal;

the preset signal naming rule comprises the following steps: the name of each unit signal includes a packet identification and a sequence number of each unit signal.

In some embodiments, the determining device 2500 of the class bus packet further includes a relationship determining module and a relationship modifying module.

And the relation determining module is used for determining the relevant relation related to each unit signal in a plurality of relations.

The relationship correction module is used for modifying the association relationship related to each unit signal by using a preset expression rule to obtain a target relationship;

the preset expression rules comprise:

replacing the original names of the unit signals in the association relationship with respective attribute names; and/or, expressing the operation relation among all unit signals belonging to one group in the association relation as a first expression, wherein the first expression comprises: a packet indicator of a packet to which all unit signals belong; and/or, expressing the operation relation among the partial unit signals belonging to one group in the association relation as a second expression, wherein the second expression comprises: a sub-packet indicator of a sub-packet to which the partial unit signal belongs.

In some embodiments, the plurality of packets includes at least one first packet.

Accordingly, the grouping module 2520 includes a correlation parameter determining unit and a first grouping unit.

And a correlation parameter determination unit for determining correlation parameters of the plurality of unit signals based on the circuit diagram data.

The first grouping unit is used for grouping the unit signals of which the correlation parameters meet the preset correlation condition in the plurality of unit signals to obtain at least one first grouping.

In some embodiments, the plurality of packets further includes a second packet unit.

Accordingly, the packet module 2520 also includes a second packet unit.

And the second grouping unit is used for grouping the related unit signals of each first grouping into one group in the plurality of unit signals to obtain at least one second grouping, wherein the related unit signals and the unit signals of each first grouping have a correlation relationship.

In some embodiments, the correlation parameter determining unit specifically includes:

the data processing subunit is used for processing the circuit diagram data to obtain target data;

and the parameter searching unit is used for searching the respective correlation parameters of the plurality of unit signals in the target data.

The device for determining a bus-like group according to the embodiment of the present application, after a bus signal grouping rule is preset, a unit signal belonging to a bus signal in a plurality of unit signals of circuit diagram data is preliminarily divided into a group, and when a bit sequence of the unit signal in each group is not obtained, the unit signal in the group can be divided into a bus-like group by sorting the unit signals in the group. The unit signals in each class of bus group are orderly arranged and belong to one bus signal, so that the characteristics of correlation and orderliness among the unit signals of the bus signals are reflected, and the unit signals without the bit sequences can be accurately divided.

Other details of the apparatus for determining a bus-like packet according to the embodiment of the present application are similar to the method for determining a bus-like packet described above with reference to the examples shown in fig. 1 to fig. 24, and can achieve the corresponding technical effects, and are not described herein again for brevity.

The determining device at class bus packet may include a processor 2601 and a memory 2602 storing computer program instructions.

Specifically, the processor 2601 may include a Central Processing Unit (CPU), an Application Specific Integrated Circuit (ASIC), or one or more Integrated circuits configured to implement the embodiments of the present invention.

Memory 2602 may include mass storage for data or instructions. By way of example, and not limitation, memory 2602 may include a Hard Disk Drive (HDD), a floppy Disk Drive, flash memory, an optical Disk, a magneto-optical Disk, magnetic tape, or a Universal Serial Bus (USB) Drive or a combination of two or more of these. In some instances, memory 2602 may include removable or non-removable (or fixed) media, or memory 2602 is non-volatile solid-state memory. In some embodiments, memory 2602 may be internal or external to the determining device of the class bus packet.

In some examples, Memory 2602 may be a Read Only Memory (ROM). In one example, the ROM may be mask programmed ROM, programmable ROM (prom), erasable prom (eprom), electrically erasable prom (eeprom), electrically rewritable ROM (earom), or flash memory, or a combination of two or more of these.

Memory 2602 may include Read Only Memory (ROM), Random Access Memory (RAM), magnetic disk storage media devices, optical storage media devices, flash memory devices, electrical, optical, or other physical/tangible memory storage devices. Thus, in general, the memory includes one or more tangible (non-transitory) computer-readable storage media (e.g., memory devices) encoded with software comprising computer-executable instructions and when the software is executed (e.g., by one or more processors), it is operable to perform operations described with reference to the methods according to an aspect of the present disclosure.

The processor 2601 reads and executes the computer program instructions stored in the memory 2602 to implement the method/steps in the embodiments shown in fig. 3 to fig. 22, and achieve the corresponding technical effects achieved by the example shown in fig. 3 to fig. 24 executing the method/steps, which are not described herein again for brevity.

In one example, the determining device of the class bus packet may also include a communication interface 2603 and a bus 2610. As shown in fig. 26, the processor 2601, the memory 2602, and the communication interface 2603 are connected by a bus 2610 to communicate with each other.

The communication interface 2603 is mainly used for implementing communication between modules, apparatuses, units and/or devices in the embodiments of the present invention.

Bus 2610 includes hardware, software, or both to couple the components of the online data traffic billing device to each other. By way of example, and not limitation, a Bus may include an Accelerated Graphics Port (AGP) or other Graphics Bus, an Enhanced Industry Standard Architecture (EISA) Bus, a Front-Side Bus (Front Side Bus, FSB), a Hyper Transport (HT) interconnect, an Industry Standard Architecture (ISA) Bus, an infiniband interconnect, a Low Pin Count (LPC) Bus, a memory Bus, a Micro Channel Architecture (MCA) Bus, a Peripheral Component Interconnect (PCI) Bus, a PCI-Express (PCI-X) Bus, a Serial Advanced Technology Attachment (SATA) Bus, a video electronics standards association local (VLB) Bus, or other suitable Bus or a combination of two or more of these. Bus 2610 may include one or more buses, where appropriate. Although specific buses have been described and shown in the embodiments of the invention, any suitable buses or interconnects are contemplated by the invention.

The determining device of the bus packet class may execute the determining method of the bus packet class in the embodiment of the present invention, so as to implement the determining method and apparatus of the bus packet class described in conjunction with fig. 3 to fig. 25.

In addition, in combination with the method for determining the class bus packet in the foregoing embodiment, the embodiment of the present invention may be implemented by providing a computer storage medium. The computer storage medium having computer program instructions stored thereon; the computer program instructions, when executed by a processor, implement the method of determining a bus packet of any of the above-described embodiments.

It is to be understood that the invention is not limited to the specific arrangements and instrumentality described above and shown in the drawings. A detailed description of known methods is omitted herein for the sake of brevity. In the above embodiments, several specific steps are described and shown as examples. However, the method processes of the present invention are not limited to the specific steps described and illustrated, and those skilled in the art can make various changes, modifications and additions or change the order between the steps after comprehending the spirit of the present invention.

The functional blocks shown in the above-described structural block diagrams may be implemented as hardware, software, firmware, or a combination thereof. When implemented in hardware, it may be, for example, an electronic Circuit, an Application Specific Integrated Circuit (ASIC), suitable firmware, plug-in, function card, or the like. When implemented in software, the elements of the invention are the programs or code segments used to perform the required tasks. The program or code segments may be stored in a machine-readable medium or transmitted by a data signal carried in a carrier wave over a transmission medium or a communication link. A "machine-readable medium" may include any medium that can store or transfer information. Examples of a machine-readable medium include electronic circuits, semiconductor memory devices, ROM, flash memory, Erasable ROM (EROM), floppy disks, CD-ROMs, optical disks, hard disks, fiber optic media, Radio Frequency (RF) links, and so forth. The code segments may be downloaded via computer networks such as the internet, intranet, etc.

It should also be noted that the exemplary embodiments mentioned in this patent describe some methods or systems based on a series of steps or devices. However, the present invention is not limited to the order of the above-described steps, that is, the steps may be performed in the order mentioned in the embodiments, may be performed in an order different from the order in the embodiments, or may be performed simultaneously.

Aspects of the present disclosure are described above with reference to flowchart illustrations and/or block diagrams of methods, apparatus, devices, and computer program products according to embodiments of the disclosure. It will be understood that each block of the flowchart illustrations and/or block diagrams, and combinations of blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, enable the implementation of the functions/acts specified in the flowchart and/or block diagram block or blocks. Such a processor may be, but is not limited to, a general purpose processor, a special purpose processor, an application specific processor, or a field programmable logic circuit. It will also be understood that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware for performing the specified functions or acts, or combinations of special purpose hardware and computer instructions.

As described above, only the specific embodiments of the present invention are provided, and it can be clearly understood by those skilled in the art that, for convenience and brevity of description, the specific working processes of the system, the module and the unit described above may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again. It should be understood that the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive various equivalent modifications or substitutions within the technical scope of the present invention, and these modifications or substitutions should be covered within the scope of the present invention.

Claims

1. A method for determining a generic bus packet, comprising:

obtaining circuit diagram data of a target digital circuit, wherein the circuit diagram data comprises: a plurality of unit signals and a plurality of corresponding incidence relations thereof transmitted among the logic devices of the target digital circuit;

sequencing all unit signals in each group aiming at each group to obtain a bus-like group consisting of all the unit signals;

determining the bit sequence of each unit signal in each class bus group according to a preset bit sequence determination rule;

adjusting the unit signals in each class bus packet according to the bit sequence of each unit signal in each class bus packet, and determining bus signals based on the adjusted class bus packets;

wherein the preset bit sequence determination rule comprises:

if the unit signal of the class bus packet is the input signal or the output signal of the preset logic function module, determining the bit sequence of each unit signal in the class bus packet according to the high and low bits of the input signal or the output signal of the preset logic function module, or,

the bit sequence of each unit signal within a bus-like packet is determined in accordance with the bit sequence of its associated unit signal.

2. The method of claim 1, wherein after sorting all unit signals in each group to obtain a bus-like group consisting of all unit signals, the method further comprises:

naming each unit signal according to a preset signal naming rule aiming at each class bus group to obtain an attribute name of each unit signal;

wherein, presetting the signal naming rule comprises: the name of each unit signal includes a packet identifier and a sequence number of each unit signal.

3. The method of claim 2,

after obtaining the attribute name of each unit signal, the method further includes:

determining an association relation related to each unit signal in the plurality of association relations;

modifying the association relation related to each unit signal by using a preset expression rule to obtain a target relation;

wherein, the preset representation rule comprises:

replacing the original names of the unit signals in the association relationship with respective attribute names; and/or

Expressing an operational relationship between all unit signals belonging to one packet in an association relationship as a first expression, the first expression including: a packet indicator of a packet to which all the unit signals belong; and/or

Expressing an operational relationship between partial unit signals belonging to one packet in the association relationship as a second expression, the second expression including: a sub-packet indicator of a sub-packet to which the partial unit signal belongs.

4. The method of claim 1, wherein the plurality of packets comprises at least one first packet;

the grouping the plurality of unit signals according to a preset bus signal grouping rule based on the circuit diagram data to obtain a plurality of groups comprises:

determining a correlation parameter for the plurality of unit signals based on the schematic data;

and in the plurality of unit signals, dividing the unit signals of which the correlation parameters meet a preset correlation condition into a group to obtain at least one first group.

5. The method of claim 4, wherein the plurality of packets further comprises at least one second packet, and wherein after obtaining at least one first packet, the method further comprises:

and dividing the associated unit signals of each first group into a group to obtain at least one second group, wherein the associated unit signals and the unit signals of each first group have an association relationship.

6. An apparatus for determining a generic bus packet, the apparatus comprising:

a data acquisition module, configured to acquire circuit diagram data of a target digital circuit, where the circuit diagram data includes: a plurality of unit signals and a plurality of corresponding incidence relations thereof transmitted among the logic devices of the target digital circuit;

the grouping module is used for grouping the unit signals according to a preset bus signal grouping rule based on the circuit diagram data to obtain a plurality of groups;

the sorting module is used for sorting all unit signals of input signals or output signals of the preset logic function module in each group aiming at each group to obtain a bus-like group consisting of all the unit signals;

the bit sequence determining module is used for determining the bit sequence of each unit signal in each class bus group according to a preset bit sequence determining rule;

the order adjusting module is used for adjusting the unit signals in each class bus group according to the bit order of each unit signal in each class bus group and determining bus signals based on the adjusted class bus groups;

wherein the preset bit sequence determination rule comprises: if the unit signal of the class bus packet is the input signal or the output signal of the preset logic function module, determining the bit sequence of each unit signal in the class bus packet according to the high and low bits of the input signal or the output signal of the preset logic function module, or,

7. A device for determining generic bus packets, the device comprising: a processor and a memory storing computer program instructions;

the processor reads and executes the computer program instructions to implement the method of determining a bus-like packet according to any of claims 1-5.

8. A computer storage medium having stored thereon computer program instructions which, when executed by a processor, implement the method of determining a bus-like packet according to any one of claims 1 to 5.