CN115952760A

CN115952760A - Method, device and equipment for simulating digital-analog circuit and computer storage medium

Info

Publication number: CN115952760A
Application number: CN202310245203.6A
Authority: CN
Inventors: 丁柯; 李想; 刘永萍
Original assignee: Beijing Core Vision Software Technology Co ltd
Current assignee: Beijing Core Vision Software Technology Co ltd
Priority date: 2023-03-15
Filing date: 2023-03-15
Publication date: 2023-04-11
Anticipated expiration: 2043-03-15
Also published as: CN115952760B

Abstract

The application discloses a digital-to-analog circuit simulation method, a digital-to-analog circuit simulation device and a computer storage medium. And replacing the reference relation of the marked parameter example by using a Verilog fusion algorithm based on the second Verilog data and the first Verilog data of the marked parameter example to obtain third Verilog data of the digital-analog circuit. Therefore, by adding the marking parameters to the instances with the data flow problem and creating the corresponding second Verilog data, the original data can be prevented from being directly modified, and the risk of introducing new errors is reduced. And updating the first Verilog data according to the second Verilog data of the example with the marked parameters to obtain third Verilog data of the digital-analog circuit, so that the efficiency of simulating the digital-analog circuit can be improved.

Description

Method, device and equipment for simulating digital-analog circuit and computer storage medium

Technical Field

The present application relates to the field of circuit simulation, and in particular, to a method, an apparatus, a device, and a computer storage medium for digital-to-analog circuit simulation.

Background

In order to ensure the connectivity and the coordinated operation performance between the digital circuit and the analog circuit, a digital-analog circuit hybrid simulation is usually required. The existing digital-analog hybrid circuit simulation is based on Verilog modeling of unit models in a basic unit library, each unit instance in circuit data to be simulated refers to the unit models in the basic unit library, so that corresponding Verilog views exist in all the unit instances, and then simulation is carried out on each unit instance in the circuit data to be simulated.

But because the ports of part of the analog unit devices are equivalent, namely ambiguity exists, simulation failure can be caused. In the prior art, when a unit example has a data flow problem due to ambiguity, an engineer is required to check and manually modify original data, and further the efficiency of digital-analog circuit hybrid simulation is reduced.

Disclosure of Invention

The embodiment of the application provides a digital-analog circuit simulation method, a digital-analog circuit simulation device, a digital-analog circuit simulation equipment and a computer storage medium, and can improve the simulation efficiency of the digital-analog circuit.

In a first aspect, an embodiment of the present application provides a digital-to-analog circuit simulation method, which may include:

under the condition of acquiring first Verilog data of the digital-analog circuit, simulating the first Verilog data to obtain simulation information, wherein the simulation information is used for indicating at least one example with a data flow problem in the digital-analog circuit;

adding a marking parameter to at least one instance with a data flow problem, wherein the marking parameter is used for indicating the type of the at least one instance;

creating second Verilog data for the at least one instance with the added marking parameters;

and replacing the reference relation of the marked parameter examples in the first Verilog data by using a Verilog fusion algorithm based on the second Verilog data and the first Verilog data of the marked parameter examples to obtain third Verilog data of the digital-analog circuit.

In one embodiment, the first Verilog data related to the first Verilog data includes a first model corresponding to each instance and a reference relationship of each instance, the reference relationship includes a reference relationship between each instance and the first model, and the second Verilog data includes a second model corresponding to an instance with a marked parameter;

replacing the reference relation of the marked parameter instance in the first Verilog data by utilizing a Verilog fusion algorithm based on the second Verilog data and the first Verilog data of the marked parameter instance to obtain third Verilog data of the digital-analog circuit, wherein the third Verilog data comprises the following steps:

fusing the second Verilog data of the instance with the marked parameters into the first Verilog data;

and replacing the reference relation between the marked parameter instance in the first Verilog data and the first model based on the second model in the second Verilog data of the marked parameter instance to obtain third Verilog data of the digital-analog circuit.

In one embodiment, the above mentioned method for using Verilog fusion algorithm to replace the reference relationship of the marked parameter instance in the first Verilog data based on the second Verilog data and the first Verilog data of the marked parameter instance to obtain the third Verilog data of the digital-analog circuit further includes:

according to the third Verilog data of the digital-analog circuit, carrying out simulation;

and under the condition that the simulation according to the third Verilog data of the digital-analog circuit fails, jumping to the step of simulating the first Verilog data to obtain simulation information, and re-verifying at least one example with the data flow problem in the digital-analog circuit until the simulation according to the third Verilog data of the digital-analog circuit succeeds.

In one embodiment, after adding the marking parameter to the at least one instance in which the data flow problem exists, the method further includes:

summarizing the marked parameter examples and the marked parameters corresponding to the marked parameter examples to generate an example marked parameter table;

replacing the reference relation of the marked parameter instance in the first Verilog data by using a Verilog fusion algorithm based on the second Verilog data and the first Verilog data of the marked parameter instance to obtain third Verilog data of the digital-analog circuit, wherein the third Verilog data comprises:

and replacing the Verilog data of the marked parameter examples in the first Verilog data in batches by utilizing a Verilog fusion algorithm based on the second Verilog data of the marked parameter examples in the example marking parameter table to obtain third Verilog data of the digital-analog circuit.

In a second aspect, an embodiment of the present application provides a digital-to-analog circuit simulation apparatus, where the apparatus may include:

the simulation module is used for simulating the first Verilog data of the digital-analog circuit under the condition of acquiring the first Verilog data of the digital-analog circuit to obtain simulation information, and the simulation information is used for indicating at least one example with a data flow problem in the digital-analog circuit;

the marking module is used for adding a marking parameter to at least one instance with a data flow problem, and the marking parameter is used for indicating the type of the at least one instance;

a creating module for creating second Verilog data for at least one instance to which a marking parameter is added;

and the updating module is used for replacing the reference relation of the marked parameter examples in the first Verilog data by utilizing a Verilog fusion algorithm based on the second Verilog data and the first Verilog data of the marked parameter examples to obtain third Verilog data of the digital-analog circuit.

In a third aspect, an embodiment of the present application provides an electronic device, where the device includes:

a processor;

a memory for storing processor-executable instructions;

wherein the processor is configured to execute the instructions to implement the digital-to-analog circuit simulation method as shown in any embodiment of the first aspect.

In a fourth aspect, embodiments of the present application provide a computer storage medium, where a computer program is stored on the computer readable storage medium, and when the computer program is executed by a processor, the digital-to-analog circuit simulation method shown in any one of the embodiments of the first aspect is implemented.

In a fifth aspect, the present application further provides a computer program product, where the computer program product includes a computer program, the computer program is stored in a readable storage medium, and at least one processor of the device reads and executes the computer program from the storage medium, so that the device executes the digital-to-analog circuit simulation method shown in any one of the embodiments of the first aspect.

Compared with the prior art, the embodiment of the application provides a digital-analog circuit simulation method, a digital-analog circuit simulation device, a digital-analog circuit simulation equipment and a computer storage medium, and the application has the following beneficial effects:

according to the digital-to-analog circuit simulation method, the digital-to-analog circuit simulation device and the digital-to-analog circuit simulation equipment, at least one example with a flow direction problem is obtained through simulation of first Verilog data of a digital-to-analog circuit, marking parameters are added to the example with the data flow direction problem, and second Verilog data are created for the example with the marking parameters. And replacing the reference relation of the marked parameter instance by utilizing a Verilog fusion algorithm based on the second Verilog data and the first Verilog data of the marked parameter instance to obtain third Verilog data of the digital-analog circuit.

Therefore, by adding the marking parameters to the instances with the data flow problem and creating the corresponding second Verilog data, the original data can be prevented from being directly modified, and the risk of introducing new errors is reduced. And updating the first Verilog data according to the second Verilog data of the example with the marked parameters to obtain third Verilog data of the digital-analog circuit, so that the efficiency of simulating the digital-analog circuit can be improved.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed to be used in the embodiments of the present application will be briefly described below, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

Fig. 1 is a schematic flowchart of a digital-to-analog circuit simulation method according to an embodiment of the present disclosure;

fig. 2 is a schematic diagram of an amplifier module circuit according to an embodiment of the present disclosure;

FIG. 3 is a schematic diagram of another amplifier module circuit provided in an embodiment of the present application;

FIG. 4 is a schematic diagram of a marking parameter provided by an embodiment of the present application;

FIG. 5 is a schematic flow chart of another digital-to-analog circuit simulation method provided in the embodiments of the present application;

FIG. 6 is a schematic flowchart of another simulation method for digital-to-analog circuits according to an embodiment of the present disclosure;

FIG. 7 is a schematic flow chart illustrating a further method for simulating a digital-to-analog circuit according to an embodiment of the present disclosure;

FIG. 8 is a schematic structural diagram of a digital-to-analog circuit simulation apparatus according to an embodiment of the present disclosure;

fig. 9 is a schematic structural diagram of an electronic device according to an embodiment of the present application.

Detailed Description

Features and exemplary embodiments of various aspects of the present application will be described in detail below, and in order to make objects, technical solutions and advantages of the present application more apparent, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are intended to be illustrative only and are not intended to be limiting. It will be apparent to one skilled in the art that the present application may be practiced without some of these specific details. The following description of the embodiments is merely intended to provide a better understanding of the present application by illustrating examples thereof.

It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrases "comprising 8230; \8230;" comprises 8230; "does not exclude the presence of additional like elements in a process, method, article, or apparatus that comprises the element.

Based on the background art, in the existing digital-analog circuit simulation method, when a data flow problem occurs to a unit instance due to ambiguity, an engineer is required to review and manually modify original data, which may cause a reduction in the efficiency of digital-analog circuit hybrid simulation.

In order to solve the problems in the prior art, embodiments of the present application provide a method, an apparatus, a device, and a computer storage medium for simulating a digital-to-analog circuit, where at least one example with a flow direction problem is obtained by simulating first Verilog data of the digital-to-analog circuit, a marking parameter is added to the example with the data flow direction problem, and second Verilog data is created for the example with the marking parameter. And replacing the reference relation of the marked parameter instance by utilizing a Verilog fusion algorithm based on the second Verilog data and the first Verilog data of the marked parameter instance to obtain third Verilog data of the digital-analog circuit.

First, a digital-to-analog circuit simulation method provided in the embodiment of the present application is described below. As shown in fig. 1, the digital-to-analog circuit simulation method provided in the embodiment of the present application includes the following steps:

s101: under the condition of acquiring first Verilog data of the digital-analog circuit, simulating the first Verilog data to obtain simulation information, wherein the simulation information is used for indicating at least one example with a data flow problem in the digital-analog circuit;

s102: adding a marking parameter to at least one instance with a data flow problem, wherein the marking parameter is used for indicating the type of the at least one instance;

s103: creating second Verilog data for the at least one instance with the added marking parameters;

s104: and replacing the reference relation of the marked parameter examples in the first Verilog data by using a Verilog fusion algorithm based on the second Verilog data and the first Verilog data of the marked parameter examples to obtain third Verilog data of the digital-analog circuit.

In the above digital-to-analog circuit simulation method provided by the embodiment of the application, the first Verilog data of the digital-to-analog circuit is simulated, at least one example with the flow direction problem is obtained through checking, then the marking parameter is added to the example with the data flow direction problem, and the second Verilog data is created for the example with the marking parameter. And replacing the reference relation of the marked parameter example by using a Verilog fusion algorithm based on the second Verilog data and the first Verilog data of the marked parameter example to obtain third Verilog data of the digital-analog circuit.

In S101, under the condition that the first Verilog data of the digital-analog circuit is acquired, the first Verilog data is simulated to obtain simulation information. The digital-analog circuit comprises a plurality of examples, and the simulation information comprises information for indicating the examples with data flow problems in the digital-analog circuit. In an example, taking an amplifier circuit module as an example, first, a Verilog view is created for a unit model in a basic unit library according to a conventional process, and then a Verilog file (i.e. first Verilog data) of the amplifier module is derived hierarchically, named Verilog _ old.v, where the content of the Verilog file may specifically include:

//Cell Name : RPOLY

module RPOLY(MINUS,PLUS);

inout MINUS;

inout PLUS;

assign MINUS=PLUS;

endmodule //RPOLY

//Cell Name :AMP

module AMP(VP,PVB2,PVB1,VM,VO,VS,GS);

input VP;

inputPVB2;

input PVB1;

input VM;

output VO;

input VS;

input GS;

NMOS4 N1 (.D(NOD2),.B(GS),.G(NOD2),.S(GS));

NMOS4 N2(.D(NOD3),.B(GS),.G(NOD2),.S(GS));

NMOS4 N3 (.D(VO),.B(GS),.G(NOD3),.S(GS));

PMOS4 P1 (.D(NOD4),.B(VS),.G(NOD5),.S(VS));

PMOS4 P2 (.D(NOD2),.B(VS),.G(NOD0),.S(NOD4));

PMOS4 P3 (.D(NOD3),.B(VS),.G(NOD1),.S(NOD4));

PMOS4 P4 (.D(VO),.B(VS),.G(PVB2),.S(VS));

RPOLY R1 (.MINUS (NOD0),.PLUS(VM));

RPOLY R2(.MINUS(VP),.PLUS(NOD1));

RPOLY R3 (.MINUS(NOD5),.PLUS(PVB1));

endmodule // AMP

in one example, the first Verilog data of the digital-to-analog circuit can include a first model corresponding to an instance type, a reference relationship of each instance, and a connection relationship between each instance, wherein the reference relationship includes the reference relationship between each instance and the first model. It is to be understood that instances of the same type may refer to the same first model. For example, when the R1, R2, and R3 resistors are all RPOLY type resistors, the same RPOLY type first model may be referred to.

In one example, first Verilog data is simulated to obtain simulation information, wherein the simulation information includes at least one instance for indicating that a data flow problem exists in a digital-to-analog circuit. For example, as shown in fig. 2, the first Verilog data of the amplifier module circuit is imported into simulation software for simulation, where R1, R2 and R3 are of the same type, the first model used is RPOLY, and as can be seen from the Verilog _ old.v file, the data flow direction of the first model RPOLY is to assign the data of the PLUS port to the MINUS port. As shown in fig. 3, as can be seen from simulation data, the data flow direction of R2 in the circuit is to assign the data of the mini port to PLUS, which is different from the RPOLY model, and therefore, R2 is an example of a problem of data flow direction.

In S102, a marking parameter is added to the data flow to the problematic instance. In one example, the marking parameters may be added manually or automatically in batches, and after the adding is completed, a marking parameter instance list may be formed. As can be seen from the embodiment in fig. 3, R2 is an example with a data flow problem, and therefore, a parameter INST may be added to the example R2, as shown in fig. 4. If there are multiple types of instances in the circuit that flow in opposite directions, the different parameter values can be used for distinguishing, such as resistance parameter value 1, capacitance parameter value 2, etc., wherein the same Verilog can be referred to by the same instance of the same parameter value, and a tag information table can be generated. For example, as shown in table 1, the resistance marking parameter value is 1, the capacitance marking parameter value is 2, the diode marking parameter value is 3, and R1, R2, and R3 are examples of the same marking parameter, so that the same Verilog file may be referred to.

Table 1: tagged parameter value list

In S103, a corresponding Verilog file, i.e., second Verilog data, is created for the instance to which the marking parameter is added. In one example, the second Verilog data corresponding to instances of the tagged parameters includes a second model corresponding to the instances. For example, still referring to fig. 2 and fig. 3, in step S102, a marking parameter is added to the problematic instance R2 of the data stream, and a Verilog file inst.v corresponding to the instance R2, that is, verilog data of the second model corresponding to R2, is created according to the marking parameter corresponding to R2.

In one example, after adding the marking parameter to the at least one instance in which the data flow problem exists, the method further comprises:

summarizing the marked parameter examples and the marked parameters corresponding to the marked parameter examples, and generating an example marked parameter table;

In a specific embodiment, if the flow direction of multiple types of electronic element examples in a circuit is opposite, summarizing marking parameters of at least one example, generating an example marking parameter table, and creating corresponding second Verilog data for all examples with data flow problems in batch. The second Verilog data is automatically named in a numeric suffix when multiple types of instances exist. For example, INST1.V, INST2.V.

In S104, a third Verilog data of the digital-to-analog circuit is obtained by using a Verilog fusion algorithm, and replacing the reference relationship of the marked parameter instance in the first Verilog data based on the second Verilog data and the first Verilog data of the marked parameter instance. In one example, the second Verilog data of the instances with labeled parameters generated in S103 is fused into the first Verilog data and replaces the reference relationship between the instances with labeled parameters in the first Verilog data and the first model.

In order to improve the efficiency of the simulation of the digital-analog circuit, as shown in fig. 5, as an example, the first Verilog data includes a first model corresponding to each instance and a reference relationship of each instance, the reference relationship includes a reference relationship between each instance and the first model, and the second Verilog data includes a second model corresponding to an instance with a labeled parameter; accordingly, S104 may include:

s1041: fusing second Verilog data of the instances with the marked parameters into the first Verilog data;

s1042: and replacing the reference relation between the marked parameter example in the first Verilog data and the first model based on the second model in the second Verilog data of the marked parameter example to obtain third Verilog data of the digital-analog circuit.

And replacing the reference relation of the case with the flow direction problem by the Verilog fusion algorithm based on the marked parameter case list and the second Verilog data which is newly created, and generating a new Verilog file, namely third Verilog data, so that the efficiency of simulating the digital-analog circuit can be improved. In S1041, the second Verilog data of the instance with the tagged parameter is fused to the first Verilog data. For example, the inst.v file corresponding to R2 created in S103, i.e. Verilog data of the second model, is fused into the first Verilog data.

In a specific embodiment, the Verilog data corresponding to the first model RPOLY specifically includes:

module RPOLY (MINUS,PLUS);

inout MINUS;

inout PLUS;

assignMINUS = PLUS;

endmodule // RPOLY

and generating a Verilog file inst.v corresponding to the problem-oriented instance R2, that is, verilog data of the second model specifically includes:

module INST(MINUS,PLUS);

inout MINUS;

inout PLUS;

assign PLUS = MINUS;

endmodule // INST

and adding the created Verilog file INST.v corresponding to the R2 and the Verilog data of the second model into the Verilog file (namely the first Verilog data) of the amplifier module. Obtaining:

// Cell Name : RPOLY

module INST(MINUS,PLUS);

inout MINUS;

inout PLUS;

assign PLUS = MINUS;

endmodule // INST

//Cell Name : RPOLY

module RPOLY(MINUS,PLUS);

inout MINUS;

inout PLUS;

assign MINUS=PLUS;

endmodule //RPOLY

//Cell Name : AMP

module AMP(VP,PVB2,PVB1,VM,VO,VS,GS);

input VP;

input PVB2;

input PVB1;

input VM;

output VO;

input VS;

input GS;

NMOS4 N1 (.D(NOD2),.B(GS),.G(NOD2),.S(GS));

NMOS4 N2 (.D(NOD3),.B(GS),.G(NOD2),.S(GS));

NMOS4 N3 (.D(VO),.B(GS),.G(NOD3),.S(GS));

PMOS4 P1 (.D(NOD4),.B(VS),.G(NOD5),.S(VS));

PMOS4 P2 (.D(NOD2),.B(VS),.G(NOD0),.S(NOD4));

PMOS4 P3 (.D(NOD3),.B(VS),.G(NOD1),.S(NOD4));

PMOS4 P4 (.D(VO),.B(VS),.G(PVB2),.S(VS));

RPOLY R1 (.MINUS (NOD0),.PLUS(VM));

RPOLY R2(.MINUS(VP),.PLUS(NOD1));

RPOLY R3 (.MINUS(NOD5),.PLUS(PVB1));

endmodule // AMP

in S1042, a reference relationship between the marked parameter instance in the first Verilog data and the first model is replaced based on the second model in the second Verilog data of the marked parameter instance, so as to obtain third Verilog data of the digital-to-analog circuit. For example, in the first Verilog data, the reference relationship between R2 and the RPOLY type first model is replaced with the reference relationship between INST type second model, so as to obtain second Verilog data of the digital-analog circuit. In a specific embodiment, the RPOLY R2 in the Verilog _ old.v file (i.e. the first Verilog data) of the amplifier module is replaced with INST R2, resulting in the Verilog _ new.v file (i.e. the third Verilog data) of the amplifier module

// Cell Name : RPOLY

module INST(MINUS,PLUS);

inout MINUS;

inout PLUS;

assign PLUS = MINUS;

endmodule // INST

//Cell Name : RPOLY

module RPOLY(MINUS,PLUS);

inout MINUS;

inout PLUS;

assign MINUS=PLUS;

endmodule //RPOLY

//Cell Name : AMP

module AMP(VP,PVB2,PVB1,VM,VO,VS,GS);

input VP;

input PVB2;

input PVB1;

input VM;

output VO;

input VS;

input GS;

NMOS4 N1 (.D(NOD2),.B(GS),.G(NOD2),.S(GS));

NMOS4 N2 (.D(NOD3),.B(GS),.G(NOD2),.S(GS));

NMOS4 N3 (.D(VO),.B(GS),.G(NOD3),.S(GS));

PMOS4 P1 (.D(NOD4),.B(VS),.G(NOD5),.S(VS));

PMOS4 P2 (.D(NOD2),.B(VS),.G(NOD0),.S(NOD4));

PMOS4 P3 (.D(NOD3),.B(VS),.G(NOD1),.S(NOD4));

PMOS4 P4 (.D(VO),.B(VS),.G(PVB2),.S(VS));

RPOLY R1 (.MINUS (NOD0),.PLUS(VM));

INSTR2(.MINUS(VP),.PLUS(NOD1));

RPOLY R3 (.MINUS(NOD5),.PLUS(PVB1));

endmodule // AMP

In order to improve the accuracy of the digital-to-analog circuit simulation, as shown in fig. 6, as an example, after S104, the method may further include:

s601: according to the third Verilog data of the digital-analog circuit, carrying out simulation;

s602: and under the condition that the simulation according to the third Verilog data of the digital-analog circuit fails, jumping to the step S101, and re-verifying at least one example of the data flow problem in the digital-analog circuit until the simulation according to the third Verilog data of the digital-analog circuit succeeds.

Under the condition that the simulation according to the third Verilog data of the digital-analog circuit fails, the step of simulating the first Verilog data is skipped to obtain simulation information, so that the Verilog data of the digital-analog circuit can be subjected to secondary simulation, an example with a data flow problem is checked, and the simulation accuracy of the digital-analog circuit is improved.

The following describes a simulation process of the digital-to-analog circuit in the above technical solution in an embodiment, and as shown in fig. 7, the steps in the figure are as follows:

s701, modeling a basic unit library;

s702, exporting a simulation module Verilog file (namely first Verilog data) in a layering way;

s703, importing simulation software for analysis;

s704, checking the flow of data to the problem instance (namely the target instance) in the circuit diagram;

s705, adding a marking parameter INST to a problem instance (namely a target instance) to form a marking instance list;

s706, creating an example Verilog file (namely second Verilog data) for the example of the marking parameter;

s707, generating a new module Verilog file (namely third Verilog data) by utilizing a Verilog fusion algorithm;

and S708, performing simulation.

The foregoing is a specific implementation of the digital-to-analog circuit simulation method provided in the embodiment of the present application. Based on the digital-analog circuit simulation method provided by the above embodiment, correspondingly, the present application also provides a specific implementation manner of the digital-analog circuit simulation apparatus, please refer to the following embodiments.

As shown in fig. 8, an analog-to-digital circuit simulation apparatus 800 according to an embodiment of the present application includes:

the simulation module 801 is configured to, under the condition that first Verilog data of the digital-analog circuit is obtained, simulate the first Verilog data to obtain simulation information, where the simulation information is used to indicate at least one instance in which a data flow problem exists in the digital-analog circuit;

a marking module 802, configured to add a marking parameter to at least one instance in which a data flow problem exists, where the marking parameter is used to indicate a type of the at least one instance;

a creating module 803, configured to create second Verilog data for the at least one instance to which the marking parameter is added;

and the updating module 804 is configured to replace the reference relationship of the marked parameter instance in the first Verilog data by using a Verilog fusion algorithm based on the second Verilog data and the first Verilog data of the marked parameter instance, so as to obtain third Verilog data of the digital-analog circuit.

In the digital-analog circuit simulation device 800 provided by the embodiment of the application, the simulation module 801 is used for simulating the first Verilog data of the digital-analog circuit, at least one example with a data flow direction problem is obtained through troubleshooting, the marking module 802 is used for adding marking parameters to the example with the data flow direction problem, and the creating module 803 is used for creating a second Verilog file for the example with the marking parameters. The updating module 804 replaces the reference relationship of the example with the marked parameters by using the Verilog fusion algorithm based on the second Verilog data and the first Verilog data of the example with the marked parameters, so as to obtain third Verilog data of the digital-analog circuit.

Therefore, by adding the marking parameters to the example with the data flow problem and then creating the second Verilog data to the example with the marking parameters, the original data can be prevented from being directly modified, and the risk of introducing new errors is reduced. And updating the first Verilog data according to the second Verilog data of the example with the marked parameters to obtain third Verilog data of the digital-analog circuit, so that the efficiency of simulating the digital-analog circuit can be improved.

As another embodiment of the present application, in order to improve the efficiency of simulating the digital-to-analog circuit, the updating module 804 may include:

the adding unit is used for fusing the second Verilog data of the marked parameter instance into the first Verilog data;

and the updating unit is used for replacing the reference relation between the marked parameter example in the first Verilog data and the first model based on the second model in the second Verilog data of the marked parameter example to obtain third Verilog data of the digital-analog circuit.

As another embodiment of the present application, in order to improve the accuracy of the digital-to-analog circuit simulation, the digital-to-analog circuit simulation apparatus 800 may further include:

the second simulation module is used for carrying out simulation according to the third Verilog data of the digital-analog circuit;

and the skipping module is used for skipping to the step of simulating the first Verilog data to obtain simulation information under the condition that the simulation according to the third Verilog data of the digital-analog circuit fails, and rechecking at least one example with the data flow direction problem in the digital-analog circuit until the simulation according to the third Verilog data of the digital-analog circuit succeeds.

the summarizing module is used for summarizing the marked parameter examples and the marked parameters corresponding to the marked parameter examples and generating an example marked parameter table;

accordingly, the update module 804 may be specifically configured to:

Based on the digital-to-analog circuit simulation method and apparatus provided in the foregoing embodiments, an embodiment of the present application further provides an electronic device 900, as shown in fig. 9:

the simulation system comprises a processor 901, a memory 902 and a computer program stored in the memory 902 and capable of running on the processor 901, wherein the computer program realizes each process of the above embodiments of the digital-analog circuit simulation method when being executed by the processor 901, and can achieve the same technical effects.

Specifically, the processor 901 may include a Central Processing Unit (CPU), or an Application Specific Integrated Circuit (ASIC), or may be configured to implement one or more Integrated circuits of the embodiments of the present Application.

Memory 902 may include mass storage for data or instructions. By way of example, and not limitation, memory 902 may include a Hard Disk Drive (HDD), a floppy Disk Drive, flash memory, an optical Disk, a magneto-optical Disk, tape, or a Universal Serial Bus (USB) Drive or a combination of two or more of these. Memory 902 may include removable or non-removable (or fixed) media, where appropriate. The memory 902 may be internal or external to the integrated gateway disaster recovery device, where appropriate. In a particular embodiment, the memory 902 is a non-volatile solid-state memory.

In particular embodiments, memory may include Read Only Memory (ROM), random Access Memory (RAM), magnetic disk storage media devices, optical storage media devices, flash memory devices, electrical, optical, or other physical/tangible memory storage devices. Thus, in general, the memory includes one or more tangible (non-transitory) computer-readable storage media (e.g., memory devices) encoded with software comprising computer-executable instructions and when the software is executed (e.g., by one or more processors), it is operable to perform operations described with reference to the methods according to an aspect of the application.

The processor 901 realizes any one of the digital-to-analog circuit simulation methods in the above embodiments by reading and executing computer program instructions stored in the memory 902.

In one example, the electronic device can also include a communication interface 903 and a bus 910. As an example, as shown in fig. 9, the processor 901, the memory 902 and the communication interface 903 are connected via a bus 910 to complete communication with each other.

The communication interface 903 is mainly used for implementing communication between modules, apparatuses, units and/or devices in this embodiment of the application.

Bus 910 includes hardware, software, or both to couple the components of the online data traffic billing device to each other. By way of example, and not limitation, a bus may include an Accelerated Graphics Port (AGP) or other graphics bus, an Enhanced Industrial Standard Architecture (EISA) bus, a Front Side Bus (FSB), a Hyper Transport (HT) interconnect, an Industrial Standard Architecture (ISA) bus, an infiniband interconnect, a Low Pin Count (LPC) bus, a memory bus, a Micro Channel Architecture (MCA) bus, a Peripheral Component Interconnect (PCI) bus, a PCI-Express (PCI-X) bus, a Serial Advanced Technology Attachment (SATA) bus, a video electronics standards association local (VLB) bus, or other suitable bus or a combination of two or more of these. Bus 910 can include one or more buses, where appropriate. Although specific buses are described and shown in the embodiments of the application, any suitable buses or interconnects are contemplated by the application.

The embodiment of the present application further provides a computer-readable storage medium, where a computer program is stored on the computer-readable storage medium, and when the computer program is executed by a processor, the computer program implements each process of the above digital-to-analog circuit simulation method embodiment, and can achieve the same technical effect, and in order to avoid repetition, details are not repeated here. The computer-readable storage medium may be a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk, or an optical disk.

It is to be understood that the present application is not limited to the particular arrangements and instrumentality described above and shown in the attached drawings. A detailed description of known methods is omitted herein for the sake of brevity. In the above embodiments, several specific steps are described and shown as examples. However, the method processes of the present application are not limited to the specific steps described and illustrated, and those skilled in the art can make various changes, modifications, and additions or change the order between the steps after comprehending the spirit of the present application.

The functional blocks shown in the above structural block diagrams may be implemented as hardware, software, firmware, or a combination thereof. When implemented in hardware, it may be, for example, an electronic circuit, an Application Specific Integrated Circuit (ASIC), suitable firmware, plug-in, function card, or the like. When implemented in software, the elements of the present application are the programs or code segments used to perform the required tasks. The program or code segments may be stored in a machine-readable medium or transmitted by a data signal carried in a carrier wave over a transmission medium or a communication link. A "machine-readable medium" may include any medium that can store or transfer information. Examples of a machine-readable medium include electronic circuits, semiconductor memory devices, ROM, flash memory, erasable ROM (EROM), floppy disks, CD-ROMs, optical disks, hard disks, fiber optic media, radio Frequency (RF) links, and so forth. The code segments may be downloaded via computer networks such as the internet, intranets, etc.

It should also be noted that the exemplary embodiments mentioned in this application describe some methods or systems based on a series of steps or devices. However, the present application is not limited to the order of the above-described steps, that is, the steps may be performed in the order mentioned in the embodiments, may be performed in an order different from the order in the embodiments, or may be performed simultaneously.

Aspects of the present application are described above with reference to flowchart illustrations and/or block diagrams of methods, apparatus, and computer program products according to embodiments of the application. It will be understood that each block of the flowchart illustrations and/or block diagrams, and combinations of blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, enable the implementation of the functions/acts specified in the flowchart and/or block diagram block or blocks. Such a processor may be, but is not limited to, a general purpose processor, a special purpose processor, an application specific processor, or a field programmable logic circuit. It will also be understood that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware for performing the specified functions or acts, or combinations of special purpose hardware and computer instructions.

As will be apparent to those skilled in the art, for convenience and brevity of description, the specific working processes of the systems, modules and units described above may refer to corresponding processes in the foregoing method embodiments, and are not described herein again. It should be understood that the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive various equivalent modifications or substitutions within the technical scope of the present application, and these modifications or substitutions should be covered within the scope of the present application.

Claims

1. A method of digital-to-analog circuit simulation, comprising:

under the condition of acquiring first Verilog data of a digital-analog circuit, simulating the first Verilog data to obtain simulation information, wherein the simulation information is used for indicating at least one example with a data flow problem in the digital-analog circuit;

adding a marking parameter to the at least one instance with the data flow problem, wherein the marking parameter is used for indicating the type of the at least one instance;

creating second Verilog data for the at least one instance to which the tagged parameters are added;

2. The method of claim 1, wherein the first Verilog data comprises a first model corresponding to each instance and a reference relationship of each instance, the reference relationship comprises a reference relationship between each instance and the first model, and the second Verilog data comprises a second model corresponding to the instance with the labeled parameter;

fusing second Verilog data of the instances of tagged parameters into the first Verilog data;

and replacing the reference relation between the marked parameter example and the first model in the first Verilog data based on the second model in the second Verilog data of the marked parameter example to obtain third Verilog data of the digital-analog circuit.

3. The method according to claim 1, wherein after replacing the reference relationship of the marked instance in the first Verilog data with the second Verilog data of the marked instance and the first Verilog data by using Verilog fusion algorithm, and obtaining third Verilog data of the digital-analog circuit, the method further comprises:

and under the condition that the simulation according to the third Verilog data of the digital-analog circuit fails, jumping to the step of simulating the first Verilog data to obtain simulation information, and re-verifying at least one example with the data flow direction problem in the digital-analog circuit until the simulation according to the third Verilog data of the digital-analog circuit succeeds.

4. The method according to any one of claims 1-3, wherein after adding the marking parameter to the at least one instance in which the data flow problem exists, further comprising:

and replacing the Verilog data of the marked parameter examples in the first Verilog data in batch by using a Verilog fusion algorithm based on the second Verilog data of the marked parameter examples in the example marking parameter table to obtain third Verilog data of the digital-analog circuit.

5. A digital to analog circuit emulation apparatus, comprising:

the simulation module is used for simulating the first Verilog data of the digital-analog circuit under the condition that the first Verilog data of the digital-analog circuit are obtained to obtain simulation information, and the simulation information is used for indicating at least one example with a data flow problem in the digital-analog circuit;

a marking module, configured to add a marking parameter to the at least one instance with the data flow problem, where the marking parameter is used to indicate a type of the at least one instance;

the creating module is used for creating second Verilog data for at least one example added with the marking parameters;

6. An electronic device, characterized in that the device comprises: a processor and a memory storing computer program instructions;

the processor, when executing the computer program instructions, implements the digital to analog circuit simulation method of any of claims 1-4.

7. A computer-readable storage medium having computer program instructions stored thereon which, when executed by a processor, implement the digital-to-analog circuit simulation method of any of claims 1-4.

8. A computer program product, characterized in that instructions in the computer program product, when executed by a processor of an electronic device, cause the electronic device to perform the digital-to-analog circuit simulation method of any of claims 1-4.