CN115952760B - Digital-analog circuit simulation method, device, equipment and computer storage medium - Google Patents
Digital-analog circuit simulation method, device, equipment and computer storage medium Download PDFInfo
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- CN115952760B CN115952760B CN202310245203.6A CN202310245203A CN115952760B CN 115952760 B CN115952760 B CN 115952760B CN 202310245203 A CN202310245203 A CN 202310245203A CN 115952760 B CN115952760 B CN 115952760B
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Abstract
The application discloses a simulation method, a simulation device, simulation equipment and a computer storage medium of a digital-analog circuit. And replacing the reference relation of the instance with the marking parameters based on the second Verilog data and the first Verilog data of the instance with the marking parameters by using a Verilog fusion algorithm to obtain third Verilog data of the digital-to-analog circuit. Therefore, by adding the marking parameters to the instance with the data flow problem and creating the corresponding second Verilog data, the original data can be prevented from being directly modified, and the risk of introducing new errors is reduced. And updating the first Verilog data according to the second Verilog data with the marked parameter example to obtain third Verilog data of the digital-to-analog circuit, so that the simulation efficiency of the digital-to-analog circuit can be improved.
Description
Technical Field
The present application relates to the field of circuit simulation, and in particular, to a digital-analog circuit simulation method, apparatus, device, and computer storage medium.
Background
In order to ensure connectivity and coordinated performance between digital and analog circuits, digital-to-analog circuit hybrid simulations are typically required. The existing digital-analog hybrid circuit simulation is based on carrying out Verilog modeling on unit models in a basic unit library, each unit instance in circuit data to be simulated refers to the unit models in the basic unit library, so that the corresponding Verilog view exists in all the unit instances, and then each unit instance in the circuit data to be simulated is subjected to simulation.
But may result in simulation failure due to port equivalency, i.e., ambiguity, of a portion of the analog cell device. In the prior art, when a data flow problem occurs in a unit instance due to ambiguity, engineers are required to check and manually modify original data, which further results in reduced efficiency of mixed simulation of digital-analog circuits.
Disclosure of Invention
The embodiment of the application provides a digital-analog circuit simulation method, a device, equipment and a computer storage medium, which can improve the simulation efficiency of a digital-analog circuit.
In a first aspect, an embodiment of the present application provides a digital-to-analog circuit simulation method, which may include:
under the condition that first Verilog data of the digital-to-analog circuit are obtained, simulating the first Verilog data to obtain simulation information, wherein the simulation information is used for indicating at least one example of a data flow problem in the digital-to-analog circuit;
adding a marking parameter to at least one instance having a data flow problem, the marking parameter being used to indicate a type of the at least one instance;
creating second Verilog data for at least one instance to which the marking parameters are added;
and replacing the reference relation of the example with the marking parameters in the first Verilog data based on the second Verilog data and the first Verilog data of the example with the marking parameters by using a Verilog fusion algorithm to obtain third Verilog data of the digital-to-analog circuit.
In one embodiment, the first Verilog data includes a first model corresponding to each instance and a reference relationship of each instance, the reference relationship includes a reference relationship between each instance and the first model, and the second Verilog data includes a second model corresponding to the instance with the marking parameter;
replacing the reference relation of the example with the marking parameters in the first Verilog data based on the second Verilog data and the first Verilog data of the example with the marking parameters by using a Verilog fusion algorithm to obtain third Verilog data of the digital-to-analog circuit, wherein the third Verilog data comprises:
fusing second Verilog data with instances of the tagged parameters into the first Verilog data;
and replacing the reference relation between the example with the marking parameters in the first Verilog data and the first model based on the second model in the second Verilog data with the example with the marking parameters to obtain third Verilog data of the digital-to-analog circuit.
In one embodiment, the above-mentioned Verilog fusion algorithm is based on the second Verilog data and the first Verilog data with the instance of the marking parameter, and after replacing the reference relationship with the instance of the marking parameter in the first Verilog data, obtaining the third Verilog data of the digital-to-analog circuit, the method further includes:
according to the third Verilog data of the digital-analog circuit, simulation is carried out;
and under the condition that the simulation according to the third Verilog data of the digital-to-analog circuit fails, jumping to the step of simulating the first Verilog data to obtain simulation information, and rechecking at least one example of the problem of data flow in the real-to-analog circuit until the simulation according to the third Verilog data of the digital-to-analog circuit is successful.
In one embodiment, after adding the marking parameter to at least one instance of the data flow problem, the method further includes:
summarizing the examples with the marking parameters and the marking parameters corresponding to the examples with the marking parameters to generate an example marking parameter table;
replacing the reference relation of the example with the marking parameters in the first Verilog data based on the second Verilog data and the first Verilog data of the example with the marking parameters by using a Verilog fusion algorithm to obtain third Verilog data of the digital-to-analog circuit, wherein the third Verilog data comprises:
and replacing the Verilog data of the examples with the marking parameters in the first Verilog data in batches based on the second Verilog data of the examples with the marking parameters in the example marking parameter table by using a Verilog fusion algorithm to obtain third Verilog data of the digital-to-analog circuit.
In a second aspect, an embodiment of the present application provides a digital-analog circuit simulation apparatus, where the apparatus may include:
the simulation module is used for simulating the first Verilog data to obtain simulation information under the condition that the first Verilog data of the digital-to-analog circuit is obtained, and the simulation information is used for indicating at least one example of the problem of data flow in the digital-to-analog circuit;
a marking module for adding marking parameters to at least one instance having a data flow problem, the marking parameters being used to indicate the type of the at least one instance;
a creation module for creating second Verilog data for at least one instance to which the marking parameters are added;
and the updating module is used for replacing the reference relation of the instance with the marking parameter in the first Verilog data based on the second Verilog data and the first Verilog data of the instance with the marking parameter by using a Verilog fusion algorithm to obtain third Verilog data of the digital-to-analog circuit.
In a third aspect, an embodiment of the present application provides an electronic device, including:
a processor;
a memory for storing processor-executable instructions;
wherein the processor is configured to execute instructions to implement a digital-to-analog circuit emulation method as shown in any embodiment of the first aspect.
In a fourth aspect, embodiments of the present application provide a computer storage medium having a computer program stored thereon, which when executed by a processor implements a digital-to-analog circuit emulation method as shown in any of the embodiments of the first aspect.
In a fifth aspect, embodiments of the present application also provide a computer program product comprising a computer program stored in a readable storage medium, the at least one processor of the apparatus reading and executing the computer program from the storage medium, causing the apparatus to perform the digital-to-analog circuit emulation method shown in any one of the embodiments of the first aspect.
The embodiment of the application provides a digital-analog circuit simulation method, a device, equipment and a computer storage medium, which have the following beneficial effects compared with the prior art:
according to the simulation method, the simulation device, the simulation equipment and the computer storage medium of the digital-analog circuit, at least one example with a flow problem is obtained through the simulation of the first Verilog data of the digital-analog circuit, then the marking parameters are added to the example with the flow problem, and the second Verilog data is created for the example with the marking parameters. And replacing the reference relation of the instance with the marking parameters based on the second Verilog data and the first Verilog data of the instance with the marking parameters by using a Verilog fusion algorithm to obtain third Verilog data of the digital-to-analog circuit.
Therefore, by adding the marking parameters to the instance with the data flow problem and creating the corresponding second Verilog data, the original data can be prevented from being directly modified, and the risk of introducing new errors is reduced. And updating the first Verilog data according to the second Verilog data with the marked parameter example to obtain third Verilog data of the digital-to-analog circuit, so that the simulation efficiency of the digital-to-analog circuit can be improved.
Drawings
In order to more clearly illustrate the technical solution of the embodiments of the present application, the drawings that are needed to be used in the embodiments of the present application will be briefly described, and it is possible for a person skilled in the art to obtain other drawings according to these drawings without inventive effort.
FIG. 1 is a schematic flow chart of a digital-to-analog circuit simulation method according to an embodiment of the present application;
FIG. 2 is a schematic diagram of an amplifier module circuit according to an embodiment of the present application;
FIG. 3 is a schematic diagram of another amplifier module circuit provided by an embodiment of the present application;
FIG. 4 is a schematic diagram of a marking parameter according to an embodiment of the present application;
FIG. 5 is a flow chart of another simulation method of a digital-to-analog circuit according to an embodiment of the present application;
FIG. 6 is a flow chart of another simulation method of a digital-to-analog circuit according to an embodiment of the present application;
FIG. 7 is a flow chart of another simulation method of a digital-to-analog circuit according to an embodiment of the present application;
FIG. 8 is a schematic diagram of a digital-to-analog circuit simulation device according to an embodiment of the present application;
fig. 9 is a schematic structural diagram of an electronic device according to an embodiment of the present application.
Detailed Description
Features and exemplary embodiments of various aspects of the present application will be described in detail below, and in order to make the objects, technical solutions and advantages of the present application more apparent, the present application will be described in further detail below with reference to the accompanying drawings and the detailed embodiments. It should be understood that the particular embodiments described herein are meant to be illustrative of the application only and not limiting. It will be apparent to one skilled in the art that the present application may be practiced without some of these specific details. The following description of the embodiments is merely intended to provide a better understanding of the application by showing examples of the application.
It is noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises an element.
Based on the background art, in the existing digital-analog circuit simulation method, when the unit instance has a data flow problem due to ambiguity, an engineer is required to check and manually modify the original data, which results in the reduction of the efficiency of the digital-analog circuit hybrid simulation.
In order to solve the problems in the prior art, the embodiment of the application provides a digital-analog circuit simulation method, a device, equipment and a computer storage medium. And replacing the reference relation of the instance with the marking parameters based on the second Verilog data and the first Verilog data of the instance with the marking parameters by using a Verilog fusion algorithm to obtain third Verilog data of the digital-to-analog circuit.
Therefore, by adding the marking parameters to the instance with the data flow problem and creating the corresponding second Verilog data, the original data can be prevented from being directly modified, and the risk of introducing new errors is reduced. And updating the first Verilog data according to the second Verilog data with the marked parameter example to obtain third Verilog data of the digital-to-analog circuit, so that the simulation efficiency of the digital-to-analog circuit can be improved.
The following first describes a digital-analog circuit simulation method provided by the embodiment of the application. As shown in fig. 1, the digital-analog circuit simulation method provided by the embodiment of the application comprises the following steps:
s101: under the condition that first Verilog data of the digital-to-analog circuit are obtained, simulating the first Verilog data to obtain simulation information, wherein the simulation information is used for indicating at least one example of a data flow problem in the digital-to-analog circuit;
s102: adding a marking parameter to at least one instance having a data flow problem, the marking parameter being used to indicate a type of the at least one instance;
s103: creating second Verilog data for at least one instance to which the marking parameters are added;
s104: and replacing the reference relation of the example with the marking parameters in the first Verilog data based on the second Verilog data and the first Verilog data of the example with the marking parameters by using a Verilog fusion algorithm to obtain third Verilog data of the digital-to-analog circuit.
The simulation method for the digital-analog circuit provided by the embodiment of the application comprises the steps of obtaining at least one example with a flow problem by checking the first Verilog data of the digital-analog circuit, adding a marking parameter to the example with the data flow problem, and creating second Verilog data for the example with the marking parameter. And replacing the reference relation of the instance with the marking parameters based on the second Verilog data and the first Verilog data of the instance with the marking parameters by using a Verilog fusion algorithm to obtain third Verilog data of the digital-to-analog circuit.
Therefore, by adding the marking parameters to the instance with the data flow problem and creating the corresponding second Verilog data, the original data can be prevented from being directly modified, and the risk of introducing new errors is reduced. And updating the first Verilog data according to the second Verilog data with the marked parameter example to obtain third Verilog data of the digital-to-analog circuit, so that the simulation efficiency of the digital-to-analog circuit can be improved.
In S101, when the first Verilog data of the digital-to-analog circuit is acquired, the first Verilog data is simulated to obtain simulation information. Wherein the digital-to-analog circuit includes a plurality of instances, and the simulation information includes information indicating an instance in the digital-to-analog circuit where a data flow problem exists. In one example, taking an amplifier circuit module as an example, a Verilog view is first created for a unit model in a basic unit library according to a conventional flow, and then a Verilog file (i.e., first Verilog data) of the amplifier module is exported in a hierarchical manner, where the named verilog_old.v, the Verilog file content may specifically include:
//Cell Name : RPOLY
module RPOLY(MINUS,PLUS);
inout MINUS;
inout PLUS;
assign MINUS=PLUS;
endmodule //RPOLY
//Cell Name :AMP
module AMP(VP,PVB2,PVB1,VM,VO,VS,GS);
input VP;
inputPVB2;
input PVB1;
input VM;
output VO;
input VS;
input GS;
NMOS4 N1 (.D(NOD2),.B(GS),.G(NOD2),.S(GS));
NMOS4 N2(.D(NOD3),.B(GS),.G(NOD2),.S(GS));
NMOS4 N3 (.D(VO),.B(GS),.G(NOD3),.S(GS));
PMOS4 P1 (.D(NOD4),.B(VS),.G(NOD5),.S(VS));
PMOS4 P2 (.D(NOD2),.B(VS),.G(NOD0),.S(NOD4));
PMOS4 P3 (.D(NOD3),.B(VS),.G(NOD1),.S(NOD4));
PMOS4 P4 (.D(VO),.B(VS),.G(PVB2),.S(VS));
RPOLY R1 (.MINUS (NOD0),.PLUS(VM));
RPOLY R2(.MINUS(VP),.PLUS(NOD1));
RPOLY R3 (.MINUS(NOD5),.PLUS(PVB1));
endmodule // AMP
in one example, the first Verilog data of the digital-to-analog circuit may include a first model corresponding to the instance type, a reference relationship for each instance, and a connection relationship between each instance, wherein the reference relationship includes a reference relationship between each instance and the first model. It will be appreciated that instances of the same type may refer to the same first model. For example, when the resistances of R1, R2, and R3 are all RPOLY-type resistances, the same RPOLY-type first model can be cited.
In one example, the first Verilog data is simulated to obtain simulation information, wherein the simulation information includes at least one instance for indicating that a data flow problem exists in the digital-to-analog circuit. For example, as shown in fig. 2, the first Verilog data of the amplifier module circuit is imported into simulation software for simulation, wherein R1, R2 and R3 are of the same type, the first model used is RPOLY, and as known from the verilog_old.v file, the data flow direction of the first model RPOLY is to assign the data of the PLUS port to the MINUS port. As shown in fig. 3, it is known from simulation data that the data flow of R2 in the circuit assigns data of the menu port to the PLUS, which is different from the RPOLY model, and thus R2 is an example where there is a problem of the data flow.
In S102, a marking parameter is added to an instance in which the data flow is problematic. In one example, the marking parameters may be added manually or automatically in batch, and a marking parameter instance list may be formed after the addition is completed. As can be seen from the embodiment of fig. 3, R2 is an example where there is a problem in the data flow direction, so the parameter INST can be added to the example R2, as shown in fig. 4. If there are multiple types of instances in the circuit that are in opposite flow, different parameter values may be used to distinguish, for example, a resistance parameter value of 1, a capacitance parameter value of 2, etc., where instances of the same parameter value may refer to the same Verilog, and a flag information table may be generated. For example, as shown in table 1, the resistance flag parameter value is 1, the capacitance flag parameter value is 2, the diode flag parameter value is 3, and R1, R2, and R3 are examples of the same flag parameters, so the same Verilog file can be cited.
Table 1: marking parameter value list
In S103, a corresponding Verilog file, i.e., second Verilog data, is created for the instance to which the markup parameters are added. In one example, the second Verilog data corresponding to the instance with the tagged parameters includes a second model corresponding to the instance. For example, still referring to fig. 2 and 3, in step S102, a marking parameter is added to the instance R2 having a problem in the data flow direction, and according to the marking parameter corresponding to R2, a Verilog file inst.v corresponding to the instance R2, that is, verilog data of the second model corresponding to R2 is created.
In one example, after adding the marking parameter to at least one instance where there is a data flow problem, further comprising:
summarizing the examples with the marking parameters and the marking parameters corresponding to the examples with the marking parameters to generate an example marking parameter table;
replacing the reference relation of the example with the marking parameters in the first Verilog data based on the second Verilog data and the first Verilog data of the example with the marking parameters by using a Verilog fusion algorithm to obtain third Verilog data of the digital-to-analog circuit, wherein the third Verilog data comprises:
and replacing the Verilog data of the examples with the marking parameters in the first Verilog data in batches based on the second Verilog data of the examples with the marking parameters in the example marking parameter table by using a Verilog fusion algorithm to obtain third Verilog data of the digital-to-analog circuit.
In a specific embodiment, if multiple types of electronic component examples exist in the circuit and the flow directions are opposite, marking parameters of at least one example are summarized, an example marking parameter table is generated, and corresponding second Verilog data are created in batches for all the examples with the data flow direction problem. When multiple types of instances exist, the second Verilog data is automatically named in a digital suffix manner. For example, INST1.V, INST2.V.
In S104, using a Verilog fusion algorithm, replacing the reference relation of the instance with the marking parameter in the first Verilog data based on the second Verilog data and the first Verilog data of the instance with the marking parameter, and obtaining third Verilog data of the digital-to-analog circuit. In one example, the second Verilog data of the marked instances of parameters generated in S103 is fused into the first Verilog data and replaces the referencing relationship between the marked instances of parameters in the first Verilog data and the first model.
In order to improve the efficiency of the log circuit simulation, as shown in fig. 5, as an example, the first Verilog data includes a first model corresponding to each instance and a reference relationship of each instance, the reference relationship includes a reference relationship between each instance and the first model, and the second Verilog data includes a second model corresponding to the instance with a marking parameter; accordingly, S104 may include:
s1041: fusing second Verilog data with instances of the tagged parameters into the first Verilog data;
s1042: and replacing the reference relation between the example with the marking parameters in the first Verilog data and the first model based on the second model in the second Verilog data with the example with the marking parameters to obtain third Verilog data of the digital-to-analog circuit.
And replacing the reference relation with the flow problem instance based on the marked parameter instance list and the re-created second Verilog data by using a Verilog fusion algorithm to generate a new Verilog file, namely third Verilog data, so that the simulation efficiency of the log-mode circuit can be improved. In S1041, second Verilog data with instances of tagged parameters are fused into the first Verilog data. For example, the ins t.v file corresponding to R2 created in S103, i.e. Verilog data of the second model, is fused into the first Verilog data.
In a specific embodiment, the Verilog data corresponding to the first model RPOLY specifically includes:
module RPOLY (MINUS,PLUS);
inout MINUS;
inout PLUS;
assignMINUS = PLUS;
endmodule // RPOLY
the generation of Verilog data of the second model, which is the Verilog file inst.v corresponding to the flow problem instance R2, specifically includes:
module INST(MINUS,PLUS);
inout MINUS;
inout PLUS;
assign PLUS = MINUS;
endmodule // INST
and adding the created Verilog file INST.v corresponding to the R2 and the Verilog data of the second model into the Verilog file (namely the first Verilog data) of the amplifier module. The method comprises the following steps:
// Cell Name : RPOLY
module INST(MINUS,PLUS);
inout MINUS;
inout PLUS;
assign PLUS = MINUS;
endmodule // INST
//Cell Name : RPOLY
module RPOLY(MINUS,PLUS);
inout MINUS;
inout PLUS;
assign MINUS=PLUS;
endmodule //RPOLY
//Cell Name : AMP
module AMP(VP,PVB2,PVB1,VM,VO,VS,GS);
input VP;
input PVB2;
input PVB1;
input VM;
output VO;
input VS;
input GS;
NMOS4 N1 (.D(NOD2),.B(GS),.G(NOD2),.S(GS));
NMOS4 N2 (.D(NOD3),.B(GS),.G(NOD2),.S(GS));
NMOS4 N3 (.D(VO),.B(GS),.G(NOD3),.S(GS));
PMOS4 P1 (.D(NOD4),.B(VS),.G(NOD5),.S(VS));
PMOS4 P2 (.D(NOD2),.B(VS),.G(NOD0),.S(NOD4));
PMOS4 P3 (.D(NOD3),.B(VS),.G(NOD1),.S(NOD4));
PMOS4 P4 (.D(VO),.B(VS),.G(PVB2),.S(VS));
RPOLY R1 (.MINUS (NOD0),.PLUS(VM));
RPOLY R2(.MINUS(VP),.PLUS(NOD1));
RPOLY R3 (.MINUS(NOD5),.PLUS(PVB1));
endmodule // AMP
in S1042, replacing a reference relationship between the instance with the mark parameter in the first Verilog data and the first model based on the second model in the second Verilog data with the instance with the mark parameter to obtain third Verilog data of the digital-to-analog circuit. For example, the reference relation between R2 and the RPOLY type first model is replaced by the reference relation between the R2 and the INST type second model in the first Verilog data, so as to obtain the second Verilog data of the digital-to-analog circuit. In a specific embodiment, RPOLY R2 in the Verilog_old.v file of the amplifier module (i.e., the first Verilog data) is replaced with INST R2 to obtain the Verilog_new.v file of the amplifier module (i.e., the third Verilog data)
// Cell Name : RPOLY
module INST(MINUS,PLUS);
inout MINUS;
inout PLUS;
assign PLUS = MINUS;
endmodule // INST
//Cell Name : RPOLY
module RPOLY(MINUS,PLUS);
inout MINUS;
inout PLUS;
assign MINUS=PLUS;
endmodule //RPOLY
//Cell Name : AMP
module AMP(VP,PVB2,PVB1,VM,VO,VS,GS);
input VP;
input PVB2;
input PVB1;
input VM;
output VO;
input VS;
input GS;
NMOS4 N1 (.D(NOD2),.B(GS),.G(NOD2),.S(GS));
NMOS4 N2 (.D(NOD3),.B(GS),.G(NOD2),.S(GS));
NMOS4 N3 (.D(VO),.B(GS),.G(NOD3),.S(GS));
PMOS4 P1 (.D(NOD4),.B(VS),.G(NOD5),.S(VS));
PMOS4 P2 (.D(NOD2),.B(VS),.G(NOD0),.S(NOD4));
PMOS4 P3 (.D(NOD3),.B(VS),.G(NOD1),.S(NOD4));
PMOS4 P4 (.D(VO),.B(VS),.G(PVB2),.S(VS));
RPOLY R1 (.MINUS (NOD0),.PLUS(VM));
INSTR2(.MINUS(VP),.PLUS(NOD1));
RPOLY R3 (.MINUS(NOD5),.PLUS(PVB1));
endmodule // AMP
To improve accuracy of the digital-to-analog circuit simulation, as shown in fig. 6, as an example, after S104, it may further include:
s601: according to the third Verilog data of the digital-analog circuit, simulation is carried out;
s602: and under the condition that the simulation is failed according to the third Verilog data of the digital-to-analog circuit, jumping to the step S101, and re-checking at least one example of the data flow problem in the real-to-analog circuit until the simulation is successful according to the third Verilog data of the digital-to-analog circuit.
Under the condition that simulation fails according to the third Verilog data of the digital-to-analog circuit, by jumping to the step of simulating the first Verilog data to obtain simulation information, the second simulation can be performed on the Verilog data of the digital-to-analog circuit, and the example with the data flow problem in the second simulation can be checked, so that the simulation accuracy of the digital-to-analog circuit is improved.
The following describes the simulation process of the digital-analog circuit in the above technical solution with an embodiment, as shown in fig. 7, and the steps in the figure are specifically as follows:
s701, modeling a basic unit library;
s702, hierarchically exporting a simulation module Verilog file (namely first Verilog data);
s703, importing simulation software for analysis;
s704, verifying a data flow problem instance (namely a target instance) in the circuit diagram;
s705, adding a marking parameter INST to a problem instance (namely a target instance) to form a marking instance list;
s706, creating an instance Verilog file (namely second Verilog data) for the instance of the marking parameter;
s707, generating a new module Verilog file (namely third Verilog data) by using a Verilog fusion algorithm;
s708, performing simulation.
The above is a specific implementation manner of a digital-analog circuit simulation method provided by the embodiment of the application. Based on the digital-analog circuit simulation method provided by the embodiment, correspondingly, the application also provides a specific implementation mode of the digital-analog circuit simulation device, please refer to the following embodiment.
As shown in fig. 8, an embodiment of the present application provides a digital-analog circuit simulation apparatus 800, which includes:
the simulation module 801 is configured to simulate the first Verilog data of the digital-to-analog circuit to obtain simulation information, where the simulation information is used to indicate that at least one instance of a data flow problem exists in the digital-to-analog circuit;
a marking module 802 for adding a marking parameter to at least one instance having a data flow problem, the marking parameter being used to indicate a type of the at least one instance;
a creation module 803 for creating second Verilog data for at least one instance to which a marking parameter is added;
and an updating module 804, configured to replace a reference relationship of the instance with the marking parameter in the first Verilog data by using a Verilog fusion algorithm based on the second Verilog data and the first Verilog data of the instance with the marking parameter, so as to obtain third Verilog data of the digital-to-analog circuit.
In the digital-analog circuit simulation device 800 provided in the embodiment of the present application, the simulation module 801 simulates the first Verilog data of the digital-analog circuit to obtain at least one instance with a data flow problem, the marking module 802 adds marking parameters to the instance with the data flow problem, and the creating module 803 creates a second Verilog file for the instance with the marking parameters. Update module 804 replaces the reference relationship of the instance with the tagged parameters with the second Verilog data and the first Verilog data of the instance with the tagged parameters using a Verilog fusion algorithm to obtain third Verilog data of the digital-to-analog circuit.
Therefore, by adding the marking parameters to the example with the data flow problem and creating the second Verilog data to the example with the marking parameters, the original data can be prevented from being directly modified, and the risk of introducing new errors is reduced. And updating the first Verilog data according to the second Verilog data with the marked parameter example to obtain third Verilog data of the digital-to-analog circuit, so that the simulation efficiency of the digital-to-analog circuit can be improved.
As another embodiment of the present application, to improve the efficiency of the log-mode circuit simulation, the update module 804 may include:
an adding unit for fusing the second Verilog data with the marked parameter instance into the first Verilog data;
and the updating unit is used for replacing the reference relation between the example with the marking parameters in the first Verilog data and the first model based on the second model in the second Verilog data with the example with the marking parameters to obtain third Verilog data of the digital-to-analog circuit.
As another embodiment of the present application, in order to improve accuracy of the digital-to-analog circuit simulation, the digital-to-analog circuit simulation apparatus 800 may further include:
the second simulation module is used for performing simulation according to third Verilog data of the digital-to-analog circuit;
and the jump module is used for jumping to the step of simulating the first Verilog data to obtain simulation information under the condition that the simulation according to the third Verilog data of the digital-to-analog circuit fails, and rechecking at least one example of the data flow problem in the real-to-analog circuit until the simulation according to the third Verilog data of the digital-to-analog circuit is successful.
As another embodiment of the present application, in order to improve accuracy of the digital-to-analog circuit simulation, the digital-to-analog circuit simulation apparatus 800 may further include:
the summarizing module is used for summarizing the examples with the marking parameters and the marking parameters corresponding to the examples with the marking parameters to generate an example marking parameter table;
accordingly, the update module 804 may be specifically configured to:
and replacing the Verilog data of the examples with the marking parameters in the first Verilog data in batches based on the second Verilog data of the examples with the marking parameters in the example marking parameter table by using a Verilog fusion algorithm to obtain third Verilog data of the digital-to-analog circuit.
Based on the digital-analog circuit simulation method and device provided in the foregoing embodiments, the embodiment of the present application further provides an electronic device 900, as shown in fig. 9:
comprises a processor 901, a memory 902, and a computer program stored in the memory 902 and capable of running on the processor 901, wherein the computer program realizes the processes of the embodiment of the simulation method of the digital-analog circuit when being executed by the processor 901, and can achieve the same technical effect.
In particular, the processor 901 may include a Central Processing Unit (CPU), or an application specific integrated circuit (ASIC, application Specific Integrated Circuit), or may be configured as one or more integrated circuits that implement embodiments of the present application.
Memory 902 may include mass storage for data or instructions. By way of example, and not limitation, the memory 902 may comprise a Hard Disk Drive (HDD), floppy Disk Drive, flash memory, optical Disk, magneto-optical Disk, magnetic tape, or universal serial bus (USB, universal Serial Bus) Drive, or a combination of two or more of the foregoing. The memory 902 may include removable or non-removable (or fixed) media, where appropriate. The memory 902 may be internal or external to the integrated gateway disaster recovery device, where appropriate. In a particular embodiment, the memory 902 is a non-volatile solid state memory.
In particular embodiments, the memory may include Read Only Memory (ROM), random Access Memory (RAM), magnetic disk storage media devices, optical storage media devices, flash memory devices, electrical, optical, or other physical/tangible memory storage devices. Thus, in general, the memory includes one or more tangible (non-transitory) computer-readable storage media (e.g., memory devices) encoded with software comprising computer-executable instructions and when the software is executed (e.g., by one or more processors) it is operable to perform the operations described with reference to a method in accordance with an aspect of the application.
The processor 901 implements any of the digital-analog circuit simulation methods of the above embodiments by reading and executing computer program instructions stored in the memory 902.
In one example, the electronic device may also include a communication interface 903 and a bus 910. As an example, as shown in fig. 9, a processor 901, a memory 902, and a communication interface 903 are connected and communicate with each other through a bus 910.
The communication interface 903 is mainly used to implement communication between each module, device, unit, and/or apparatus in the embodiment of the present application.
Bus 910 includes hardware, software, or both, that couple the components of the online data flow billing device to each other. By way of example, and not limitation, the buses may include an Accelerated Graphics Port (AGP) or other graphics bus, an Enhanced Industry Standard Architecture (EISA) bus, a Front Side Bus (FSB), a HyperTransport (HT) interconnect, an Industry Standard Architecture (ISA) bus, an infiniband interconnect, a Low Pin Count (LPC) bus, a memory bus, a micro channel architecture (MCa) bus, a Peripheral Component Interconnect (PCI) bus, a PCI-Express (PCI-X) bus, a Serial Advanced Technology Attachment (SATA) bus, a video electronics standards association local (VLB) bus, or other suitable bus, or a combination of two or more of the above. Bus 910 may include one or more buses, where appropriate. Although embodiments of the application have been described and illustrated with respect to a particular bus, the application contemplates any suitable bus or interconnect.
The embodiment of the application also provides a computer readable storage medium, on which a computer program is stored, which when executed by a processor, realizes the processes of the above embodiment of the digital-analog circuit simulation method, and can achieve the same technical effects, and in order to avoid repetition, the description is omitted here. Among them, a computer-readable storage medium such as a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), a magnetic disk or an optical disk, and the like.
It should be understood that the application is not limited to the particular arrangements and instrumentality described above and shown in the drawings. For the sake of brevity, a detailed description of known methods is omitted here. In the above embodiments, several specific steps are described and shown as examples. However, the method processes of the present application are not limited to the specific steps described and shown, and those skilled in the art can make various changes, modifications and additions, or change the order between steps, after appreciating the spirit of the present application.
The functional blocks shown in the above block diagrams may be implemented in hardware, software, firmware, or a combination thereof. When implemented in hardware, it may be, for example, an electronic circuit, an Application Specific Integrated Circuit (ASIC), suitable firmware, a plug-in, a function card, or the like. When implemented in software, the elements of the application are the programs or code segments used to perform the required tasks. The program or code segments may be stored in a machine readable medium or transmitted over transmission media or communication links by a data signal carried in a carrier wave. A "machine-readable medium" may include any medium that can store or transfer information. Examples of machine-readable media include electronic circuitry, semiconductor memory devices, ROM, flash memory, erasable ROM (EROM), floppy disks, CD-ROMs, optical disks, hard disks, fiber optic media, radio Frequency (RF) links, and the like. The code segments may be downloaded via computer networks such as the internet, intranets, etc.
It should also be noted that the exemplary embodiments mentioned in this disclosure describe some methods or systems based on a series of steps or devices. However, the present application is not limited to the order of the above-described steps, that is, the steps may be performed in the order mentioned in the embodiments, or may be performed in a different order from the order in the embodiments, or several steps may be performed simultaneously.
Aspects of the present application are described above with reference to flowchart illustrations and/or block diagrams of methods, apparatus and computer program products according to embodiments of the application. It will be understood that each block of the flowchart illustrations and/or block diagrams, and combinations of blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, enable the implementation of the functions/acts specified in the flowchart and/or block diagram block or blocks. Such a processor may be, but is not limited to being, a general purpose processor, a special purpose processor, an application specific processor, or a field programmable logic circuit. It will also be understood that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware which performs the specified functions or acts, or combinations of special purpose hardware and computer instructions.
In the foregoing, only the specific embodiments of the present application are described, and it will be clearly understood by those skilled in the art that, for convenience and brevity of description, the specific working processes of the systems, modules and units described above may refer to the corresponding processes in the foregoing method embodiments, which are not repeated herein. It should be understood that the scope of the present application is not limited thereto, and any equivalent modifications or substitutions can be easily made by those skilled in the art within the technical scope of the present application, and they should be included in the scope of the present application.
Claims (7)
1. A digital-to-analog circuit simulation method, comprising:
under the condition that first Verilog data of a digital-to-analog circuit are obtained, simulating the first Verilog data to obtain simulation information, wherein the first Verilog data comprise a first model corresponding to each instance and a reference relation of each instance, the reference relation comprises the reference relation between each instance and the first model, and the simulation information is used for indicating at least one instance with a data flow problem in the digital-to-analog circuit;
adding a marking parameter to at least one instance of the existing data flow problem, wherein the marking parameter is used for indicating the type of the at least one instance;
creating second Verilog data for at least one instance added with the marking parameters, wherein the second Verilog data comprises a second model corresponding to the instance with the marking parameters;
and replacing a reference relation of the instance with the marking parameter in the first Verilog data based on the second Verilog data of the instance with the marking parameter and the first Verilog data by using a Verilog fusion algorithm to obtain third Verilog data of the digital-to-analog circuit.
2. The method of claim 1, wherein the step of determining the position of the substrate comprises,
the replacing, by using a Verilog fusion algorithm, a reference relation of an instance with a marking parameter in the first Verilog data based on the second Verilog data and the first Verilog data of the instance with the marking parameter to obtain third Verilog data of the digital-to-analog circuit, including:
fusing second Verilog data of the marked parameter instance into the first Verilog data;
and replacing a reference relation between the marked parameter instance and the first model in the first Verilog data based on a second model in the second Verilog data of the marked parameter instance to obtain third Verilog data of the digital-to-analog circuit.
3. The method of claim 1, wherein replacing the reference relationship of the marked instances in the first Verilog data with the Verilog fusion algorithm based on the second Verilog data of the marked instances and the first Verilog data to obtain the third Verilog data of the digital-to-analog circuit further comprises:
performing simulation according to third Verilog data of the digital-analog circuit;
and under the condition that the simulation according to the third Verilog data of the digital-to-analog circuit fails, jumping to the step of simulating the first Verilog data to obtain simulation information, and re-verifying at least one example of the data flow problem in the digital-to-analog circuit until the simulation according to the third Verilog data of the digital-to-analog circuit succeeds.
4. A method according to any one of claims 1-3, wherein said adding a marking parameter to said at least one instance of a data flow problem further comprises:
summarizing the examples of the marked parameters and the marked parameters corresponding to the examples of the marked parameters to generate an example marked parameter table;
the replacing, by using a Verilog fusion algorithm, a reference relation of an instance with a marking parameter in the first Verilog data based on the second Verilog data and the first Verilog data of the instance with the marking parameter to obtain third Verilog data of the digital-to-analog circuit, including:
and replacing the Verilog data of the example with the marking parameters in the first Verilog data in batches based on the second Verilog data of the example with the marking parameters in the example marking parameter table by using a Verilog fusion algorithm to obtain third Verilog data of the digital-to-analog circuit.
5. A digital-to-analog circuit simulation apparatus, comprising:
the simulation module is used for simulating the first Verilog data of the digital-to-analog circuit to obtain simulation information under the condition that the first Verilog data of the digital-to-analog circuit are obtained, the first Verilog data comprise a first model corresponding to each instance and a reference relation of each instance, the reference relation comprises the reference relation between each instance and the first model, and the simulation information is used for indicating at least one instance with a data flow problem in the digital-to-analog circuit;
a marking module for adding marking parameters to at least one instance with a data flow problem, wherein the marking parameters are used for indicating the type of the at least one instance;
the creation module is used for creating second Verilog data for at least one instance added with the marking parameters, wherein the second Verilog data comprises a second model corresponding to the instance with the marking parameters;
and the updating module is used for replacing the reference relation of the example with the marking parameter in the first Verilog data based on the second Verilog data of the example with the marking parameter and the first Verilog data by using a Verilog fusion algorithm to obtain third Verilog data of the digital-to-analog circuit.
6. An electronic device, the device comprising: a processor and a memory storing computer program instructions;
the processor, when executing the computer program instructions, implements a digital-to-analog circuit emulation method as claimed in any one of claims 1-4.
7. A computer readable storage medium, wherein computer program instructions are stored on the computer readable storage medium, which when executed by a processor, implement the digital-to-analog circuit emulation method according to any one of claims 1-4.
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