CN117892664A - SoC mixed signal verification device and verification method - Google Patents
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Abstract
The invention provides a device and a method for verifying SoC mixed signals, wherein the device comprises: an instance interface module for receiving SoC design file input and outputting the hierarchy and interface information of all instances; the analog IP instance interface expansion module receives the input of the analog IP name list and outputs the layer-level instance names of all analog IPs and all interface signals thereof in the SoC design; the equivalent signal module outputs all equivalent signals listed according to the analog IP instance interface; the analog IP interface filtering module filters out the signal output belonging to the analog IP instance interface; and the formatting output module outputs all instances of all analog IPs and all interfaces thereof, and marks other equivalent analog IP instance interface signals and equivalent digital interface signals and whether the interfaces are designed for floating the input end or not for each interface. The invention can find out the problems of floating of the analog IP input end, effectiveness of all the wires related to the key signals and the like in time before the mixed signal simulation, thereby improving the mixed signal verification efficiency.
Description
Technical Field
The invention relates to the technical field of integrated circuits, in particular to a system on chip (SoC) mixed signal verification device and a verification method.
Background
Currently, most socs (System on Chip) are mixed signal designs, and mixed signal verification is an important ring of SoC development. According to analog IP (Intellectual Property, also called IP core, generally refers to a chip with specific functions, which is developed by others and has intellectual property rights, a developer can continuously develop a model used by a larger, more complete and more specific chip facing a specific application scene on the basis of the specific chip, and mixed signal verification can be classified into behavior-level model mixed signal verification and netlist-level mixed signal verification. Behavior-level model-mix verification is performed in the form of RTL (Register Transfer Level, register transfer level, also known as register transfer hierarchy) +behavior model, while netlist-level-mix verification is based on rtl+spice (Simulation program with integrated circuit emphasis, simulation circuit simulator) netlist. Behavior-level models may lack complete functionality and port description as abstract behavior descriptions for analog circuits, with the advantage of not high performance requirements on the simulator. The netlist is used as a direct embodiment of an analog circuit, and can be applied to SoC simulation to reduce the dependence of verification quality on behavior-level model abstraction work, and meanwhile, the function and performance of the simulator are supported.
The behavioral level model is typically defined by the user based on an understanding of the schematic, or generated from the schematic using EDA (Electronic design automation ) tools. Errors in the behavior model functions defined by the user can reduce the efficiency of verification, and if the schematic diagram is incorrect and the behavior model omits critical information in the abstract process, problems can be left undiscovered. The behavior model generated by the schematic diagram has the problems of high complexity and long error correction period.
The simulation IP adopts the form of the netlist, so that the problems caused by the behavior level model can be effectively avoided in the mixed signal verification, the abstract process of the schematic diagram is omitted, the influence of human factors related to the model on the verification quality is avoided, the update and synchronization of the model and the schematic diagram are not required to be additionally maintained, and the reasons of the problems related to the simulation IP can be rapidly positioned without going through the behavior level model. The introduction of the netlist also puts new requirements on the simulator, simulation environment configuration and server performance. The simulation time becomes long, resulting in a longer period of finding problems and correcting errors, and the regression-test time becomes costly. In addition, it is necessary to configure an analog simulator in the simulation environment and define a digital-analog signal interface, etc.
At present, netlist-level mixed signal verification has high dependence on EDA tools, is complicated in configuration of a logarithmic mode signal interface, and needs to check whether the configuration is correct or not through simulation, so that the period for obtaining the correct configuration is long, and is particularly remarkable in multi-voltage domain design. In complex mixed signal designs, multiple iterations of verification and design are required to obtain the correct digital-to-analog port configuration due to critical errors associated with the mixed signal IP by the SoC. Furthermore, EDA tools lack a mechanism for checking the validity of the analog signal interface connection, such as not supporting the checking of analog input floating designs, where simulation has found that problems caused by floating designs are less efficient and are also prone to error. For some connections between analog IPs that require centralized inspection, such as voltage domain inspection from other analog IP signals on an analog test bus, there is a lack of quick, intuitive, and efficient tools.
At present, the mixed signal verification field does not have a quick and effective tool for checking the digital-analog signal interface, and the traditional simulation tool can bring the problem of the mixed signal interface into simulation, and because the mixed signal simulation time is long, the period of finding the problem through simulation is long and the efficiency is low.
Disclosure of Invention
The invention aims to provide a system-on-chip (SoC) mixed signal verification device and a mixed signal verification method, which can be used for rapidly checking the validity of analog signal connection in mixed signal verification.
In order to achieve the above purpose, the present invention provides the following technical scheme:
the invention provides a mixed signal verification device of SoC, comprising:
the instance interface module receives the input of the SoC design file, analyzes the SoC design file and outputs the hierarchy and interface information of all instances;
the analog IP instance interface expansion module receives analog IP name list input, is connected with the output end of the instance interface module, receives the hierarchy and interface information of all instances output by the instance interface module, and outputs the layer level instance names of all analog IPs and all interface signals thereof in SoC design;
the equivalent signal module receives the input of the analog IP name list, is connected with the output end of the analog IP instance interface expansion module, receives the belt-level instance names of all analog IPs and all interface signals thereof output by the analog IP instance interface expansion module, and outputs all equivalent signals listed according to the analog IP instance interface, wherein the equivalent signals are a plurality of signals with different names which are directly connected through the interfaces of the instances without any logic;
the analog IP interface filtering module is connected with the output ends of the analog IP instance interface expansion module and the equivalent signal module, receives all the layer-level instance names of the analog IP in the SoC design output by the analog IP instance interface expansion module, all interface signals of the analog IP in the SoC design output by the analog IP instance interface expansion module and the equivalent signal input output by the equivalent signal module, and filters out the signal output belonging to the analog IP instance interface in all equivalent signal sets for analyzing the connection of key analog signal lines;
the formatting output module is connected with the output ends of the analog IP instance interface expansion module and the analog IP interface filtering module, receives the tape layer level instance names of all analog IPs in the SoC design output by the analog IP instance interface expansion module and all interface signals thereof, and the signal input belonging to the analog IP instance interface output by the analog IP interface filtering module, outputs all instances of all analog IPs and all interfaces thereof, and marks other equivalent analog IP instance interface signals and equivalent digital interface signals for each interface and whether the interface is an input end floating design.
In an embodiment, the instance interface module is a third party open source tool or custom script.
In an embodiment, the SoC design file includes all RTLs and analog circuit null models, and interface information in the analog circuit null models is kept consistent with a spice netlist, including signal bus width and signal direction; the interface information of all the examples output by the example interface module comprises interface names, interface directions and signal bus widths.
In an embodiment, the analog IP name list contains the module names of all analog IPs used in the SoC, either provided by the SoC design or grabbed from the SoC design by custom scripts.
In one embodiment, the equivalent signals are a plurality of signals with different names directly connected through an interface of an example without any logic, and the signals comprise a digital interface signal and an analog interface signal.
In an embodiment, the formatted output module outputs all instances of all analog IPs and all interfaces thereof, for each interface, labels other equivalent analog IP instance interface signals and equivalent digital interface signals and whether the interface is an input float design, is formatted classified summary information, uses analog IPs as major classes and uses analog IPs as sheet names of EXCEL tables, lists all interfaces of all instances of the analog IPs in each major class, and for each interface, labels other equivalent analog IP instance interface signals and equivalent digital interface signals and whether the interface is an input float design.
In an embodiment, the instance interface module, the analog IP instance interface extension module, the equivalent signal module, the analog IP interface filtering module, and the formatted output module are all implemented in a programming language.
The invention also provides a method for verifying the SoC mixed signal, which adopts the device for verifying the SoC mixed signal, and comprises the following steps:
the instance interface module receives the input of the SoC design file, analyzes the SoC design file and outputs the hierarchy and interface information of all instances;
the analog IP instance interface expansion module receives analog IP name list input, is connected with the output end of the instance interface module, receives the hierarchy and interface information of all instances output by the instance interface module, and outputs the layer level instance names of all analog IPs and all interface signals thereof in SoC design;
the equivalent signal module receives the input of the analog IP name list, is connected with the output end of the analog IP instance interface expansion module, receives the belt-level instance names of all analog IPs and all interface signals thereof output by the analog IP instance interface expansion module, and outputs all equivalent signals listed according to the analog IP instance interface, wherein the equivalent signals are a plurality of signals with different names which are directly connected through the interfaces of the instances without any logic;
the analog IP interface filtering module is connected with the output ends of the analog IP instance interface expansion module and the equivalent signal module, receives all the layer level instance names of the analog IP in the SoC design output by the analog IP instance interface expansion module, all interface signals of the analog IP and equivalent signal input output by the equivalent signal module, and filters out signal output belonging to the analog IP instance interface in all equivalent signal sets for analyzing the connection of key analog signal lines;
the formatted output module is connected with the output ends of the analog IP instance interface expansion module and the analog IP interface filtering module, receives the tape layer level instance names of all analog IPs in the SoC design output by the analog IP instance interface expansion module and all interface signals thereof, and the signal input belonging to the analog IP instance interface output by the analog IP interface filtering module, outputs all instances of all analog IPs and all interfaces thereof, and marks other equivalent analog IP instance interface signals and equivalent digital interface signals for each interface and whether the interface is an input end floating design.
In an embodiment, the analog IP instance interface extension module combines the analog IP name list and the hierarchy and interface information of all the instances output by the instance interface module, and obtains the layer level instance names of all the analog IPs in the SoC design and all the interface signals thereof through a searching manner.
In an embodiment, the equivalent signal module searches all interface signals output by the analog IP instance interface expansion module in the SoC design file to find all interface signals of other instances directly connected to the interface, so as to form the equivalent signal.
In an embodiment, the equivalent signal module further performs a deduplication process on the equivalent signal.
In an embodiment, the formatted output module classifies the analog IP instances and lists the interfaces of all the instances according to the analog IP instances in the form of a table or a log file, marks other equivalent analog IP instance interface signals and equivalent digital interface signals, then analyzes the analog IP instance interface signals without equivalent signals, reports the input ends of the floating analog IP instances according to the signal direction, generates formatted classified summary information, lists all the interfaces of all the instances of the analog IP in each large class by using the analog IP name as the sheet name of the EXCEL table, and marks other equivalent analog IP instance interface signals and equivalent digital interface signals for each interface and whether the interfaces are designed with floating input ends.
Compared with the prior art, the technical scheme of the invention has the following beneficial effects:
the invention discloses a system-on-chip (SoC) mixed signal verification device and a verification method, which aim to solve the problem of checking the connectivity of analog signals in mixed signal verification, and can timely discover the problems of floating of an analog IP input end, effectiveness of all wires related to key signals and the like before mixed signal simulation based on a SoC design file and an analog IP name list through static analysis before simulation, so that the mixed signal verification efficiency is improved. A class generalized inspection report is output that can directly give all analog IP instance input floating analog interfaces, and all connections for critical analog signals, such as analog test buses and power supply connections for different voltage domains.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the description of the embodiments will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic structural diagram of a SoC mixed signal verification device according to a first embodiment of the present invention.
Detailed Description
The following description of the technical solutions in the embodiments of the present invention will be clear and complete, and it is obvious that the described embodiments are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to fall within the scope of the invention.
The technical scheme of the invention provides a verification device and a verification method for SoC mixed signals, and the verification device and the verification method are described in detail below. It should be noted that the following description order of the embodiments is not intended to limit the preferred order of the embodiments of the present invention. In the following embodiments, the descriptions of the embodiments are focused on, and for the part that is not described in detail in a certain embodiment, reference may be made to the related descriptions of other embodiments.
Referring to fig. 1, a device for verifying a SoC mixed signal according to a first embodiment of the present invention includes:
an instance interface module (GMIO) receives the input of the SoC design file, analyzes the SoC design file and outputs the hierarchy and interface information of all instances;
an analog IP instance interface expansion module (EAIP), which receives analog IP name list input, is connected with the output end of the instance interface module, receives the hierarchy and interface information of all instances output by the instance interface module, and outputs the layer level instance names of all analog IPs and all interface signals thereof in SoC design;
an equivalent signal module (GES) which receives the input of the analog IP name list, is connected with the output end of the analog IP instance interface expansion module, receives the layer level instance names of all analog IPs and all interface signals thereof output by the analog IP instance interface expansion module, and outputs all equivalent signals listed according to the analog IP instance interface, wherein the equivalent signals are a plurality of signals which are directly connected with different names through the interfaces of the instance without any logic;
the analog IP interface filtering module (FAES) is connected with the output ends of the analog IP instance interface expansion module and the equivalent signal module, receives all the layer level instance names of all analog IPs in the SoC design output by the analog IP instance interface expansion module, all interface signals thereof and equivalent signal input output by the equivalent signal module, and filters out signal output belonging to the analog IP instance interface in all equivalent signal sets for analyzing the connection of key analog signal lines;
and the formatting output module (M & F) is connected with the output ends of the analog IP instance interface expansion module and the analog IP interface filtering module, receives the tape layer level instance names and all interface signals of all analog IPs in the SoC design output by the analog IP instance interface expansion module and the signal input belonging to the analog IP instance interface output by the analog IP interface filtering module, outputs all instances of all analog IPs and all interfaces thereof, and marks other equivalent analog IP instance interface signals and equivalent digital interface signals for each interface and whether the interface is an input end floating design.
In an embodiment, the instance interface module is a third party open source tool or a custom script. In one embodiment, the example interface module may be implemented in a programming language, and in one embodiment is implemented based on python code.
In an embodiment, the SoC design file includes all RTLs and analog circuit null models, and interface information in the analog circuit null models is kept consistent with a spice netlist, including signal bus width and signal direction; the interface information of all the examples output by the example interface module comprises interface names, interface directions and signal bus widths.
In an embodiment, the analog IP name list contains the module names of all analog IPs used in the SoC, either provided by the SoC design or grabbed from the SoC design by custom scripts.
In an embodiment, the analog IP instance interface extension module combines the analog IP name list and the hierarchy and interface information of all the instances output by the instance interface module, and obtains the layer level instance names of all the analog IPs in the SoC design and all the interface signals thereof through a searching manner. In one embodiment, the analog IP instance interface extension module may be implemented in a programming language, and in one embodiment is implemented based on python code.
In an embodiment, the equivalent signal module searches all interface signals output by the analog IP instance interface expansion module in the SoC design file to find all interface signals of other instances directly connected to the interface, including digital interface signals and analog interface signals, to form the equivalent signal. In one embodiment, the equivalent signal module may be implemented in a programming language, and in one embodiment is implemented based on python code.
In one embodiment, the analog IP interface filtering module filters out signals belonging to an analog IP interface for analyzing all connections of critical analog signals, such as analog test buses and power supply connections of different voltage domains. In one embodiment, the analog IP interface filtering module may be implemented in a programming language, and in one embodiment, is implemented based on Python code.
In an embodiment, the formatted output module classifies the analog IP instances and lists the interfaces of all the instances according to the analog IP instances in the form of a table or a log file, marks other equivalent analog IP instance interface signals and equivalent digital interface signals, then analyzes the analog IP instance interface signals without equivalent signals, reports the input ends of the floating analog IP instances according to the signal direction, generates formatted classified summary information, lists all the interfaces of all the instances of the analog IP in each large class by using the analog IP name as the sheet name of the EXCEL table, marks other equivalent analog IP instance interface signals and equivalent digital interface signals for each interface, and whether the interfaces are designed with floating input ends, namely, checks the report. In one embodiment, the formatted output module may be implemented in a programming language, and in one embodiment is implemented based on python code.
The second embodiment of the present invention provides a method for verifying a SoC mixed signal, using the SoC mixed signal verification apparatus as described above, the method comprising:
the instance interface module receives the input of the SoC design file, analyzes the SoC design file and outputs the hierarchy and interface information of all instances;
the analog IP instance interface expansion module receives analog IP name list input, is connected with the output end of the instance interface module, receives the hierarchy and interface information of all instances output by the instance interface module, and outputs the layer level instance names of all analog IPs and all interface signals thereof in SoC design;
the equivalent signal module receives the input of the analog IP name list, is connected with the output end of the analog IP instance interface expansion module, receives the belt-level instance names of all analog IPs and all interface signals thereof output by the analog IP instance interface expansion module, and outputs all equivalent signals listed according to the analog IP instance interface, wherein the equivalent signals are a plurality of signals with different names which are directly connected through the interfaces of the instances without any logic;
the analog IP interface filtering module is connected with the output ends of the analog IP instance interface expansion module and the equivalent signal module, receives all the layer level instance names of the analog IP in the SoC design output by the analog IP instance interface expansion module, all interface signals of the analog IP and equivalent signal input output by the equivalent signal module, and filters out signal output belonging to the analog IP instance interface in all equivalent signal sets for analyzing the connection of key analog signal lines;
the formatted output module is connected with the output ends of the analog IP instance interface expansion module and the analog IP interface filtering module, receives the tape layer level instance names of all analog IPs in the SoC design output by the analog IP instance interface expansion module and all interface signals thereof, and the signal input belonging to the analog IP instance interface output by the analog IP interface filtering module, outputs all instances of all analog IPs and all interfaces thereof, and marks other equivalent analog IP instance interface signals and equivalent digital interface signals for each interface and whether the interface is an input end floating design.
Accordingly, as described above, in one embodiment, the analog IP instance interface extension module combines the analog IP name list and the hierarchy and interface information of all the instances output by the instance interface module, and obtains the layer level instance names of all the analog IPs in the SoC design and all the interface signals thereof through a search method.
In an embodiment, the equivalent signal module searches all interface signals output by the analog IP instance interface expansion module in the SoC design file to find all interface signals of other instances directly connected to the interface, so as to form the equivalent signal.
In one embodiment, the equivalent signal module further performs a deduplication process on the equivalent signal, since the output of the analog IP instance interface expansion module may itself include the equivalent signal.
In an embodiment, the formatted output module classifies the analog IP instances and lists the interfaces of all the instances according to the analog IP instances in the form of a table or a log file, marks other equivalent analog IP instance interface signals and equivalent digital interface signals, then analyzes the analog IP instance interface signals without equivalent signals, reports the input ends of the floating analog IP instances according to the signal direction, generates formatted classified summary information, lists all the interfaces of all the instances of the analog IP in each large class by using the analog IP name as the sheet name of the EXCEL table, marks other equivalent analog IP instance interface signals and equivalent digital interface signals for each interface, and whether the interfaces are designed with floating input ends, namely, checks the report.
Compared with the prior art, the technical scheme of the invention has the following beneficial effects:
the invention discloses a system-on-chip (SoC) mixed signal verification device and a verification method, which aim to solve the problem of checking the connectivity of analog signals in mixed signal verification, and can timely discover the problems of floating of an analog IP input end, effectiveness of all wires related to key signals and the like before mixed signal simulation based on a SoC design file and an analog IP name list through static analysis before simulation, so that the mixed signal verification efficiency is improved. A class generalized inspection report is output that can directly give all analog IP instance input floating analog interfaces, and all connections for critical analog signals, such as analog test buses and power supply connections for different voltage domains.
The foregoing is merely illustrative of the present invention, and the present invention is not limited thereto, and any person skilled in the art will readily recognize that variations or substitutions are within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims. Furthermore, the foregoing description of the principles and embodiments of the invention has been provided for the purpose of illustrating the principles and embodiments of the invention and for the purpose of providing a further understanding of the principles and embodiments of the invention, and is not to be construed as limiting the invention.
Claims (12)
1. An SoC hybrid signal verification apparatus, characterized in that the SoC hybrid signal verification apparatus includes:
the instance interface module receives the input of the SoC design file, analyzes the SoC design file and outputs the hierarchy and interface information of all instances;
the analog IP instance interface expansion module receives analog IP name list input, is connected with the output end of the instance interface module, receives the hierarchy and interface information of all instances output by the instance interface module, and outputs the layer level instance names of all analog IPs and all interface signals thereof in SoC design;
the equivalent signal module receives the input of the analog IP name list, is connected with the output end of the analog IP instance interface expansion module, receives the belt-level instance names of all analog IPs and all interface signals thereof output by the analog IP instance interface expansion module, and outputs all equivalent signals listed according to the analog IP instance interface, wherein the equivalent signals are a plurality of signals with different names which are directly connected through the interfaces of the instances without any logic;
the analog IP interface filtering module is connected with the output ends of the analog IP instance interface expansion module and the equivalent signal module, receives all the layer-level instance names of the analog IP in the SoC design output by the analog IP instance interface expansion module, all interface signals of the analog IP in the SoC design output by the analog IP instance interface expansion module and the equivalent signal input output by the equivalent signal module, and filters out the signal output belonging to the analog IP instance interface in all equivalent signal sets for analyzing the connection of key analog signal lines;
the formatting output module is connected with the output ends of the analog IP instance interface expansion module and the analog IP interface filtering module, receives the tape layer level instance names of all analog IPs in the SoC design output by the analog IP instance interface expansion module and all interface signals thereof, and the signal input belonging to the analog IP instance interface output by the analog IP interface filtering module, outputs all instances of all analog IPs and all interfaces thereof, and marks other equivalent analog IP instance interface signals and equivalent digital interface signals for each interface and whether the interface is an input end floating design.
2. The SoC mixed-signal authentication apparatus of claim 1, wherein the instance interface module is a third party open source tool or a custom script.
3. The SoC mixed signal verification device of claim 1, wherein the SoC design file includes all RTLs and analog circuit null models, interface information in the analog circuit null models is consistent with a spice netlist, and the interface information includes signal bus width and signal direction; the interface information of all the examples output by the example interface module comprises interface names, interface directions and signal bus widths.
4. The SoC mixed signal verification device of claim 1, wherein the analog IP name list contains module names of all analog IPs used in the SoC, provided by the SoC design or grabbed from the SoC design by custom scripts.
5. The SoC mixed signal authentication apparatus of claim 1, wherein the equivalent signals are a plurality of signals having different names directly connected through an interface of an instance without any logic, including a digital interface signal and an analog interface signal.
6. The SoC hybrid signal verification device of claim 1, wherein the formatted output module outputs all instances of all analog IPs and all interfaces thereof, and for each interface, labels other equivalent analog IP instance interface signals and equivalent digital interface signals and whether the interface is an input float design,
the method is characterized in that the method is formatted classified summary information, analog IP is taken as a major class, the analog IP name is taken as the sheet name of an EXCEL table, all interfaces of all examples of the analog IP are listed in each major class, and for each interface, other equivalent analog IP example interface signals and equivalent digital interface signals are marked and whether the interface is designed for input end float.
7. The SoC hybrid signal authentication apparatus of claim 1, wherein the instance interface module, analog IP instance interface extension module, equivalent signal module, analog IP interface filter module, formatted output module,
are all implemented in a programming language.
8. A SoC mixed signal authentication method, characterized in that the SoC mixed signal authentication apparatus according to any one of claims 1 to 7 is employed, the authentication method comprising:
the instance interface module receives the input of the SoC design file, analyzes the SoC design file and outputs the hierarchy and interface information of all instances;
the analog IP instance interface expansion module receives analog IP name list input, is connected with the output end of the instance interface module, receives the hierarchy and interface information of all instances output by the instance interface module, and outputs the layer level instance names of all analog IPs and all interface signals thereof in SoC design;
the equivalent signal module receives the input of the analog IP name list, is connected with the output end of the analog IP instance interface expansion module, receives the belt-level instance names of all analog IPs and all interface signals thereof output by the analog IP instance interface expansion module, and outputs all equivalent signals listed according to the analog IP instance interface, wherein the equivalent signals are a plurality of signals with different names which are directly connected through the interfaces of the instances without any logic;
the analog IP interface filtering module is connected with the output ends of the analog IP instance interface expansion module and the equivalent signal module, receives all the layer level instance names of the analog IP in the SoC design output by the analog IP instance interface expansion module, all interface signals of the analog IP and equivalent signal input output by the equivalent signal module, and filters out signal output belonging to the analog IP instance interface in all equivalent signal sets for analyzing the connection of key analog signal lines;
the formatted output module is connected with the output ends of the analog IP instance interface expansion module and the analog IP interface filtering module, receives the tape layer level instance names of all analog IPs in the SoC design output by the analog IP instance interface expansion module and all interface signals thereof, and the signal input belonging to the analog IP instance interface output by the analog IP interface filtering module, outputs all instances of all analog IPs and all interfaces thereof, and marks other equivalent analog IP instance interface signals and equivalent digital interface signals for each interface and whether the interface is an input end floating design.
9. The SoC mixed signal verification method of claim 8, wherein the analog IP instance interface extension module combines the analog IP name list and the hierarchy and interface information of all instances output by the instance interface module, and obtains the tape layer level instance names of all analog IPs in the SoC design and all interface signal outputs thereof by means of a search.
10. The SoC mixed signal verification method of claim 8, wherein the equivalent signal module searches the SoC design file for all interface signals output by the analog IP instance interface expansion module, and finds all interface signals of other instances directly connected to the interface, to form the equivalent signal.
11. The SoC hybrid signal verification method of claim 8, wherein the equivalent signal module further performs a de-duplication process on the equivalent signal.
12. The SoC hybrid signal verification method of claim 8, wherein the formatted output module classifies and lists interfaces of all instances according to the instances of the analog IP in the form of a table or log file, labels other equivalent analog IP instance interface signals and equivalent digital interface signals, then analyzes the analog IP instance interface signals without equivalent signals, reports the input of the floating analog IP instance according to the signal direction, generates formatted classified summary information, lists all interfaces of all instances of the analog IP in each of the large classes with analog IP as a large class and with analog IP names as a sheet name of an EXCEL table, labels other equivalent analog IP instance interface signals and equivalent digital interface signals for each interface, and whether the interfaces are of a floating design for the input.
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