RU2115952C1 - Information search engine - Google Patents

Abstract

FIELD: electric communication, in particular, for identification of TFTP communication protocol used in digital communication systems. SUBSTANCE: device has frequency divider 1, subtraction counter 3, commutator 4 which provide connection of input signal to different circuits of logical units. Memory unit 2 serves for storage of one packet of protocol under investigation. First selection unit 5 performs preliminary selection of input digital flow into packet bytes with code of operation. Second to fourth selection units 6-8 perform selection of packet structure in packet flow. Search strategy register 9 checks compliance of order of arrival of packets of digital flow under investigation with requirements of information exchange. Time interval generator 10 provides detection of moment when connection is closed. When signal passes through specific circuits of logical units, indication unit 11 generates information messages about search results. EFFECT: real-time operations, increased validity of search, zero probability of miss (in case of a priori information about protocol), simplified design and modification for arbitrary interface protocol. 8 cl, 11 dwg

Description

 The invention relates to telecommunications and can be used to search for information and operational identification used in digital communication systems and, in particular, in a data transmission network (SPD) such as the Internet Protocol TFTP (Trivial File Transfer Protocol), belonging to the family of known DARPA procedures ( Information Computer Network Protocols, Handbook, Edited by I.A. Mizin, A.P. Kuleshov, Moscow: Radio and Communications, 1990, p. 503), standardized by the US Department of Defense.

 A well-known analogue of the proposed device is described in the copyright certificate of the USSR N 1621049, class. G 06 F 15/40, 09.01.89 and contains boundary registers that add up and subtract counters, comparison schemes, memory blocks, calculation blocks and a number of other elements that allow you to search for information.

 In the course of fulfilling the task of receiving and searching digital message streams, it is necessary to determine the parameters of the digital stream by which information is searched, packets are identified, and the frame transmission sequence matches the data exchange rules established for this protocol, and the well-known analogue does not fulfill these requirements - the definition of communication packets implemented in it with the probability of correct recognition is much less than 0.1, since recognition is carried out in a statistical way, and each with Communication is unique in its own way and does not take into account the signs of the sequence of information transfer (exchange rules).

 The nearest information retrieval device (prototype) to the proposed one is described in the USSR copyright certificate N 1711185, class. G 06 F 15/40, 04/05/89. The indicated invention describes an information search device comprising upper and lower bound registers, an adder-calculator, a search strategy register, subtracting and adding up counters, comparison circuits, a memory block, a key register, an output register, a group of AND and OR elements, a trigger, a trigger input , inputs of addresses of the upper and lower boundaries, the input of the code of the criterion for changing the search strategy, the key input, the output of the address, the output of the sign of lack of information and the pulse distributor.

 The disadvantage of this device is the impossibility of obtaining an unambiguous solution due to the low level of reliability and probability of identification (the probability of identifying the parameters of the digital stream and the identification of the communication protocol is less than 0.3), since the prototype searches for information blocks in the array using the dichotomous method without taking into account the presence of a large number types of possible packages and their valid sequence.

 The aim of the invention is the development of a device for searching for information on a digital stream with finite a priori uncertainty regarding its parameters, which provides increased reliability of the search, identification of information by obtaining an unambiguous decision on whether this digital stream is a TFTP protocol digital stream.

 The goal is achieved by the fact that in the known information retrieval device containing a memory unit, a search strategy register and a subtracting counter, the following elements are additionally introduced: a frequency divider, a switch, a first, second, third and fourth selection unit, a time interval generator and an indication unit. The output of the frequency divider is connected to the first inputs of the memory block, subtracting the counter, the first, second, third and fourth blocks of selection, the search strategy register. The outputs of the memory block are connected respectively to the fourth to eleventh inputs of the switch, and the first output of the subtracting counter is connected to the tenth input of the memory block, the twelfth input of the switch, the eleventh input of the first selection block, the tenth inputs of the second, third, and fourth selection blocks, the third input of the search strategy register and is the command output of the device. The second output of the subtracting counter is connected to the eleventh inputs of the second, third and fourth selection blocks, and the third output of the subtracting counter is connected to the twelfth input of the first selection block. The outputs of the switch are connected to the second and ninth inputs of the first, second, third and fourth blocks of selection, respectively, and the first and second outputs of the first block of selection are connected respectively to the first and second inputs of the switch. The third output of the first selection block is connected to the fourth input of the search strategy register and the fourteenth input of the subtracting counter, and the fourth output of the first selection block is connected to the fifth input of the search strategy register, the fourteenth input of the subtracting counter and the input of the time interval shaper. The fifth output of the first selection block is connected to the third input of the switch. The sixth output of the first selection block and the first outputs of the second, third and fourth selection blocks, the output of the search strategy register are connected to the first input of the display unit, the tenth input of the first selection block and the fourteenth input of the subtracting counter. The second output of the second selection block is connected to the second input of the search strategy register, and the second output of the third selection block is connected to the third input of the search strategy register. In this case, the second output of the fourth selection block and the output of the shaper of the time intervals are connected to the second input of the display unit and the fourteenth input of the subtracting counter. The input of the frequency divider, the second - the ninth inputs of the memory block and the second - thirteenth inputs of the subtracting counter are respectively the clock frequency input, signal and information inputs of the device.

 The memory block contains an inverter, the first and second totalizing counters, a switch, an element And, a differentiating circuit and RAM. The outputs of the first and second totalizing counters are connected to the corresponding inputs of random access memory (RAM), the other inputs of which are connected to the corresponding inputs of the switch. In this case, the outputs of the first totalizing counter through the And element are connected to one of the inputs of the second totalizing counter, the other input of which is connected to the corresponding input of the first totalizing counter and to the output of the differentiating circuit. The input of the differentiating circuit is connected to the corresponding input of the switch and RAM, to the input of the inverter, the output of which is connected to the corresponding input of the switch. The other input of the first totalizing counter, the other inputs of the switch and the input of the inverter are the corresponding inputs of the memory block, the outputs of which are the corresponding outputs of the switch.

 The switch contains the first, second, third and fourth triggers, the first, second, third and fourth buffer elements. One of the inputs of the first, second, third and fourth triggers is the corresponding inputs of the switch, and the other inputs are connected to the corresponding inputs of the switch. The output of the first, second, third, and fourth triggers is connected to one of the inputs of the first, second, third, and fourth buffer elements, respectively; other inputs of which are the corresponding inputs of the switch, and their outputs are the corresponding outputs of the switch.

 The first selection block contains the first, second and third delay lines, the first, second and third switches of the first, second, third and fourth decoders, element I. One of the inputs of the first, second, third and fourth decoders is the corresponding input of the first selection block. Other inputs of the first and second decoders are connected to the corresponding outputs of the second switch, and other inputs of the third and fourth decoders are connected to the corresponding outputs of the third switch. In this case, one of the outputs of the first decoder through the second delay line is connected to the corresponding input of the second switch. The input of the first delay line is connected to the corresponding outputs of the second decoder, which are the corresponding outputs of the first block of selection, and the output of the first delay line is connected to one of the inputs of the first switch, the outputs of which are connected to the corresponding inputs of the second and third switches. In this case, the other input of the second switch is connected to one of the inputs of the first switch and is the corresponding input of the first selection block. One of the outputs of the third decoder through the third delay line is connected to the corresponding input of the third switch. One of the inputs of the element And is connected to the corresponding output of the fourth decoder, while the other outputs of the first, second and third decoders are connected to the corresponding output of the fourth decoder and are the corresponding output of the first selection block. Other outputs of the fourth decoder and the output of the element And are the corresponding outputs of the first block selection. Other inputs of the first, third switches and the element And are the corresponding inputs of the first block selection.

 The second selection block contains the first, second, third and fourth decoders, the first and second switches, a delay line, the summing counter and element I. One of the inputs of the first, second, third and fourth decoders are interconnected and are the corresponding input of the second selection block. Other inputs of the first decoder connected to the corresponding inputs of the second decoder, and other inputs of the third decoder connected to the corresponding inputs of the second decoder, are the corresponding inputs of the second selection block. Other inputs of the fourth decoder are connected to the corresponding outputs of the first switch, and the output of the first decoder is connected to the corresponding inputs of the first switch and to the corresponding input of the second switch. The output of the second decoder is connected to the corresponding input of the first, second switches, the summing counter and through the delay line is connected to the corresponding input of the first switch. The output of the third decoder is connected to the corresponding input of the second switch, the output of which is connected to the corresponding input of the first switch. One of the outputs of the summing counter outputs is connected to the corresponding input of the element I. The other input of the summing counter and the element And are the corresponding inputs of the second selection block. Other outputs of the first switch, summing the counter, connected to the output of the fourth decoder, and the output of the element And are the corresponding outputs of the second block selection.

 The third selection block contains the first, second, third and fourth decoders, the first and second switches, a delay line summing the counter and element I. One of the inputs of the first, second, third and fourth decoders are interconnected and are the corresponding input of the third selection block. Other inputs of the first decoder connected to the corresponding inputs of the second decoder, and other inputs of the third decoder connected to the corresponding inputs of the second decoder, are the corresponding inputs of the third selection block. Other inputs of the fourth decoder are connected to the corresponding outputs of the first switch, and the output of the first decoder is connected to the corresponding inputs of the first switch and to the corresponding input of the second switch. The output of the second decoder is connected to the corresponding input of the first, second switches, the summing counter and through the delay line is connected to the corresponding input of the first switch. The output of the third decoder is connected to the corresponding input of the second switch, the output of which is connected to the corresponding input of the first switch. One of the outputs of the totalizing counter is connected to the corresponding input of the And element, and the other input of the totalizing counter and the And element are the corresponding inputs of the third selection block. The other outputs of the first switch, summing the counter, connected to the output of the fourth decoder, and the output of the And element are the corresponding outputs of the third selection block.

 The fourth selection block contains the first and second switches, a delay line, the first, second and third decoders, the totalizing counter and element I. One of the inputs of the first, second switches and the totalizing counter are interconnected and are the corresponding input of the fourth selection block. The output of the totalizing counter through the delay line is connected to the corresponding input of the second switch. One of the inputs of the first, second, third decoders, the summing counter and the And element, interconnected, are the corresponding input of the fourth block of selection. One of the inputs of the first switch is connected to the corresponding input of the And element and is the corresponding input of the fourth selection block, and the other inputs of the first switch are the corresponding inputs of the fourth selection block. Other inputs of the first and second decoders are connected to the corresponding outputs of the second switch. Other inputs of the second switch and the third decoder are connected to the corresponding outputs of the first switch. One of the outputs of the first decoder is connected to the other input of the totalizing counter. The other output of the first decoder connected to the output of the second decoder and the And element, and the output of the third decoder connected to the other input of the And element, are the corresponding outputs of the fourth selection block.

 The search strategy register contains a trigger, the first to the fourth AND elements and a delay line. One of the inputs of the first and second elements And, interconnected, are the corresponding input of the search strategy register. In this case, the output of the first element And is connected to the output of the fourth element And and is the output of the search strategy register. The output of the second and third elements And through the delay line are connected to the corresponding input of the trigger, the output of which is connected to the corresponding input of the first, second, third and fourth elements I. Another input of the first element And is connected to the corresponding input of the second, third and fourth elements And is search case register entry. Other trigger inputs, interconnected, another input of the third and fourth elements AND are the corresponding inputs of the search strategy register.

 Unlike known devices that provide only probabilistic recognition of information, depending on various conditions, the proposed device gives an unambiguous decision on the presence (or absence) of TFTP communication protocol in this SPD, provided that the digital stream is received qualitatively. A useful effect consists in isolating the parameters of the digital stream and obtaining an unambiguous decision on the presence (or absence) of TFTP protocol in the general information digital stream.

 In FIG. 1 shows an electrical functional diagram of the proposed device; figure 2 is an electrical functional diagram of a memory unit; in FIG. 3 - electrical functional diagram of the switch; figure 4 is an electrical functional diagram of the first block selection; figure 5 is an electrical functional diagram of the second block selection; figure 6 is an electrical functional diagram of the third block of selection; Fig.7 is an electrical functional diagram of the fourth block selection; on Fig - electrical functional diagram of the register search strategy; figure 9 - packet structure of the TFTP protocol; in FIG. 10 is an algorithm for the operation of the TFTP communication protocol; 11 is a syntax recognition algorithm for the TFTP communication protocol.

The information search device shown in Fig. 1 comprises a frequency divider 1, a memory unit 2, a subtracting counter 3, a switch 4, a first 5, a second 6, a third 7 and a fourth 8 selection blocks, a search strategy register 9, a shaper 10 of time intervals and block 11 indication. The input of the frequency divider 1 is the input of the clock frequency F _{t of the} information retrieval device. The second and ninth inputs of the memory unit 2 are the corresponding signal inputs F _{s of the} device. The second and thirteenth inputs of the subtracting counter 3 are the corresponding information inputs N of the information retrieval device. The output of the frequency divider 1 is connected to the first inputs of the memory block 2, subtracting the counter 3, the first 5, the second 6, the third 7 and the fourth 8 selection blocks, register 9 of the search strategy. The first and eighth outputs of memory block 2 are connected respectively to the fourth and eleventh inputs of switch 4. The first output of the subtracting counter 3 is connected to the tenth input of memory block 2, the twelfth input of switch 4, the eleventh input of the first selection block 5, tenth inputs of the second 6, third 7, and the fourth 8 selection blocks, the third input of the search strategy register 9 and is the command output F _{r of the} device. The second output of the subtracting counter 3 is connected to the eleventh inputs of the second 6, third 7 and fourth 8 selection blocks, and the third output of the subtracting counter 3 is connected to the twelfth input of the first block 5 of selection. The first - eighth, ninth - sixteenth, seventeenth - twenty fourth and twenty fifth - thirty second outputs of switch 4 are respectively connected to the second and ninth inputs of the first 5, second 6, third 7 and fourth 8 selection blocks, respectively. The first and second outputs of the first selection block 5 are connected respectively to the first and second inputs of the switch 4, the third output of the first selection block 5 is connected to the fourth input of the search strategy register 9 and the fourteenth input of the subtracting counter 3, the fourth output of the first selection block 5 is connected to the fifth input of the register 9 of the search strategy, the fourteenth input of the subtracting counter 3 and the input of the shaper 10 time intervals. The fifth output of the first selection block 5 is connected to the third input of the switch 4. The sixth output of the first selection block 5, the output of the search strategy register 9 and the first outputs of the second 6, third 7 and fourth 8 selection blocks are connected to the first input of the indication block 11, the tenth input of the first block 5 selection and the fourteenth input of the subtracting counter 3. The second output of the second selection block 6 is connected to the second input of the search strategy register 9, and the second output of the third selection block 7 is connected to the third input of the search strategy register 9. The second output of the fourth block 8 selection and the output of the shaper 10 time intervals are connected to the second input of the block 11 of the display and the fourteenth input of the subtracting counter 3.

 The memory unit 2 shown in FIG. 2 contains an inverter 2.1, a first 2.2 and a second 2.3 summing counters, a switch 2.4, an AND 2.5 element, a differentiating circuit 2.6 and RAM 2.7. The second input of the first totalizing counter 2.2 is the first input of the memory unit 2, the first and eighth inputs of the switch 2.4 are the second and ninth inputs of the memory unit 2, and the tenth input of the memory unit 2 is connected to the ninth input of the switch 2.4, the first input of RAM 2.7 and the inputs of inverter 2.1 and differentiating circuit 2.6. The output of the inverter 2.1 is the tenth input of the switch 2.4. The first, second, third and fourth outputs of the first totalizing counter 2.2 are connected, respectively, with the first input of the AND 2.5 element and the second input of RAM 2.7, with the second input of the AND 2.5 element and the third input of RAM 2.7, with the third input of the AND 2.5 element and the fourth input of RAM 2.7, with the fourth input of AND 2.5 and the fifth input of RAM 2.7. The first - seventh outputs of the second totalizing counter 2.3 are respectively the sixth - twelfth inputs of RAM 2.7. The first - the eighth input / output of the switch 2.4 is connected respectively with the thirteenth - twentieth input / output of RAM 2.7. The ninth - sixteenth outputs of the switch 2.4 are respectively the first - eighth output of the memory unit 2. The output of AND 2.5 is the first input of the second totalizing counter 2.3, and the output of the differentiating circuit 2.6 is connected to the first input of the first totalizing counter 2.2 and the second input of the second totalizing counter 2.3.

 The switch 4. shown in FIG. 3, contains the first 4.1, second 4.2, third 4.3 and fourth 4.4 triggers, first 4.5, second 4.6, third 4.7 and fourth 4.8 buffer elements. The first input of the switch 4 is connected to the first input of the second trigger 4.2 and the second inputs of the first 4.1, the third 4.3 and the fourth 4.4 triggers. The second input of the switch 4 is connected to the first input of the third trigger 4.3 and the second inputs of the first 4.1, the second 4.2 and the fourth 4.4 triggers. The third input of the switch 4 is connected to the first input of the fourth trigger 4.4 and the second inputs of the first 4.1, the second 4.2 and the third 4.3 triggers. The fourth and eleventh inputs of switch 4 are, respectively, the second and ninth inputs of the first 4.5, second 4.6, third 4.7 and fourth 4.8 buffer elements. The twelfth input of the switch 4 is connected in parallel with the first input of the first trigger 4.1 and the second inputs of the second 4.2, the third 4.3 and the fourth 4.4 triggers. The outputs of the first 4.1, second 4.2, third 4.3 and fourth 4.4 triggers are the first inputs of the first 4.5, second 4.6, third 4.7 and fourth 4.8 elements, respectively. The first - eighth outputs of the first buffer element 4.5 are, respectively, the first - eighth outputs of the switch 4, the first - eighth outputs of the second buffer element 4.6 are the ninth - sixteenth outputs of the switch 4, the first - eighth outputs of the third buffer element 4.7 are, respectively, the seventeenth - twenty fourth outputs of the switch 4, and the first - eighth outputs of the fourth buffer element 4.8 are, respectively, the twenty fifth - thirty second outputs of the switch 4.

 The first selection block 5, shown in Fig. 4, contains the first delay line 5.1, the first 5.2, the second 5.3 and the third 5.4 switches, the first 5.5, the second 5.6, the third 5.7 and the fourth 5.8 decoders, the second 5.9 and the third 5.10 delay lines, AND element 5.11. In this case, the first input of the first block 5 of selection is connected to the first inputs of the first 5.5, third 5.7 decoders and the ninth inputs of the second 5.6 and fourth 5.8 decoders. The second - ninth inputs of the first block 5 selection are respectively the second - ninth inputs of the first switch 5.2. The tenth input of the first block 5 of selection is connected to the tenth inputs of the first 5.2 and second 5.3 switches. The eleventh input of the first selection block 5 is the tenth input of the third switch 5.4. The twelfth input of the first block 5 selection is the second input of the element And 5.11. The output of the first delay line 5.1 is the first input of the first switch 5.2. The first - eighth and ninth - sixteenth outputs of the first switch 5.2 are respectively the second - ninth inputs of the second 5.3 and third 5.4 switches, respectively. The first - eighth and ninth - sixteenth outputs of the second switch 5.3 are, respectively, the second - ninth inputs of the first decoder 5.5 and the first - eighth inputs of the second decoder 5.6. The first - eighth and ninth - sixteenth outputs of the third switch 5.4 are, respectively, the second - ninth inputs of the third decoder 5.7 and the first - eighth inputs of the fourth decoder 5.8. The first output of the first decoder 5.5 is the input of the second delay line 5.9, the output of which is the first input of the second switch 5.3. The first and second outputs of the second decoder 5.6 are respectively the first and second outputs of the first block 5 of selection, and their connection is the input of the first delay line 5.1. The first output of the third decoder 5.7 is the input of the third delay line 5.10. The first, second and third outputs of the fourth decoder 5.8 are respectively the third output of the first block 5 of selection, the first input of the element And 5.11 and the fifth output of the first block 5 of selection. The connection of the second outputs of the first 5.5 and third 5.7 decoders, the third output of the second decoder 5.6 and the fourth output of the fourth decoder 5.8 is the sixth output of the first block 5 of selection. The output of the third delay line 5.10 is the first input of the third switch 5.4, and the output of AND 5.11 is the fourth output of the first selection unit 5.

 The second selection block 6, shown in FIG. 5, contains the first 6.1, second 6.2, third 6.3 and fourth 6.7 decoders, the first 6.4 and second 6.6 switches, a delay line 6.5, the totalizing counter 6.8 and the And element 6.9. The first input of the second block 6 of the selection is the first inputs of the first 6.1, second 6.2, third 6.3 and fourth 6.7 decoders. The second, third and fourth inputs of the second block 6 of selection are connected respectively with the second, third and fourth inputs of the first 6.1 and second 6.2 decoders. The fifth - ninth inputs of the second block 6 of selection are respectively the fifth - ninth and second - sixth inputs, respectively, of the second 6.2 and third 6.3 decoders. The tenth input of the second block 6 selection is the second input of the totalizing counter 6.8, and its eleventh input is the second input of the element And 6.9. The output of the first decoder 6.1 is connected to the first and second inputs of the first switch 6.4 and the second input of the second switch 6.6. The output of the second decoder 6.2 is connected to the third input of the first switch 6.4, the input of the delay line 6.5 and the first inputs of the totalizing counter 6.8 and the second switch 6.6. The output of the third decoder 6.3 is the third input of the second switch 6.6. The output of the delay line 6.5 is the fourth input of the first switch 6.4. The output of the second switch 6.6 is connected to the third input of the first switch 6.4. The first and second outputs of the first switch 6.4 are respectively the second and third inputs of the fourth decoder 6.7. The connection of the output of the fourth decoder 6.7, the third output of the first switch 6.4, the first output of the totalizing counter 6.8 is the first output of the second block 6 selection. The second output of the totalizing counter 6.8 is the first input of the element And 6.9, the output of which is the second output of the second block 6 of selection.

 The third selection block 7, shown in Fig.6, contains the first 7.1, second 7.2, third 7.3 and fourth 7.7 decoders, the first 7.4 and second 7.6 switches, delay line 7.5, summing counter 7.8 and AND element 7.9. The first input of the third block 7 selection is the first inputs of the first 7.1, the second 7.2. third 7.3 and fourth 7.7 decoders. The second, third and fourth inputs of the third block 7 of selection are connected respectively with the second, third and fourth inputs of the first 7.1 and second 7.2 decoders. The fifth and ninth inputs of the third block 7 of selection are respectively the fifth - ninth and second - sixth inputs of the second 7.2 and third 7.3 decoders, respectively. The tenth input of the third block 7 of selection is the second input of the totalizing counter 7.8, and its eleventh input is the second input of the element And 7.9. The output of the first decoder 7.1 is connected to the first and second inputs of the first switch 7.4 and the second input of the second switch 7.6. The output of the second decoder 7.2 is connected to the third input of the first switch 7.4, the input of the delay line 7.5 and the first inputs of the totalizing counter 7.8 and the second switch 7.6. The output of the third decoder 7.3 is the third input of the second switch 7.6. The output of the delay line 7.5 is the fourth input of the first switch 7.4. The output of the second switch 7.6 is connected to the third input of the first switch 7.4. The first and second outputs of the first switch 7.4 are respectively the second and third inputs of the fourth decoder 7.7. The connection of the output of the fourth decoder 7.7, the third output of the first switch 7.4, the first output of the totalizing counter 7.8 is the first output of the third block 7 selection. The second output of the totalizing counter 7.8 is the first input of the element And 7.9, the output of which is the second output of the third block 7 of selection.

 The fourth block 8 of the selection shown in Fig.7, contains the first switch 8.1, the delay line 8.2, the second switch 8.3, the first 8.4, the second 8.5 and the third 8.6 decoders, summing the counter 8.7 and the element And 8.8. The first input of the fourth block 8 of selection is the first inputs of the first 8.4, second 8.5 and third 8.6 decoders and the second inputs of the totalizing counter 8.7 and the element And 8.8. The second and ninth inputs of the fourth block 8 of selection are, respectively, the first and eighth inputs of the first switch 8.1. The tenth input of the fourth block 8 of the selection is the ninth input of the first switch 8.1, the first inputs of the second switch 8.3 and the totalizing counter 8.7. The eleventh input of the fourth block 8 selection is the tenth input of the first switch 8.1 and the third input of the element And 8.8. The first - eighth and ninth - sixteenth outputs of the first switch 8.1 are respectively the third - tenth inputs of the second switch 8.3 and the second - ninth inputs of the third decoder 8.6. The output of the delay line 8.2 is the second input of the second switch 8.3. The first - eighth and ninth - eleventh outputs of the second switch 8.3 are respectively the second - ninth inputs of the first decoder 8.4 and the second - fourth inputs of the second decoder 8.5. The output of the first decoder 8.4 is the third input of the totalizing counter 8.7. The output of the totalizing counter 8.7 is the input of the delay line 8.2. The connection of the second output of the first decoder 8.4, the outputs of the second decoder 8.5 and the element And 8.8 is the first output of the fourth block 8 of the selection. The output of the third decoder 8.6 is connected to the first input of the AND element 8.8 and is the second output of the fourth block 8 of selection.

 The search strategy register 9 shown in FIG. 8 comprises a trigger 9.1, a first 9.2, a second 9.3, a third 9.4 and a fourth 9.5 and elements 4 and a delay line 9.6. In this case, the first input of the search strategy register 9 is connected to the second inputs of the first 9.2 and second 9.3 elements AND and the first inputs of the third 9.4 and fourth 9.5 elements I. The second input of the search strategy register 9 is the second input of trigger 9.1, and the third input of the search strategy register 9 is the third trigger input 9.1. The fourth input of the search strategy register 9 is connected in parallel with the third input of the fourth AND element 9.5 and the second input of the third AND element 9.4. The fifth input of the search strategy register 9 is connected to the third inputs of the first 9.2 and second 9.3 elements I. The trigger output 9.1 is connected to the first inputs of the first 9.2, second 9.3 elements And, the second input of the fourth element And 9.5 and the third input of the third element And 9.4. The connection of the outputs of the second 9.3 and the third 9.4 elements And is the input of the delay line 9.6, the output of which is connected to the first input of the trigger 9.1. The connection of the outputs of the first 9.2 and fourth 9.5 elements And is the output of the register 9 of the search strategy.

 The claimed device operates as follows.

 The information retrieval device is designed to detect in a digital stream transmitted in a communication channel messages corresponding to a TFTP protocol that differs from other similar file transfer protocols by a specific set of service and information messages (packets) and the rules for exchanging them with corresponding stations during an inter-machine exchange session.

 In a whole series of technical problems in the field of telecommunications, the problem of searching for information of a certain type in the general information flow arises, which can be solved by statistical (analog), logical (prototype) methods or methods of the theory of pattern recognition (the proposed device that implements the principles of the theory of parsing), described in the book by J. Tu, R. Gonzalez. Pattern recognition principles. Per. from English -M .: Mir, 1978, p. 411.

 Unlike known devices that provide correct recognition of information with some probability, depending on various conditions, the proposed device develops an unambiguous decision on the presence (absence) of messages of a certain type in the general information stream.

 Actually, the functioning algorithm of the TFTP protocol is as follows (Fig. 10): the interaction between computers on reading / writing files is carried out in standard-length packets in start-stop mode. TFTP packets are carried in separate gateway datagrams (or network protocol packets).

 Any transmission begins with the transmission of the packet "Request for reading" (in Fig. 10, 11 is indicated 01) or "Request for recording" (02), transmitted from the user to the remote computer, which corresponds to the request to establish a connection. If the computer receives the request, the connection is established and then the file is transmitted in blocks of a fixed length of 512 bytes. Each data packet ("Data" - 03) is sequentially numbered starting from 1, contains one block and must be confirmed by the "Receipt" packet (04), which also has a number, before the next packet is transmitted. The confirmation of the "Write Request" packet is 0, the confirmation for the "Read Request" packet is the first data block. A packet of less than 512 bytes in length is a sign of completion of transmission. Closing the connection is timed out after receiving the last packet on the receiving side and receiving confirmation of the last packet on the transmitting side.

 An error is indicated by sending an Error packet (05) and leads to a disconnection.

 The formats used in TFTP packets are shown in FIG.

Search (recognition) of information is carried out using the characteristics of two groups:
qualitative features inherent in both TFTP and a number of other types of communication protocols, which are the packages used;
structural features unique to TFTP, which is an exhaustive finite set of allowed packet sequences.

 The proposed device, which implements a method of searching for information on the indicated grounds, consists in analyzing communication sessions in SPD and comparing their structure with a priori known rules for organizing data transfer using the TFTP protocol. If they coincide, a decision is made that the communication session is carried out using the desired protocol type.

 Implemented in the proposed device, the method of syntactic recognition of the TFTP protocol (Fig. 11) is based on the identification operation transmitted on the packet channel (01, 02, 03, 04, 05) and the rules for exchanging them during a communication session.

The protocol specification is described by the following regular grammar:
G = (Vn, Vt, P, S),
Where
Vn = (01 *, 02 *, 03 *, 03 #, 04 *, 04 #, 05 *, 05 #, ANY *, ANY #, T) - a set of packets provided by the protocol (the * packets indicate the user packets, the symbol # - remote computer packets, T - timeout);
Vt = (S, A, B, C, D, E, F) - the set of possible states of the logical connection between the application file transfer processes;
P = (S ---> 01 * A, S ---> 02 * C, S ---> ANY * F, A ---> 03 # B, A ---> 05 # E, A- -> ANY # F, A ---> TE, B ---> 04 * A, D ---> 05 * E, B ---> ANY * F, C ---> 04 # D, C ---> 05 # E, C ---> ANY # F, D ---> 03 * C, D ---> 05 * E, D ---> TE, D ---> ANY * F) - many rules for exchanging packets during a communication session.

 S is the initial state of the logical connection between the application file transfer processes.

The input signals for the information retrieval device (FIG. 1) are a digital signal sequence F _s , a clock frequency signal F _t and data N about the duration of the analyzed packets coming from a demodulating device (channel controller).

A frequency divider 1 serves to divide the clock frequency F _t by 8 in order to provide a byte analysis of the signal digital sequence F _s .

The memory unit 2 is designed to provide byte write / read one packet of a digital signal sequence
Subtracting counter 3 is used to determine the number of bytes of the packet, including bytes, which are currently being analyzed in the memory block 2, control the functioning of the memory block 2, the first 5, second 6, third 7 and fourth 8 selection blocks, register 9 of the search strategy and the formation of a control signal (logical "1") F _r enable broadcast signal digital sequence F _s supplied to the demodulating device (channel controller).

 Information N on the number of bytes contained in the packet received in the memory unit 2 is recorded in the subtracting counter 3 in parallel form on its second - thirteenth inputs at the time the last byte of the packet arrives in the memory unit 2. The counter is reduced by one each time a control signal arrives at its first input from the output of the frequency divider 1. The counter is reset to zero when the control signal arrives at the fourteenth input of the subtracting counter. When the value of the subtracting counter 3 is 0, a control signal is generated at its first output, when the value of the subtracting counter 3 is 1, a control signal is generated at its second output, and when the value of the subtracting counter 3 is 3, the control signal is generated at its third output.

Switch 4 is designed for byte-switching the signal digital sequence F _s coming from memory unit 2 to the inputs of the first 5, second 6, third 7 and fourth 8 selection blocks. When a control signal arrives at the first input of switch 4, the fourth to eleventh inputs of switch 4 are switched to its ninth to sixteenth outputs, and when a control signal arrives at the second input of switch 4, the fourth to eleventh inputs of switch 4 are switched to its seventeenth to twenty-fourth outputs, respectively , when the control signal arrives at the third input of the switch 4, the fourth - eleventh inputs of the switch 4 are switched but it to a twenty-fifth - the thirty-second output, and arrives at the control signal input to the twelfth switch 4 of the fourth switching occurs - the eleventh switch inputs 4 respectively to its first - eighth outputs.

 The first block 5 selection is intended for preliminary determination of the type of packets according to the content of its first two bytes (Fig. 8).

 The second block 6 of selection is intended to identify the package "Request for reading" by its a priori structure.

 The third block 7 of selection is intended to identify the package "Request for recording" by its a priori structure.

 The fourth block 8 of selection is intended to identify the package "Error" by its a priori structure.

The register 9 of the search strategy is designed to verify compliance of the order of arrival of packets of the signal digital sequence F _{s to the} rules of the organization of data exchange of the TFTP protocol.

 Shaper 10 time intervals is designed to generate a signal indicating the end of the communication session, by timeout after receiving the last packet "Receipt". It is a timer that generates a control signal at its output after a period of time set in accordance with the data exchange rules adopted in this communication channel. The shaper zeroing 10 time intervals occurs when a control signal is received at its input.

 The indication unit 11 is intended for generating an information signal about using (or not using) in this TFTP communication session. When the control signal arrives at the first input of the display unit 11, it generates a signal indicating the use of a communication protocol other than TFTP in this communication session, and when the information signal arrives at the second input of the display unit 11, it generates a signal indicating that The communication session uses the TFTP communication protocol.

Block 2 memory (figure 2) works as follows:
Inverter 2.1 serves to generate a control signal supplied to the tenth input of switch 2.4.

 The first 2.2 and second 2.3 totalizing counters are designed to address RAM 2.7 cells when writing or reading information, while the first totalizing counter 2.2 addresses sixteen columns, and the second totalizing counter 2.3 - one hundred twenty-eight lines of the RAM 2.7 matrix. Zeroing the first 2.2 and second 2.3 counters occurs when a control signal arrives at the first and second inputs, respectively. The second input of the first 2.2 and the first input of the second 2.3 summing counters are signal.

Switch 2.4 provides a record of bytes of the signal digital sequence F _s in RAM 2.7 and their subsequent reading. When a control signal ("1") is received at the ninth input of switch 2.4, its first and eighth inputs are connected to its first and eighth inputs / outputs, and when a control signal is received at the tenth input of switch 2.4, its first and eighth inputs / outputs are connected to its ninth to sixteenth exits.

 Element And 2.5 provides a control pulse to the first input of the second totalizing counter 2.3 after counting every sixteen pulses received at the second input of the first totalizing counter 2.2.

 Differentiating circuit 2.6 converts the on-off control signal (“0” and “1”) into a sequence of bipolar pulses with further conversion of the bipolar sequence into a sequence of unipolar pulses.

 RAM 2.7 is designed to store bytes of one packet. If there is a logical "1" at the first input of RAM 2.7, RAM 2.7 is in write mode, and if there is a logical "0" - in read mode. The addressing of the RAM cells 2.7 during recording / reading is provided by a combination of control signals at its second to twelfth inputs.

 The switch 4 (figure 3) works as follows.

 The first 4.1, second 4.2, third 4.3 or fourth 4.4 triggers upon receipt of a control signal at their first inputs generate a broadcast enable signal, arriving respectively at the first 4.5, second 4.6, third 4.7 or fourth 4.8 buffer elements.

 When a control signal arrives at the second inputs of the first 4.1, second 4.2, third 4.3 or fourth 4.4 triggers, the corresponding trigger is reset. It should be noted that if there is a control signal at the first input of any of the triggers at the second inputs of the other three triggers, the control signal will also be present, so at any time the broadcast enable signal will be present at the output of only one of the triggers.

 When a broadcast enable signal arrives at the first input of the first 4.5, second 4.6, third 4.7 or fourth 4.8 buffer elements, the information signal received at their second and ninth inputs will be transmitted respectively through the first and eighth outputs respectively of the first 4.5. second 4.6, third 4.7 or fourth 4.8 buffer elements.

 The first block 5 selection (figure 4) works as follows.

The first delay line 5.1 provides a delay of the control signal arriving at its input for a time T _z = 4 / F _t to prevent the occurrence of transients during switching of the first switch 5.2.

 The first switch 5.2 provides the connection of the signal arriving at its second - ninth inputs to the inputs of the second 5.3 and third 5.4 switches. When the control signal arrives at the first input of the first switch 5.2, the second to ninth inputs of the first switch 5.2 are switched with its ninth to sixteenth outputs, and when the control signal arrives at the tenth input of the first switch 5.2, the second and ninth inputs of the first switch 5.2 are connected to its first and eighth exits.

 The second switch 5.3 connects the input signal to its second to ninth inputs to the inputs of the first 5.5 and second 5.6 decoders. When the control signal arrives at the first input of the second switch 5.3, the second to ninth inputs of the second switch 5.3 are switched with its ninth to sixteenth outputs, and when the control signal arrives at the tenth input of the second switch 5.3, the second and ninth inputs of the second switch 5.3 are connected to its first and eighth exits.

 The third switch 5.4 provides the connection of the input signal arriving at its second to ninth inputs to the inputs of the third 5.7 and fourth 5.8 decoders. When the control signal arrives at the first input of the third switch 5.4, the second to ninth inputs of the third switch 5.4 are switched with its ninth to sixteenth outputs, and when the control signal arrives at the tenth input of the third switch 5.4, the second and ninth inputs of the third switch 5.4 are connected to its first and eighth exits.

 The first decoder 5.5 provides a check for compliance with the zero value received at its second - ninth inputs of the code combination. When a zero combination arrives at these inputs, a control signal is generated at the first output of the first decoder 5.5, and if there is at least one unit in the input code combination, a control signal is generated at the second output of the first decoder 5.5.

 The second decoder 5.6 provides verification of the input code combination received at its first to eighth inputs. Upon receipt of the code combination corresponding to one, a control signal is generated at the first output of the second decoder 5.6, upon receipt of the code combination corresponding to two, a control signal is generated at the second output of the second decoder 5.6, and when any other code combination is received, the control signal is generated at the third output of the second decoder 5.6.

 The third decoder 5.7 provides a check for compliance with the zero value received at its second - ninth inputs of the code combination. When a zero combination arrives at the inputs at the first output of the third decoder 5.7, a control signal is generated, and if there is at least one unit in the input code combination, a control signal is generated at the second output of the third decoder 5.7.

 The fourth decoder 5.8 provides verification of the input code combination received at its first to eighth inputs. Upon receipt of a code combination corresponding to three, a control signal is generated at the first output of the fourth decoder 5.8, upon receipt of a code combination corresponding to four, a control signal is generated at the second output of the fourth decoder 5.8, at the receipt of a code combination corresponding to five, at the third output of the fourth decoder 5.8 a control signal is generated, and upon receipt of any other code combination, a control signal is generated at the fourth output of the fourth decoder 5.8.

 Clocking of the work of the first 5.5, third 5.7 decoders is carried out by the signal supplied to their first inputs, and clocking of the work of the second 5.6 and fourth 5.8 decoders is carried out by the signal arriving at their ninth inputs.

The second 5.9 and third 5.10 delay lines provide a delay of the control signal arriving at their input for a delay time T _z = 4 / F _t to prevent transients during switching of the second 5.3 and third 5.4 switches, respectively.

 Element And 5.11 provides a check of the structure of the "Receipt" packet for the number of bytes.

 The second block 6 selection (figure 5) works as follows.

 The first decoder 6.1 checks the input code combination arriving at its second and fourth inputs for the presence of at least one unit at these inputs, which indicates the transfer of information characters in ASCII code (Abel P. Assembly Language for IBM PC and Programming. / Per . from English Yu.V. Saltykov. -M .: Higher school. 1992, v. 47 p. 447), in this case, the control signal is generated at the output of the first decoder 6.1.

 The second decoder 6.2 provides a check of the input code combination arriving at its second to ninth inputs, in the absence of units at these inputs, which indicates the transmission of a zero byte, a control signal is generated at the output of the second decoder 6.2.

 The third decoder 6.3 in the presence of at least one unit at its second and sixth inputs generates a control signal at its output.

 When the first switch 6.4 arrives at its first input, the control signal commutes the second and third inputs of the first switch 6.4, respectively, to its first and second outputs; when the control signal arrives at the fourth input of the first switch 6.4, its third input and third output are switched. The presence of logical “1” on the third output of the first switch 6.4 indicates that after the arrival of a zero byte, the second block 6 received a second consecutive zero byte or a byte that is neither zero nor informational, which is not allowed by the rules for organizing data exchange .

The delay line 6.5 provides a delay of the control signal arriving at its input for a delay time T _z = 4 / F _t to prevent transients from occurring when switching the first switch 6.4.

 The second switch 6.6, upon receipt of a control signal at its first input, connects the output of the third decoder 6.3 to the third input of the first switch 6.4, and when the control signal arrives at the second input of the second switch 6.6, this connection is disconnected.

 The fourth decoder 6.7, summarizing the counter 6.8 and the And 6.9 element, provides a check of the structure of the “Read Request” packet for the number of zero bytes and the order of the mutual following of zero and information bytes allowed by the rules for organizing data exchange.

 The fourth decoder 6.7, when it receives a logical “0” at its second and third inputs (this means that the first code sequence received at the second and ninth inputs of the second block 6 is neither zero nor informational) generates a control signal at its output.

 The clocking of the first 6.1, second 6.2, third 6.3 and fourth 6.7 decoders is carried out according to the signals arriving at their first inputs.

 The totalizer 6.8 provides control over the number of zero bytes in one packet. When two pulses arrive at the first input of the totalizing counter 6.8, a control signal is generated at its second output, and when three pulses are received at the first input of the totalizing counter 6.8, a control signal is generated at its first output. Resetting the totalizing counter 6.8 occurs when a control signal is received at its second input.

 Element And 6.9 forms a positive decision on the correspondence of the structure of the packet under study to the structure of the "Read Request" packet only if the arrival time of the control signals coincides, indicating the presence of two zero bytes in the packet and that the last byte of the packet is being processed.

 The third block 7 selection (Fig.6) works as follows.

 The first decoder 7.1 checks the input code combination arriving at its second and fourth inputs for the presence of at least one unit at these inputs, which indicates the transmission of information symbols in the ASCII code, in this case, a control signal is generated at the output of the first decoder 7.1.

 The second decoder 7.2 provides verification of the input code combination arriving at its second to ninth inputs, in the absence of units at these inputs, which indicates the transmission of a zero byte, a control signal is generated at the output of the second decoder 7.2.

 The third decoder 7.3 in the presence of at least one unit at its second to sixth inputs generates a control signal at its output.

 The first switch 7.4, when the control signal arrives at its first input, the second and third inputs of the first switch 7.4 are switched respectively to its first and second outputs; when the control signal arrives at the fourth input of the first switch 7.4, its third input and third output are switched. The presence of logical “1” on the third output of the first switch 7.4 indicates that after the arrival of a zero byte, the second block 7 received a second consecutive zero byte or a byte that is neither zero nor informational, which is not allowed by the rules for organizing data exchange .

The delay line 7.5 provides a delay of the control signal arriving at its input for a delay time T _z = 4 / F _t to prevent the occurrence of transients during switching of the first switch 7.4.

 The second switch 7.6, upon receipt of a control signal at its first input, connects the output of the third decoder 7.3 to the third input of the first switch 7.4, and when the control signal arrives at the second input of the second switch 7.6, this connection is disconnected.

 The fourth decoder 7.7, summarizing the counter 7.8 and the And 7.9 element, provides a check of the structure of the "Write Request" packet for the number of zero bytes and the order of mutual following of zero and information bytes allowed by the rules for organizing data exchange.

 The fourth decoder 7.7, when a logical “0” is received at its second and third inputs (which means that the first code combination received at the second and ninth inputs of the third block 7 is neither zero or information) generates a control signal at its output.

 The clocking of the first 7.1, second 7.2, third 7.3 and fourth 7.7 decoders is carried out according to the signals arriving at their first inputs.

 The totalizer 7.8 provides control over the number of zero bytes in one packet. When two pulses arrive at the first input of the totalizing counter 7.8, a control signal is generated at its second output, and when three pulses are received at the first input of the totalizing counter 7.8, a control signal is generated at its first output. Resetting the totalizing counter 7.8 occurs when a control signal is received at its second input.

 Element And 7.9 forms a positive decision on the correspondence of the structure of the packet under study to the structure of the “Write Request” packet only if the arrival time of the control signals coincides, indicating the presence of two zero bytes in the packet and that the last byte of the packet is being processed.

 The fourth block 8 selection (Fig.7) works as follows.

 The first switch 8.1 is intended for switching the input stream arriving at its first and eighth inputs, at the inputs of the second switch 8.3 and the third decoder 8.6. When the control signal is received at the ninth input of the first switch 8.1, the first and eighth inputs of the first switch 8.1 are connected to its first and eighth outputs, and when the control signal is received at the tenth input of the first switch 8.1, the first and eighth inputs of the first switch 8.1 are connected to it ninth to sixteenth exits.

The delay line 8.2 provides a delay of the control signal arriving at its input for a delay time T _z = 4 / F _t to prevent transients during switching of the second switch 8.3.

 The second switch 8.3 is intended for switching the input stream arriving at its third to tenth inputs, at the inputs of the first 8.4 and second 8.5 decoders. When a control signal is received at the first input of the second switch 8.3, the third to tenth inputs of the second switch 8.3 are connected to its first and eighth outputs, and when a control signal is received at the second input of the second switch 8.3, the third and fifth inputs of the second switch 8.3 are connected to its the ninth - eleventh exits.

 The first decoder 8.4 checks for the presence of an error code and, when it arrives at its second - ninth inputs, at least one unit generates a control signal at its first output, and if there are only logical "0" at the inputs - it generates a control signal at its second output.

 The second decoder 8.5 checks for the presence of bytes of the error message, and if the second - fourth inputs of the second decoder 8.5 received only logical "0", it generates a control signal at its output.

 The third decoder 8.6 when it arrives at its second - ninth logic inputs "0" generates a control signal at its output.

 The totalizing counter 8.7 is designed to control the operation of the second switch 8.3. Upon receipt of two logical "1" at its third input, a control signal is generated at its output. The zeroing of the readings of the totalizing counter 8.7 occurs when a control signal is received at its first input.

 The AND 8.8 element, which has an inverting first input, is intended to check the last byte of the Error packet. When a logical “0” is received at its first input, indicating that the last byte of the “Error” packet is not zero, but at its third input is a signal indicating that the last byte of the packet is being analyzed, at the output of AND 8.8 a control signal is generated.

 The clocking of the work of the first 8.4, the second 8.5 and the third 8.6 of the decoders is carried out by pulses arriving at their first inputs, and the clocking operation of the summing counter 8.7 and the element And 8.8 is carried out by pulses arriving at their second inputs.

 Register 9 search strategy (Fig) works as follows.

 Trigger 9.1 takes a state of logical "1" when a control signal arrives at its second input and takes a state of logical "0" when a control signal arrives at its third input. In the future, trigger 9.1 changes its state to the opposite each time a control signal arrives at its first input.

 The first element And 9.2 information are the first and third inputs, and the clocking of the work is carried out on its second input.

 The second element And 9.3 information are the first inverse and third inputs, and the clocking of the work is carried out at its second input.

 The third element And 9.4 information are the second and third inputs, and the clocking of the work is carried out at its first input.

 The fourth element And 9.5 information are the second inverse and third inputs, and the clocking of the work is carried out at its first input.

The delay line 9.6 provides a delay of the control signal arriving at its input for a delay time T _z = 4 / F _t to prevent the occurrence of transients during the transition of trigger 9.1 from one state to another.

 Thus, in general, the device operates as follows: a frequency divider 1 provides a byte analysis of the input digital sequence. Upon receipt of write permission from the first output of the reverse counter 3 (logical "1"), the RAM cells are filled with 2 bytes of a packet received from a demodulating device (channel controller). After all the bytes of the next packet of the analyzed protocol are written, the total number of 2 bytes written to RAM is entered into the subtracting counter 3, after which a permission for reading bytes of information (logical "0") is generated at its first output. Through the switch 4, the first two bytes of the packet are sequentially delivered to the first block 5 of selection, where the value of the bytes received makes a preliminary decision about the type of packet received, while the second 6, third 7 and fourth 8 selection blocks are disabled. If it is decided that this packet is a “Read Request”, then using switch 4, the remaining bytes of the packet stored in RAM 2 are sent to the second selection block 6, while the first 5, third 7 and fourth 8 selection blocks are disabled . If it is decided that this packet is a “Write Request”, then using switch 4, the remaining bytes of the packet stored in RAM 2 are sent to the third selection block 7, while the first 5, second 6 and fourth 8 selection blocks are disabled . If it is decided that this packet is an “Error”, then using switch 4, the remaining bytes of the packet stored in RAM 2 are sent to the fourth selection block 8, with the first 5, second 6, and third 7 selection blocks disabled. If it is decided that this packet is “Data” or “Receipt”, then a control signal is generated at the third and fourth outputs of the first selection block 5.

 In the second 6, third 7 and fourth 8 selection blocks, the structure of the analyzed package is checked for conformity with the a priori known structure of the “Request to read”, “Request to write” and “Error” packages, respectively.

The register 9 of the search strategy is designed to verify compliance of the order of arrival of packets of the signal digital sequence F _{s to the} rules of the organization of data exchange of the TFTP protocol.

 When a decision is made in the first 5, second 6, third 7 or fourth 8 selection blocks that the analyzed packet is not “authorized” or in case of violation of the permissible sequence of packets detected by register 9 of the search strategy, zeroing the subtracting counter 3 stops the analysis this package and the block 11 of the indication of this message is generated.

 Shaper 10 time intervals is designed to generate a signal indicating the end of the communication session, by timeout after receiving the last packet "Receipt". It is a timer that generates a control signal at its output after a period of time set in accordance with the data exchange rules adopted in this communication channel. The shaper zeroing 10 time intervals occurs when a control signal is received at its input.

 Upon receipt of a control signal from the output of the shaper 10 time intervals or from the second output of the fourth block 8 of selection to the second input of block 11 of the display, it generates a signal indicating the use of the TFTP communication protocol in this communication session.

 After making both a positive and a negative decision about using the TFTP protocol in this network, the subtracting counter 3 is reset and the information retrieval device is ready to analyze the incoming digital sequence.

 From the standpoint of classification according to the functional purpose, it should be noted that the frequency divider 1, the first 2.2 and the second 2.3 summing counters, summing the counters 6.8, 7.8 can be performed according to the scheme depicted in FIG. 1.66 (Shilo V. L. Popular digital microcircuits: a Handbook. -M .: Radio and Communications, 1987, p. 352 (Massive Radio Library. Issue 1111).) And in particular on K155IE5; subtracting counter 3 can be performed according to the circuit shown in FIG. 1.73 and in particular on K531IE17; summing counter 8.7 may be performed according to the circuit shown in FIG. 1.64 and, in particular, on K155IE2; trigger 9.1 can be implemented as a counter for two with the possibility of presetting the initial state and is made according to the circuit depicted in FIG. 1.64 and, in particular, on K155IE2; the first decoders 5.5, 6.1, 7.1, 8.4, the second decoders 5.6, 6.2, 7.2, 8.5, the third decoders 5.7, 6.3, 7.3, 8.6, the fourth decoders 5.8, 6.7, 7.7 can be performed according to the circuit depicted in FIG. 1.95 and, in particular, on K155IDZ; switch 2.4, the first switches 5.2, 6.4, 7.4, 8.1, the second switches 5.3, 6.6, 7.6, 8.3, the third switch 5.4 can be performed according to the scheme shown in figure 3, for the corresponding number of inputs and outputs; inverter 2.1 can be performed on K155LN1; element And 2.5 may be performed according to the circuit shown in FIG. 1.19 and, in particular, on K555LI6; elements And 5.11, 6.9, 7.9 can be performed according to the circuit depicted in FIG. 1.19 and, in particular, on K555LI2; element And 8.8, the first element And 9.2, the second element And 9.3, the third element And 9.4 and the fourth element And 9.5 can be performed according to the scheme depicted in FIG. 1.19 and, in particular, on K555LIZ; the first 4.1, the second 4.2, the third 4.3 and the fourth 4.4 triggers can be performed according to the RS-trigger circuit shown in FIG. 1.42 and, in particular, on K555TP2; the first 4.5, second 4.6, third 4.7 and fourth 4.8 buffer elements can be made according to the circuit depicted in FIG. 1.13 and, in particular, on K155LP10: the first delay line 5.1, the second delay line 5.9, the third delay line 5.10, delay lines 6.5, 7.5, 8.2, 9.6 can be performed as a series connection of an even number of inverters and, in particular, K155LN1; the shaper 10 time intervals can be performed on K555GG, IE, ID; Indication unit 11 can be implemented on KL101 type LEDs (Tereshchuk R.M. et al. Semiconductor receiving and amplifying devices: Reference, amateur radio. -Kiev: Naukova Dumka, 1987, p. 800); RAM 2.7 can be implemented on the chip K537RU8 (Lebedev ON. Memory chips and their application. -M .: Radio and communications, 1990, p. 160) (Massive radio library. Issue 1152).); differentiating circuit 2.6 can be performed according to the circuit shown in FIG. 11.2 (M. Mandl. 200 selected circuits of electronics. Transl. From English. -M.: Mir, 1980, p. 344).

 Thus, the advantages of this device are the ability to work in real time, zero probability of skipping (if there is a priori reliable information about the structure of the package), ease of implementation and modification for any family of communication protocols of the dialogue type. The probability of false alarms depends on the stability of signal reception in the communication channel and the synchronization of the packets at the level of the logical network (and possibly transport) data connection.

Claims (8)

 1. An information retrieval device comprising a memory unit, subtracting a counter, a search strategy register, characterized in that a frequency divider, a switch, first, second, third and fourth selection blocks, a shaper of time intervals and an indication unit are additionally introduced, wherein the output of the frequency divider connected to the first inputs of the memory block, subtracting the counter, the first, second, third and fourth blocks of selection, search strategy register, the outputs of the memory block are connected respectively to the fourth - eleventh inputs of the com mutator, the first output of the subtractive counter is connected to the tenth input of the memory block, the twelfth input of the switch, the eleventh input of the first selection block, the tenth inputs of the second, third and fourth selection blocks, the third input of the search strategy register and is the command output of the device, the second output of the subtractive counter is connected to the eleventh inputs of the second, third and fourth selection blocks, and the third output of the subtracting counter is connected to the twelfth input of the first selection block, the outputs of the switch are connected with the second - ninth inputs of the first, second, third and fourth selection blocks, respectively, the first and second outputs of the first selection block are connected respectively to the first and second input of the switch, the third output of the first selection block is connected to the fourth input of the search strategy register and the fourteenth input of the subtracting counter , the fourth output of the first selection block is connected to the fifth input of the search strategy register, the fourteenth input of the subtracting counter and the input of the time slot former, the fifth output of the the first selection block is connected to the third input of the switch, the sixth output of the first selection block and the first outputs of the second, third and fourth selection blocks, the output of the search strategy register is connected to the first input of the display unit, the tenth input of the first selection block and the fourteenth input of the subtracting counter, the second output of the second the selection block is connected to the second input of the search strategy register, and the second output of the third selection block is connected to the third input of the search strategy register, the second output of the fourth selection block and you the course of the time interval former is connected to the second input of the display unit and the fourteenth input of the subtracting counter, the input of the frequency divider, the second to the ninth inputs of the memory unit and the second to thirteenth inputs of the subtracting counter are respectively the clock frequency input, signal and information inputs of the device.  2. The device according to claim 1, characterized in that the memory unit is made in the form of the first and second totalizing counters, the outputs of which are connected to the corresponding inputs of the random access memory (RAM), the other inputs of which are connected to the corresponding inputs of the switch, and the outputs of the first totalizing counter through the element And are connected to one of the inputs of the second totalizing counter, the other input of which is connected to the corresponding input of the first totalizing counter and to the output of the differentiating circuit, the input of which is connected to Resp input switch and RAM to the input of the inverter, the output of which is connected to the corresponding input of the switch, the other input of the first totalizer, other inputs of the switch and the input of the inverter are the corresponding memory block inputs, outputs, which are the respective outputs of the switch.  3. The device according to one of claims 1 and 2, characterized in that the switch is made in the form of first, second, third and fourth triggers, one of the inputs of which are the corresponding inputs of the switch, and the other inputs are connected to the corresponding inputs of the switch, while the output the first, second, third and fourth triggers connected to one of the inputs of the first, second, third and fourth buffer elements, the other inputs of which are the corresponding inputs of the switch, and their outputs are the corresponding switch outputs.  4. The device according to one of claims 1 to 3, characterized in that the first selection block is made in the form of the first, second, third and fourth decoders, one of the inputs of which is the corresponding input of the first selection block, the other inputs of the first and second decoders are connected to the corresponding outputs of the second switch, and the other inputs of the third and fourth decoders are connected to the corresponding outputs of the third switch, while one of the outputs of the first decoder through the second delay line is connected to the corresponding during the second switch, the input of the first delay line is connected to the corresponding outputs of the second decoder, which are the corresponding outputs of the first block of selection, and the output of the first delay line is connected to one of the inputs of the first switch, the outputs of which are connected to the corresponding inputs of the second and third switches, while the other input the second switch is connected to one of the inputs of the first switch and is the corresponding input of the first block selection, while one of the outputs of the third decoder through t this delay line is connected to the corresponding input of the third switch, one of the inputs of the element And is connected to the corresponding output of the fourth decoder, while the other outputs of the first, second and third decoders are connected to the corresponding output of the fourth decoder and are the corresponding output of the first selection block, the other outputs of the fourth decoder and the output of the element And are the corresponding outputs of the first block of selection, and the other inputs of the first, third switches and the element And are respectively etstvuyuschimi inputs of said first selection unit.  5. The device according to one of claims 1 to 4, characterized in that the second selection block is made in the form of the first, second, third and fourth decoders, one of the inputs of which are interconnected and are the corresponding input of the second selection block, while the other inputs the first decoder connected to the corresponding inputs of the second decoder, and other inputs of the third decoder connected to the corresponding inputs of the second decoder, are the corresponding inputs of the second selection block, and the other inputs of the fourth decoder the torus is connected to the corresponding outputs of the first switch, and the output of the first decoder is connected to the corresponding inputs of the first switch and to the corresponding input of the second switch, the output of the second decoder is connected to the corresponding input of the first, second switches, the summing counter and connected through the delay line to the corresponding input of the first switch, the output of the third decoder is connected to the corresponding input of the second switch, the output of which is connected to the corresponding input of the first Mutator, one of the outputs of the totalizing counter is connected to the corresponding input of the element And, the other input of the totalizing counter and the element And are the corresponding inputs of the second selection block, and the other output of the first switch, the totalizing counter, connected to the output of the fourth decoder, and the output of the element And are corresponding the outputs of the second selection block.  6. The device according to one of claims 1 to 5, characterized in that the third selection block is made in the form of the first, second, third and fourth decoders, one of the inputs of which are interconnected and are the corresponding input of the third selection block, while the other inputs the first decoder, connected to the corresponding inputs of the second decoder, and other inputs of the third decoder, connected to the corresponding inputs of the second decoder, are the corresponding inputs of the third selection block, and the other inputs of the fourth deshi the radiator is connected to the corresponding outputs of the first switch, and the output of the first decoder is connected to the corresponding inputs of the first switch and to the corresponding input of the second switch, the output of the second decoder is connected to the corresponding input of the first, second switches, the summing counter and connected through the delay line to the corresponding input of the first switch, the output of the third decoder is connected to the corresponding input of the second switch, the output of which is connected to the corresponding input of the first switch, one of the outputs of the totalizing counter is connected to the corresponding input of the element And, the other input of the totalizing counter and the element And are the corresponding inputs of the third selection block, and the other output of the first switch, the totalizing counter, connected to the output of the fourth decoder, and the output of the element And are corresponding the outputs of the third block selection.  7. The device according to one of claims 1 to 6, characterized in that the fourth selection block is made in the form of the first, second switches and a totalizing counter, one of the inputs of which are interconnected and is the corresponding input of the fourth selection block, while the output of the totalizing counter through a delay line connected to the corresponding input of the second switch, one of the inputs of the first, second, third decoders, summing counter and element And, interconnected, is the corresponding input of the fourth block of villages and one of the inputs of the first switch is connected to the corresponding input of the And element and is the corresponding input of the fourth selection block, and the other inputs of the first switch are the corresponding inputs of the fourth selection block, while the other inputs of the first and second decoders are connected to the corresponding outputs of the second switch, others the inputs of the second switch and the third decoder are connected to the corresponding outputs of the first switch, one of the outputs of the first decoder is connected to another input totalizer, while the other output of the first decoder, coupled to the output of the second decoder and AND gate and an output of the third decoder, coupled to the other input of the AND are respective fourth block selection output.  8. The device according to one of paragraphs. 1 - 7, characterized in that the search strategy register is made in the form of the first and second elements And, one of the inputs of which are interconnected is the corresponding input of the search strategy register, while the output of the first element And is connected to the output of the fourth element And is the output of the search strategy register, and the output of the second and third elements And through a delay line are connected to the corresponding input of the trigger, the output of which is connected to the corresponding input of the first, second, third and fourth elements And, and ugoy input of the first AND element is connected to the corresponding input of the second, third and fourth AND elements and a corresponding input of a register search strategy, other inputs of the flip-flop, connected with each other, the other input of the third and fourth AND gates are the respective register inputs search strategy.

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