SU1203540A1 - Device for checking wiring - Google Patents

Description

".1203540

The invention relates to computing technology and automation and can be used with automated control systems for automatically checking the quality of electrical installation 5 with control of an electronic computer (computer),

The aim of the invention is to expand the class of tasks. ABOUT

Figure 1 shows the functional diagram of the proposed device; in FIG. 2, a block diagram of a computer operation algorithm at the interface with the device in FIG. 3 is a time diagram of the device operation.

The device (Fig. 1) contains groups 1 of decoders 2 of communication with the object of the polling switches 3, decoders 4 and 5 of the reference and current addresses, comparison circuits 6 and 7, registers 8 and 9 of the reference and last addresses, counter 10, AND elements - NOT 11 and 12, element 13, control register 14, trigger 15, pulse generator 16, element 17, control word input 18, reset signal input 19 ready 15

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output, the current address output 20, the device readiness signal output 21 and the device information input 22.

The device monitors electrical connections, monitors noise immunity, and also self-monitors successively a sequence of reference address recording modes with search modes. The choice of the type of control and mode control is performed by software from the output of the computer through register 14.

The device works as follows.

The principle of installation control, adopted in the device, is based on the sequential identification of electrical or parasitic (when monitoring noise immunity) connections of each installation point (reference point) with all others and excluding previously tested points from further monitoring. The addresses of the control points (reference addresses) are programmed from the computer at input 22 and are recorded simultaneously in register 8 and in counter 10, which are set to write mode by a signal from the output of register 14. the last monitored point of installation (the last), depending on the number of points in the object of control (also arrives at input 22 and is written to register 9, the mode

records of which are set by a signal from the output of register 14. Subsequently, until the end of the control, register 9 is in the storage mode.

A control computer enters control words at input 18 into register 14. In the first discharge of the control word, the mode of operation of the device is set (communication control mode or noise immunity test), in the second discharge, the modes of operation of the register 8 and the counter 10 (write a parallel code), and in the third discharge the mode

register 9 (write parallel code).

After the reference address is written, register 8 is placed in storage mode, and counter 10 is in counting mode. The reference address from the output of register 8, after decryption, is converted into a sufficiently amplified logical O signal at the corresponding output of the decoder 2 of one of groups 1, which through the electrically connected circuits of the object being monitored goes to several inputs of the switches 3. The remaining inputs of the switches remain logical. one. Since counter 10 also recorded the reference address from its output coming to the inputs of the decoder 5 and the address inputs of the switches 3, the signal from the output of the decoder 2 (reference point) passes through the switch 3 to one of the inputs of the element AND NOT 11, open on the remaining inputs . At its output, a logical 1 signal appears, which arrives at the first information input of trigger 15, connected according to the AND circuit with the second information input locked at this time by a logical signal O from the output of the comparison circuit 6, since equal numbers of addresses arrive at its inputs and to the first input of the element And 17, locked on the second input by a signal from the first output of the register 14.

Therefore, the trigger 15, which is triggered by the cutoff of the synchronization pulses when the next sync pulse passes from the generator 16 output through the AND 13 element to the synchronization input, remains in the zero state. Element And 13, open a logical signal 1 from the inverting output of the trigger 15, passes the next pulse from the output of the generator 16 to the counting input of the counter 10, which

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calculates the leading edge of the pulse and adds one to the previously recorded reference address.

According to the new address on the address inputs, switch 3 commutes a signal from the next point of installation of the control object to the input of the NAND 11 element.

If this point is not connected to the reference point, then the information input of the trigger 15 through the switch 3 and the element IS-NOT 11 receives a logical O signal, and if it is connected, then the logical 1. The second information input of the trigger 15 from the output of the comparison circuit 6 also logical 1 comes in because its inputs are different addresses. Therefore, in the case of the existence of an electrical connection, the trigger 15 is cut off in a single state by a cut of the clock pulse. At its inverting output is set

logical o

blocking the passage of pulses through the element I 13 and the counter 10 stops. At the direct output of the trigger 15 is set logical

 one

incoming

on output 21 to the input of the control computer as a ready signal, having received the computer, reads the address from the output of counter 10 via bus 20 and issues a ready readout signal on input 19. In this case, the trigger 15 is set to the zero position and prevents the pulses from passing to the counting input of the counter 10, which counts the leading edge of the next sync pulse.

Thus, the search for electrical communications continues until the address at the output of the counter 10 coincides with the last address recorded in the register 9. In this case, the output of the comparison circuit 7 is a logical signal O, which after passing through the AND-HE element 11 goes to information input tri1-ger 15 as logical 1. Trigger 15 is set to one, stops counter 10, and issues a ready signal on output 21. Control computer on outputs 20 reads the last address and perceives it as the end of the circuit, and then on at 18 through the register 14 sets the register 8 and counter 10 in the recording mode, terminal 22 enters another reference address and a terminal 19 - readiness reset signal. So

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therefore, the starting point for the next search cycle is the next reference point. Therefore, the number of controlled points decreases.

5 as the reference address approaches the last ry recorded in register 9. In addition, the control computer excludes from the 4 reference data those points whose circuits were defined in the previous polling cycles.

The processing of the information received as a result of the check is determined separately. Information can be recorded in the computer memory as an e-mail, can be viewed completely through output devices, or only erroneous circuits can be output (if there is a reference program). Information output is carried out in

20 real addresses - with the indication of the number of the connector and the contact.

After checking the electrical installation and eliminating errors, noise immunity is monitored.

25 installation. To do this, after the last and reference addresses are written, input 18 sends a signal to register elements 17 and AND-NOT 12 through register 14. An output from AND-NO 12 from the output of generator 16 to the control input of decoder 4 is applied. much higher frequency clock. The decoder 4, and therefore the decoder 2 of one of the groups 1, are closed and opened with the appropriate frequency. Therefore, during one period of the clock pulse through element I 13, a series of high-frequency pulses passes through element IS-NOT 12. As a result of the mutual influence of the conductors of the tested installation in circuits with low noise immunity, impulse interferences occur at the input of the commutator 3 one of the group 1. At the moment when the switch 3 tos the point of such a circuit, the interference pulses pass through the switch 3, the element AND NOT 11, the element 17, open from the output of the register 14, to the input of the installation in 1 trigger 15, who works and remains pours the counter 10.

The output of the device 20 is set to the address of the mounting point belonging to the circuit with low noise immunity. Upon receipt of a ready signal from output 21, the control computer prohibits the passage of high-frequency pulses.

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owls through the elements AND-NOT 12 and AND 17, reads the address from output 20 and resets the readiness. After the arrival of the next sync pulse to the counting input of the counter 10, the computer again permits the passage of high-frequency pulses through the elements AND 12 and 17, and the search process continues.

Together with the low noise immunity circuit points, the device detects electrically connected points with the installation. Since the installation has been verified previously and there is a reference program, after comparing

The computer outputs only spurious link addresses.

Thus, the proposed device 5 has more functionality than the known one, since it permits control of the noise immunity of the installation. In addition, due to the 10-counting use of computer technology for receiving and outputting information, the process of detecting erroneous connections is simplified and the time for conducting control is reduced.

"ABOUT

BbiSofi and recording mode 8 o / 1 /

Record pos / gednogo and supporting adpecoS 6 elements 8,9, fO

Permission cvema (survey)

Code reading

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Claims (1)

DEVICE FOR CHECKING THE ELECTRICAL INSTALLATION, containing the reference address register connected to the information inputs of the reference address decoder and communication decoders with the group object, the gate inputs of which are connected to the output group of the reference address decoder, the group of polling switches, the current address decoder, the first comparison circuit, the first an input connected to the output of the register of the last address, a counter whose output is connected to the input of the decoder of the current address, the group of outputs of which are informational the counter output is connected to the address inputs of the group polling switches, the information inputs of which are connected to the outputs of the corresponding communication decoders with the group object and the corresponding group of control outputs of the device, the counter input of the counter is connected to the output of the first element And, the first input of which is connected to the first output of the pulse generator, characterized in that, in order to expand the class of tasks to be solved, a second comparison scheme, a control register, a second AND element, a trigger, and two AND-NOT elements are introduced into it, The reset input and direct trigger output are respectively the ready signal reset input and the device ready signal output, the inverse output and the sync output are connected respectively to the second input and output of the first AND element, the output of the first AND element is NOT connected to the first information input of the trigger and the first input of the second AND element, the output of which is connected to the trigger installation input, and the second input - to the first output of the control register and the first input of the second AND-NOT element, the output and second input of which are connected respectively With the gate input of the reference address decoder and the second output of the pulse generator, the group of inputs of the first NAND element is connected to the output of the first comparison circuit and the outputs of the group polling switches, the first input of the second comparison circuit is connected to the counter output and the current device address, and the second input and output - respectively, with the output of the reference address register and the second trigger input, the information inputs of the reference address register and counter are connected to the information input of the device and inf the input of the register, the last address, and the recording control inputs with the second output of the control register, the third output of which is connected to the write control input of the register of the last address, and the input is the input of the control word of the device.