SU1698842A1 - Electrical wirings connections tester - Google Patents

Abstract

The invention relates to instrumentation technology and can be used to control wiring connections in the manufacture of electronic and electrical equipment. The purpose of the invention — an increase in the monitoring speed — is achieved by excluding the measurement node from accessing points of the test object, the connections of which have already been identified, and the convenience of processing the counter-trigger results, due to recording information into the memory with a sign of the detected circuit. The device contains terminals 1 for connecting a control object, activating 2 and polling 3 switches, activating with 8

Description

The invention relates to instrumentation technology and can be used to control wiring connections in the manufacture of electronic and electrical equipment.

The purpose of the invention is to increase the monitoring speed by eliminating the access of the measuring node to the points of the test object, the connections of which have already been detected, and the convenience of processing the results of the monitoring due to recording information into the memory with a sign of the detected installation circuit.

FIG. 1 shows a functional diagram of the device for monitoring electrical connections; in fig. 2 - control object diagram.

A device for monitoring electrical installation connections contains n terminals 1 for connecting a control object, where n is the number of elements of the control object, activating 2 and interrogating 3 switches, activating 4 and interrogating 5 counters, census block 6, control block 7, source 8 testing voltage analyzer 9, memory block 10, first comparison block 11, resistor 12, first terminal 13 Start, second terminal 14 General view, block 15 of control results processing, element 16 AND-OR, second 17 and third 18 comparison blocks, first 19 and second 20 inverter , A register 21, volume control object. Each of the n terminals 1 for connecting the control object is connected to the corresponding output of the activating 2 and polling 3 switches, the control input of the activating 2 and polling 3 switches is connected to the output of the activating 4, respectively, and polling 5 counters, the counting input of the activating counter 5 is connected to the first output of the unit 7 controls

15

thirty

35

the output of the census block 6 is connected to the information input of the polling counter 5, the first output of the testing voltage source 8 is connected via a resistor 12 to the information input, the input of the analyzer 9 and the activating switch 2, the second output to the second RO element 14 General output, to the information input the interrogating switch 3 and the second input of the first comparison unit 11, the output of the activation counter 4 is connected to the informational inputs of the memory unit 10 and the census unit 6, the second inputs of the I-1SHI element 16 and the second comparison unit 17, The first input of the element 16 I-1SH11 is connected to the second input of the control unit 7, the input and output of the first inverter 19 and the third comparison unit 18, respectively, the first terminal 13 Start is connected to the first input of the control unit 7, the third input of which is connected to the third control input of the unit 6 census, with the output of the first comparison unit 11, the input of the second inverter 20, the output of which is connected to the fourth input to the control unit 7, the second and third outputs of which are connected respectively to the first and second control inputs of the census block 6, output the interrogating counter 5 is connected to the third input of the AND-OR element 16 and the second input of the third comparison unit 18, the first input of the second 17 and third 18 comparison blocks are connected to the output of the control object volume register 21, the output of the second external block 17 is connected to the control input of the block 15 processing the control results, the information input of which is connected to the output of the memory block 10 and the first input of the first block 55 11 of the comparison, the fourth output of the control block 7 is connected to the counting input of the polling counter 5, the address input of the block 10 memory connected

50

with the output of the element 16 AND-OR, the fourth input of which is connected to the output of the first inverter 19, the input of the memory unit 10 is connected to the output of the analyzer 9, the control input of which is connected to the fifth output of the control unit 7. The control unit 7 comprises the first 22 and second 23 OR elements, the first 24, the second 25, the third 26 AND elements, the 27 clock pulse generator First in; unit is connected to the first input of the first element 22 OR and the second output of the block, the first output of which is connected to the output of the first

element 22 OR, the second input of which elements I9 the first input of which is 7c counter). In the register 21 volume ..-- ttljll / L

It is connected to the third output of the block and the output of the first element 24 AND, the second input of which is connected to the second input of the block, the fourth output of which is connected to the output of the second element 23 OR, the third and fourth inputs of the block are connected to the second inputs of the second 25 and third respectively

connected to the low-frequency and high-frequency outputs of the generator 27 clock pulses, the output of the second element 25 AND connected to the fifth output of the unit and the first input of the second element 23 OR, the second input of which is connected to the output of the third element 26 AND, the first input of the first element 24 OR connected to the high-frequency output of the generator 27 takti-tovyh pulses.

Consider the operation of the device for controlling electrical connections using an example of some conventional control object, the circuit of which is shown in FIG. 2

In the initial state of the memory block 10, the activating 2 and polling 3 switches are reset. The Start signal to the activating counter 4 counter through the first element OR 22 is recorded one unit, which by the same signal Start via block 6 is rewritten into the interrogating 5 counter, the unit code from the activating counter. Thus, the information input of the analyzer 9 will be connected to the general output 14 of the device t. The e-signal at the information input of the analyzer 9 will have a zero level. Since in the initial state the memory block 10 is reset, the output of the first comparison block 11 will be an equality signal, which will open the second element 25. And the pulse from the low frequency output of the clock generator 7 clock pulses with its leading edge will start the analyzer 9, at the information input of which the test voltage is zero (a sign of the presence of a connection). The analyzer 9 provides a recording signal to the input of the memory block 10, according to which a unit is recorded in the first unit of block 10 — there is a unit at the information input of the memory block 10 (output of the activating counter 4), and the address input is also unit (the output of the interrogator

20

thirty

The control number is set to 21 (1 more than the volume of the object). The equality signal at the output of the third block 18 is no comparison, at the output of the first inverter 19. a high level (logical 1), which passes the output code of the interrogating counter 5 through the AND-OR 16 element to the address input of the memory block 10. the second element AND 35 25, having passed through the second element OR 23 to the counting input of the interrogating counter 5, increases its content by one, the interrogating switch 3 will be triggered and the second point of the control object will be connected to the general output 14 of the device. Since in the object under consideration the first and second points are not connected, i.e. In this cycle, the first point of the control object will be in a break with the general output 14 of the device, then at the information input of the analyzer 9, the testing voltage will be high (a sign of non-communication). Pe40

45

ka 4, arriving at the activating remote front of the next pulse with

ten

88426

Thus, the information input of the analyzer 9 will be connected to the common output 14 of the device, i.e. the signal at the information input of the analyzer 9 will have a zero level. Since in the initial state the memory block 10 is reset, at the output of the first comparison block 11 there will be an equality signal that will open the second element AND 25. The pulse from the low frequency output of the clock generator 7 clock pulses its front edge into the analyzer 9, at the information input of which the test voltage is zero (a sign of the presence of a connection). The analyzer 9 provides a recording signal to the input of the memory block 10, in which a unit is recorded in the first cell of the block 10 — the information input of the memory block 10 is one (output of the activating counter 4), and the address input is also one (the output of the polling

15

20

counter). In the register volume 21 volume ..-- ttljll / L

The control number is set to 21 (1 more than the volume of the object). The equality signal at the output of the third comparison unit 18 is absent, at the output of the first inverter 19. a high level (logical 1), which passes through the AND-OR element 16 to the address input of the memory block 10, the output code of the polling counter 5. The falling edge impulses the output of the second element 25, having passed through the second element OR 23 to the counting input of interrogating counter 5, will increase its contents by one, the interrogating switch 3 will be triggered and the second point of the control object will be connected to the general output 14 of the device. Since in the object under consideration the first and second points are not connected, i.e. In this cycle, the first point of the control object will be in a break with the general output 14 of the device, then at the information input of the analyzer 9, the testing voltage will be high (a sign of non-communication). Pe

mutator 2, triggers it, as a result of which the information input of the activating switch 2 is connected to the first point of the control object. Similarly, it works

interrogating switch 3, also connecting its information input to the first point of the control object.

the low-frequency output of the oscillator 7 clock ims will start the analyzer 9, but due to the high testing voltage on its information input, the write signal to the memory block 10 will not be generated. The second cell of memory block 10 will remain zero. Similar work continues

until the seventh point code is set in the interrogating counter 5. The third, fourth, fifth, and sixth cells of the memory block 10 remained zero. After the seventh point code is set in the interrogating counter 5, the interrogating switch 3 connects the seventh point of the control object to the common output 14 of the device. Since the first and the seventh points are interconnected in the object under consideration, the test voltage at the information input of the analyzer 9 is set to a low level. A unit will be recorded in the seventh cell of the memory block 10 (the output of the activating counter 4).

Similarly, the operation continues until the twenty-first point of the control object is connected.

After the twenty-first point code is set in the polling counter 5, the third comparison unit 18 is triggered, the equality signal from which through the AND-OR element 16 disconnects from the address input of the memory block 10 the output of the polling counter 5 and connects the output of the activation counter 4. The same signal equality will open the first

ten

15

20

25

In the third and fourth cells of the memory block 10, the code of the second point of the control object will be written, and the fifth and six ki will remain zero. When writing to the interrogating counter 5, the code of the seventh point at the output of memory block 10 corresponds to the code of the first point recorded in the seventh cell of memory block 10 in the first cycle. A low signal from the output of the first comparison unit 11 will close the second element I 25 and, after passing through the second inverter 20, will open the third element AND 26. The pulse from the high-frequency output of the generator 7 clock pulses, the third element AND 26 and the second element OR 23, will increase the content of the interrogating counter 5 by one. The eighth cell will be connected to the output of the memory block 10. Since a unit was recorded in it in the first polling cycle, one more pulse from the high-frequency generator of the 7 clock pulses will be passed to the polling counter 5. The ninth point of the control object will be checked. Similarly, work continues until the end of the cycle.

Once established in the polling

element 24. The impulse from the high-frequency counter of the code of the first square cell

generator output 7 clock pulses ™, w ™, „™,

owls, go through the first element and 24

and the first element OR 22 to the counting input of the activating counter 4, with its leading edge, will increase its contents by one. The address of the second cell is set at the address input of the memory block 10. Since it remained zero after the first polling cycle, the equality signal, which will open the census block 6, is output from the first comparison block 11. The back edge of the pulse from the output of the first element And 24 will be a census of the contents of the activating counter 4 into the polling counter 5. The equality signal at the output of the third comparison unit 18 is removed and the output of the activating counter 5 is connected to the address input of the memory block 10.

As described above, the output of the activating counter 4 is connected to the address input of the memory block 10. The pulse from the high-frequency generator output 7 clock pulses, passing through the first element 24 and the first element OR 22, will increase by one the content of the activating counter 4 output memory unit 10 connects a third cell, in which in the second

40 cycle was recorded code of the second point. In this case, the low level of the signal from the output of the first comparator unit 11 will not allow the census to the polling pulse from the high-frequency output of the generator of the 7 clock pulses, will increase the content of the activation counter 4 by one. A fourth cell is connected to the output of the memory block 10, in which the code of the second

The first element And 24 will close. Device - 50 cells. In this case, the census also took a state similar to the first cycle of the first cycle (survey, with the only difference that the code of the second point of the control object is set at the address and information inputs of memory 10. In the second cell of memory 10 The second point code will be written in. Next, the operation of the device follows the above algorithm.

does not happen, another impulse will go to activating counter 4. To the output of memory block 10, a cell is connected which is in the 55 zero state. At the output of the first comparison block 11, the equality signal will occur, the contents of the activating counter 4 will be copied to the interrogating counter 5.

five

0

five

In the third and fourth cells of the memory block 10, the code of the second point of the control object will be written, the fifth and sixth cells will remain zero. When writing to the interrogating counter 5, the code of the seventh point at the output of memory block 10 corresponds to the code of the first point recorded in the seventh cell of memory block 10 in the first cycle. The low level of the signal from the output of the first comparison unit 11 will close the second element I 25 and, having passed through the second inverter 20, will open the third element AND 26. The pulse from the high-frequency output of the generator 7 clock pulses, passed the third element AND 26 and the second element OR 23, will increase by unit contents of the interrogating counter 5. An eighth cell is connected to the output of memory block 10. Since a unit was recorded in it in the first polling cycle, one more pulse from the high-frequency generator of the 7 clock pulses will be passed to the polling counter 5. The state of the nine points of the control object will be interrogated. Similarly, work continues until the end of the cycle.

Once established in the polling

first cell code counter

  l ™ ,, w ™, „™,

The output input of the activation counter 4 is connected to the address input of the memory block 10, as described above. The pulse from the high-frequency generator output 7 clock pulses, passed through the first element 24 and the first element OR 22, will increase by one the content of the activation counter 4. Output memory unit 10 connects a third cell, in which in the second

cycle was recorded code of the second point. In this case, the low level of the signal from the output of the first comparison unit 11 will not allow the census to the polling pulse from the high-frequency output of the generator 7 clock pulses, will increase the contents of the activation counter 4 by one. A fourth cell is connected to the output of the memory block 10, in which the code of the second

cells In this case, the census is also

does not happen, another impulse will go to activating counter 4. A memory cell is connected to the output of the memory unit 10, which is in the zeroed state. At the output of the first comparison block 11, the equality signal will occur, the contents of the activating counter 4 will be copied to the interrogating counter 5.

The fifth fifth cell of the memory block 10 will write the code of the fifth point. Further operation of the device is similar.

When the twenty first pulse arrives at the activating counter 4, the second comparison block 17 is triggered, by a signal from which the control result processing block 15, for which a computer can be used, writes the contents of the memory block 10 into its own memory. In a computer, either the Asrmicroning of the table of connections of the control object occurs, or the comparison of the entered information file with the reference one and the formation of a table of differences.

Claims (2)

1. A device for controlling electrical installation connections, containing p terminals for connecting the object to a control, where p is the number of elements of the control object 25, activating and interrogating switches, activating and interrogating counters, census block, control unit, test voltage source, analyzer , the memory unit, the first comparison unit, the first Start terminal, the second terminal Common terminal, the control results processing unit, each of the n terminals for connecting the test object is connected to the corresponding output active the switching and polling switches, the controlling input of the activating and polling switches are connected to the output of the activating and polling counters, respectively, the counting input of the activating counter is connected to the first output of the control unit, the output of the census block is connected to the information input of the polling counter, characterized in that control speed, an I-ШШ element, the second and third comparison blocks, the first and second inverters, the volume register of the control object, the re- the first, the first output of the test voltage source is connected through a resistor to the information input of the analyzer and the activating switch, the second output is connected to the second terminal 35 40 45 50 55 conclusion, with the information input of the polling switch and the second input of the first comparison unit, the output is active five 0 0 five The sighting counter is connected to the information inputs of the memory block and the census block, the second inputs of the I-1SHA element and the second comparison unit, the first input of the AND-OR element is connected to the second input of the control unit, the input and output of the first inverter and the third comparison unit, respectively, first terminal The start is connected to the first input of the control unit, the third input of which is connected to the third control input of the census block, to the output of the first comparison unit, the input of the second inverter, the output of which is connected to the fourth input of the control unit. and the control, the second and third outputs of which are connected respectively to the first and second control inputs of the census block, the output of the polling counter is connected to the third input of element II-OR and the second input of the third comparison block, the first input of the second and third comparison blocks are connected to the register output the volume of the control object, the output of the second comparison unit is connected to the control input of the processing unit; the counter 4 whose information input is connected to the output of the memory block and the first input of the first block is compared to the fourth output of the control unit is connected to the counting input of the polling counter, the address input of the memory unit is connected 5 with the output of an AND-OR element, the fourth input of which is connected to the output of the first inverter, the input of the memory unit is connected to the output of the analyzer, the control input of which is connected 0 with the fifth output of the control unit. 2. The device according to claim. Characterized in that the control unit contains the first and second elements OR, the first, second and third 5 AND elements, clock pulse generator, while the first input of the block is connected to the first input of the first OR element and the second output of the block, the first output of which is connected to the output of the first OR element, the second input of which is connected to the third output of the block and the output of the first AND element , the input of which is connected to the second input of the block, the fourth output of which is connected to the output of the second element OR, the third and fourth inputs of the block are connected to the second inputs of the second and third elements AND, the first inputs of which 0 five connected respectively to the low-frequency and high-frequency outputs of the clock, the output of the second element And is connected to the fifth output of the block and the first input of the second Y m / g c 45  S fi / ff} ftJfStff FIG. 2 element OR, the second input of which is connected to the output of the third element AND, the first input of the first element OR is connected to the high-frequency output of the clock generator. 20