SU1522217A1 - Device for connection of k processors with group of subscribers - Google Patents

Abstract

The invention relates to computing and can be used to control the exchange of information between the processors of the computer control panel and the nodes of the electronic computer. The aim of the invention is to increase productivity by ensuring the simultaneous operation of several processors with subscribers. The device contains an address switch, input and output switch, maintenance gate switch, subscriber number comparison node, exchange unit consisting of control node, address buffer register, information buffer register, subscriber number code buffer register, number code register, subscriber number decoder . 1 hp ff, 7 ill.

Description

The invention relates to computing and can be used to control the exchange of information between the processors of the computer control panel (hereinafter, the control processors) and the nodes of the electronic computer (hereinafter the subscribers).

The aim of the invention is to increase productivity by ensuring the simultaneous operation of several processors with subscribers.

Fig about 1 presents a functional diagram of the device; Figs 2, 3, 4 are functional diagrams of the control node, the output information switch, the subscriber number comparison node; FIGS. 5, 6, .7 are timing diagrams of control signals generated at the outputs of the control nodes for implementing

in the device according to the choice of the subscriber, transmission and reception of information,

The device contains (figure 1) K blocks 1 exchange

Each exchange unit 1 contains a buffer register 2 addresses, a buffer register 3 information, a control node 4, a buffer register 5 of the subscriber number code, register 6 of the subscriber number code, a decoder 7 of the subscriber number. The device also contains an address switch 8, an output information switch 9, a maintenance strobe switch 10, an input information switch 11, a subscriber number comparison node 12

FIG o denotes the inputs, outputs, and intercoms of the device 13-37.

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The control unit 4 contains, (figo2) shift register 38, an AND-OR element 39, elements OR 40, 41, elements AND 42-49, triggers 50.51. The output information switch 9 contains (figs) a group of elements AND 52, a group of elements OR 53.

The subscriber comparison node 12 contains (FIG. 4) the group of decryptor jTOpos 54 subscriber number codes, the group EXCLUSIVE OR 55, the element OR 36 o

In FIG 3.4, the number of processors K is indicated, the information width H, the number of subscribers Mo

The buffer register 2 of the address is intended to store the address at which the subscriber has to write to or read the information that arrives at the address input of the device from the control processor.

Buffer register 3 information. pre, assigned to receive and temporarily store the subscriber's number or information code that is fed to the formation input 13 of the control processor or to receive and store information received from the subscriber through the switch 11 of the input format depending on the presence of control signals

Predictor control node 4 for receiving control signals Trigger Receive, Transmit J Select the subscriber from the control processor, respectively, through inputs 14-17, the clock signal through the code 18, signal 29, Record the number of the subscriber from the comparison node, and generate 23 correct signals , 32, 33, 34, 35, 36, 37, designed to implement the algorithm of the device, and: also signal 31 Zanto, Buffer register 5 of the number code: the subscriber is designed to receive and temporarily store the code of the subscriber number, received one of the buffer register 3 info mation and transmitting it to the register I 6 subscriber number and code comparing unit 12 abonenta- rooms.

Register. 6, the subscriber number code is for receiving and storing i of the subscriber number code, received from the buffer register 5 of the subscriber number code, and transferring it to the decoder; 7 subscriber numbers.

Node 12 comparing the number of subscribers; that is intended to receive and compare

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codes of received and occupied subscriber numbers and issuing a prohibitory signal in case of codes coincidence.

The address switch 8 is used to receive 2 addresses from the buffer registers and transfer them to subscribers on the chains of the device’s 20 output outputs, depending on the control signals on the chains 27 of the output switch 9, to receive information from the buffer registers 3 and transmit information on circuits 22 information outputs depending on control signals on 27o circuits

Accompanying gate switch 10 is used to receive and transmit to the subscribers of the escort gate through the circuits 24 escort gate outputs of the device depending on the control signals on the circuits 27 o

Ko1 Shooter 1 1 input information is designed to receive from subscribers and transfer information for control processors to registers 3 1 Information on chains 2.6 output information of switch 11 of input information depending on control signals on chains to 27

The device works as follows

Before the exchange begins, the device is connected to the subscriber, for which the subscriber's code is set up from the control processor to the information inputs 13 of the device, the control node 4 receives signals to input 14 and input 17o. By the signal at input 14, the shift register 38 begins to generate a sequence of clock pulses o The clock signal from the first output of the shift register 38 at the output 32 of the element OR 40 generates an information recording control signal (subscriber number code) in the buffer register 3 information from the control percent Jessor ,, The clock signal from the second step of the shift register 38 at the output 36 of the element 48 forms the control signal for entering information from the information register 3 into the buffer register 5 of the subscriber number code. Information from register 5 of the subscriber number code goes to the corresponding group 28 of information inputs subscriber number comparison node 12, where it is compared

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with information of other registers 5 of the subscriber number code. If the information matches, the node 12 compares the subscriber number and generates a single signal at output 29, which is fed to the input of trigger 51 of control node 4. By the clock signal from the third output of the shift register 38 at the output of the element 47 the signal supplied to the synchronous input of the flip-flop 51 of the control unit 4, which sets the flip-flop 51 into a single state, the unit output of which goes to the output 31 of the device, communicating to the control processor that it is busy subscriber. A clock signal from the fourth output of the shift register 38 at the output 35 of the element And 49 forms a reset signal, which resets the buffer register 5 of the subscriber number code, and does not connect to the subscriber,

The clock signal from the fourth output of the shift register 38 and the zero state of the trigger 51 at the output of the element 37 And 44 generates a control signal for entering information from buffer register 5 of the subscriber number code to register 6 of the subscriber number code. Information from register 6 of the subscriber number code is decoded by the decoder 7 subscriber numbers and enters the group. 27 control inputs of the address switches, output information, tracking strobe and input information, connected to the corresponding subscriber. At this, the connection mode to the subscriber ends. The timing diagram of the formation of control signals at the outputs of the control unit 3 when selecting a subscriber is shown in

By transmitting the information, the control processor sends to the control unit 4 signals to inputs 16 and 14, respectively. Control signal 4 starts up the control signals and in accordance with the

the complexity of the control signals at the outputs 32, 34, 23

The signal at input 14 of the shift register 38 begins to generate a sequence of clock signals. By the clock signal from the first output of the shift register 38 at the output 32 of the element OR 40 an information recording control signal is generated

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to the buffer register 3 information from the control processor, which is fed to a group of inputs 21 of the output switchboard and depending on the decrypted code of the subscriber number, is sent to one of the group 22 informational outputs of the device to the subscriber. By the second clock signal from the second output of the shift register 38 at the output of the control unit OR 39 of the control unit 4, a signal is generated by which the address of the register of the subscriber to which the transmitted and The information must be received from the output of the buffer register 2 of the address via the switch 8 of the address and the connected output from the group of 20 output outputs depending on the decrypted code of the subscriber’s number is transmitted to the connected subscriber, and the signal from the second output of the shift register 38 goes through element 46 to the input of the trigger 50, which is set to a single state on the falling edge of this signal. The output signal from the trigger 50 of the control unit 4 via the strobe switch 10 of the tracking device and connected, depending on the decrypted subscriber number code, is an output from a group of 24 strobe output outputs, goes to the selected subscriber and gates receiving information transmitted through the device at the specified address On the falling edge of the fourth clock signal from the fourth output of the shift register 38 arriving at the synchronous input of the trigger 50 through the cut element OR 41, the trigger 50 is set to the zero state. In this mode, the transfer rmatsii from the control processor to the subscriber terminates

  Dp of receiving information, the control processor issues to control unit 4 signals to inputs 15 and 14, respectively, from which it generates control signals at outputs 34,33, 23 (Fig.7). The signal at input 14 of the shift register 38 begins to generate a sequence of clock signals. The clock signal from the first output of the shift register 38 at the output 34 of the I-IPI element 39 generates a control signal for receiving the address from which the control processor. at the entrance to the buffer register 2, the register address of the subscriber from which information is to be read is recorded, and from the output of buffer register 2 of the address through the switch 8, the address and the connected output from the group 20 of address outputs are output to the connected subscriber depending on the code of the subscriber number to be decoded. The second clock signal from the second output of the shift register 38 through the element 46 and the element OR 41 generates control signals that set the trigger 50 to one state from the output of which, through the output 23, the tracking strobe signal is generated, which through the switch O of the tracking strobe and connected to Depending on the code of the subscriber's number to be decoded, the output from the group 24 of the gate outputs of the escort goes to the selected subscriber, gating the output of information from the subscriber to the zannuyu address. Information from the subscriber through the connected input from the group 25 of information inputs of the device through the encoder 11 of the input information is fed to the second 1P1 information input of the register Pp. The signal at the output 33 of the control unit 4 is formed at the output of the element 45 from the third output of the shift register 38, which receives } Formation in the buffer. register 3 information, and from output 30 enters the control processor "On the falling edge of the fourth clock signal from the fourth output of the shift register 38, received on the synchronous input of the trigger 50 through the element

OR 41, trigger 50 is set at. zero state on this reldam

ma information from the subscriber to the control processor is terminated,

Claims (1)

Invention Formula 50 1, An interface for K processors with a subscriber group containing an address switch, a strobe escort switch, a first exchange unit including an address buffer register, an information buffer register, a subscriber number code register, a subscriber number decoder, a control node, and information groups the outputs of the address switch and the strobe gateway switch 0 five 0 five 0 five 0 The device output groups for connecting respectively to the address inputs and gating inputs of group subscribers, the information input of the address buffer register, the first information input and the first information output of the first information exchange buffer register of the first exchange unit are the inputs and outputs of the device for connection respectively to the address output, information output and the input of the first processor, the first, second, third, fourth inputs of the log condition, the synchronous input and the first output of the control unit of the first block They are the inputs and outputs of the device for connecting, respectively, to the start-up, reception control, transmission control, sampling control, control line-out, and readiness input of the first processor, in order to improve performance by ensuring simultaneous operation several processors with subscribers, K-1 exchange units are entered into the device, output information switchboard, input information switchboard, subscriber number comparison node, and a buffer register is entered into each exchange block the subscriber number code, the group of information outputs of the cog-mutator of the output information and the group of information inputs of the input information switch form the groups of outputs and inputs of the device for connecting respectively to the information inputs and outputs of the subscribers of the group, the information input of the buffer register of the address, the first information input and The first data output of the buffer register of the information block of the i-th exchange block (i 2, K) are the inputs and outputs of the device and connected to the output output respectively. y, the information output and input of the i-ro processor, the first, second, third, fourth logical conditionals, the sync input and the first output of the control unit of the i-ro exchange unit are the inputs and outputs of the device for connecting respectively to the start outputs, receive control, transmission control, sampling control, sync output and i-ro ready input. processor, the information output of the buffer register of the address of the j-ro of the exchange unit (j 1, k) is connected to the j-th information input of the address switch, the j-th control input of which is connected to the j-MH control inputs of the input information switch, the output switch information, a gate stub switch and with the output of the decoder number of the subscriber's j-ro exchange unit, the second information output of the buffer information register J-ro of the exchange unit is connected to the information input of the buffer register of the subscriber number code J-ro of the exchange unit and CJM info the output information switch input, the second output of the control unit J-ro of the exchange unit is connected to the JM information input of the strobe switch; the second information input of the information buffer information register J-ro of the exchange unit is connected to the information output switch information input information output buffer of the subscriber number code J The -ro of the exchange unit is connected to the information input of the subscriber number code register J-ro of the exchange unit and with the JM information input of the subscriber number comparison node, the output to The first is connected to the fifth inputs of the logical condition of the control nodes of all interchange units; in each exchange block, the information input of the subscriber number decoder is connected to the information output of the subscriber number code register, whose recording input is connected to the third output of the control node, the fourth output of which is connected to the input recording the buffer register of the subscriber number code, the installation input of which is connected to the installation input of the subscriber number code register and to the fifth output of the control node, the sixth, seventh and eighth the outputs of which are connected respectively to the input of the record of the buffer address register, with the first and second inputs of the record of the buffer register of information. 2 The device according to claim 1, of t. L. That the control node contains a shift register, two triggers, eight AND elements, two OR elements, an AND-OR element, and 0 five 0 five 0 five 0 five 0 the sync input and the information input of the shift register are respectively the sync input and the first input of the logical condition of the node, the first input of the first element AND is connected to the first input of the AND-OR element and is the second input of the logical condition of the node, the first input of the second element AND is connected to the second input of the AND element -ShI is the third input of the logical condition of the node, the first input of the third element And is connected to the first inputs of the fourth, fifth elements And, and is the fourth input of the logical condition of the node, information in One of the first trigger is the fifth input of the logical condition of the node, the unit output of the first trigger is connected to the first input of the sixth AND element and is the first code of the node, the outputs of the second trigger, the seventh, third, sixth AND element, AND-OR element, the first AND element The first OR element are respectively BTopEM ,. the third, fourth, fifth, sixth, seventh, eighth outputs of the node; in the control unit, the first and second inputs of the first OR element are connected respectively to the outputs of the second and fifth AND elements, the second inputs of which are connected to the third input of the element and the first input of the shift register, the second output of which is connected to the fourth input of the I-IPI element, with the second input of the third element I and with the first input of the eighth element And, the output of which is connected to the information input of the second trigger and the first input of the second element OR, the output of which is connected to the synchronous input of the second trigger, the third output of the shift register is connected to the second input of the first element And whose output is connected to sync. the house of the first trigger, the zero output of which is connected to the second input of the eighth And element and the first input of the seventh And element, the second input of which is connected to the second inputs of the sixth And element and the second OR element, to the fourth output of the shift register. 22 1522217 2A25 t tt t nibl . Fia1 52.U 5.H.1 Jll 2.f.M If I 21.H I L 27.ti 53.1 W 5J / V 22.1 - H 53U H 22.M one 53 .. FIG. tpusA