RU2553093C1 - Information search apparatus - Google Patents

Abstract

FIELD: radio engineering, communication.

SUBSTANCE: information search apparatus comprises N≥2 mask storage units 1₁-1_N, N selection units 2₁-2_N, a frequency divider 3, a time interval generator 4, a search strategy register 5, a transition mask address generating unit 6, a display unit 7, N selection search time controllers 8₁-8_N, a main search time controller 9 and a clock-pulse generator 10.

EFFECT: high probability of timely information search in packet switched data networks, inquiry systems, based on dynamically corrected values of the maximum search time for each search query.

4 cl, 11 dwg

Description

The invention relates to the field of telecommunications and can be used for search and operational identification of information in data networks with packet switching and in information and reference (search) systems.

Known information retrieval devices - see, for example, Aut. St. USSR No. 1711185 "Information Search Device" IPC G06F 15/40, published 05.04.89 and RF Patent No. 2115952 "Information Search Device" IPC G06F 17/40, published July 20, 98.

Known analogues contain boundary registers, summing and subtracting counters, comparison circuits, memory blocks, calculation blocks and a number of other elements that allow you to search for information. When receiving a digital message and searching for a specific digital sequence in it, it is necessary to determine its parameters and the correspondence of the transmission sequence to the data exchange rules established for this protocol. Known analogues do not fully comply with these requirements.

In the first analogue, the disadvantage is the low level of reliability and probability of identifying the communication protocol (less than 0.3), since the search for information blocks is implemented by the dichotomous method without taking into account the presence of an acceptable sequence of packets.

In the second analogue, the disadvantages are the relatively long time required to identify the packets (since identification is carried out by sequential analysis of the characteristic values) and the narrow scope is only for analyzing the TFTP protocol for compliance of the observed packet sequence with the rules established for this protocol. All this limits the use of analog devices for protocol analysis in modern high-speed computer networks.

Of the known closest analogue (prototype) in terms of technical essence of the claimed device is the device according to RF Patent No. 2313128 "Information Search Device" IPC G06F 9/46, published on December 20, 2007, bull. 35.

The prototype device includes N≥2 mask storage units, N selection blocks, a frequency divider, a time interval shaper, a search strategy register, a transition mask address generating unit, and an indication unit.

In the prototype device, the clock input of the frequency divider is the first clock input of the device, and the outputs “Comparison result” of the selection blocks are connected to the corresponding inputs “Comparison result” of the search strategy register and to the corresponding inputs “Comparison result” of the transition mask address generation unit. In this case, K-bit, where K = (log ₂ N) +1, the “Event code” output of the transition mask address generation unit is connected to the K-bit “Event code” inputs of the search strategy register and display unit. The recording permission inputs of all mask storage units are interconnected and are the recording permission input of the device. The corresponding bits of the L-bit information inputs, where L≥2, of the selection blocks are combined and are the corresponding bits of the L-bit information input of the device. The first L-bit inputs “Mask 1” and “Mask 2” of the j-th mask storage block, where j = 1, 2, ..., N, are the j-th first L-bit inputs, respectively, “Mask 1” and “Mask 2 »Device. The second L-bit outputs “Mask 1” and “Mask 2” of the j-th mask storage unit are connected to the corresponding second L-bit outputs “Mask 1” and “Mask 2” of the j-th selection block. The output of the frequency divider is connected to the clock input of the shaper time intervals. The “Initial reset” input of the time slot former is connected to the “Initial reset” input of the transition mask address generation unit and is the “Initial reset” input of the device. At the same time, the M-bit input “Time-out code” of the time slot generator, where M≥2 is the bit length of the time-out code, is the M-bit input “Time-out code” of the device, and the output of the time interval generator is connected to the “Reset” input of the block formation of the address of the transition mask. The signal output of the search strategy register is connected to the signal inputs of the time slot generator and the transition mask address generation unit. The K-bit address input, the control input, the N-bit information input, and the search register enable input are the K-bit address input, the control input, the N-bit information input, and the device enable input. The “Choice of crystal” and “Read / write” inputs of the search strategy register are respectively the “Choice of crystal" and "Read / write" inputs of the device. The N-bit input “Search completion rule” and the “Search result” output of the display unit are respectively the N-bit input “Search completion rule” and the “Search result” output of the device.

Such a scheme, in comparison with analog devices, allows you to expand the scope and speed of the analysis of incoming packets of the prototype device by identifying packets by parallel analysis of the values of identification signs and monitoring the sequence of their exchange for compliance with any a priori specified rules.

However, the prototype has a drawback - a relatively low probability of timely information retrieval in the context of continuous dynamics of changing states of different priority requests for information search and taking into account influencing factors. This is due to the fact that the prototype device does not allow you to dynamically adjust the maximum information search time, which varies both in priority and in dynamically changing requirements for the timeliness of information search in the framework of search queries of different priority.

This prototype device allows you to set the maximum allowable time interval during which the next block of binary information (BDI) specified by the search script is expected, but searches for information without limiting the maximum search time until a specified value is found in the incoming data stream the search script sequence of BDI for each specific search query, while a large number of requests for information search from real users is multifunctional A complex, manageable information and inquiry (search) system can change its state in the dynamics (the requirements for the quality, volume and timeliness of information retrieval within search queries of various priorities, for example, the current requirements for the values of the maximum search time for a particular one, can dynamically change information), under the influence of control actions on the information-reference system, based on the current requirements of subscribers or under the influence of external factors. This excludes the use of the prototype for timely and dynamic information retrieval in real conditions, when not only the properties of the system and the environment, but also the requirements for quality and quality are objectively changed in time in the dynamics of the operation of the information retrieval device within the framework of a managed information and inquiry (search) system timeliness of information retrieval [1-5].

Under the "implementation of search queries" is understood the totality of the information and inquiry (search) system, including fetching a query to search for information from the queue, allocating a resource to this query and actually searching for information in accordance with a given search script, as well as conducting final operations. Search request - sending a search signal that initiates a response.

“Priority” means a number prescribed to a task, process or operation that determines the order (place in the queue) of their implementation or maintenance. The lower the number, the higher the priority level. It is possible to control the priority of incoming search queries by changing the place in the queue and (or) dynamic correction (if necessary) of the maximum search time.

Under the “state of diverse search requests for information” is meant a set of parameter values characterizing these requests (their priority is the place in the queue and the maximum time required to search for information for each search scenario, search query) at a particular time.

By “maximum search time” is meant the maximum time for the implementation of a search query in accordance with a given scenario. The code for the maximum search time T _n for a specific given scenario, a specific set of transition masks - the set of BDI types that are part of a specific scenario (where n = 1, 2, ..., N is the corresponding number of the nth scenario, and N is the total number of types BDI (transition masks)) is stored, then a search request signal is generated and a search queue is formed from such request signals.

The purpose of the claimed technical solution is to create an information search device that increases the likelihood of timely information retrieval in conditions inherent in the real process of functioning of modern data networks with packet switching, modern information and reference (search) systems - in the context of continuous dynamics of changing states of different priority search requests information and taking into account the influencing factors, a device capable of timely search queries taking into account, ak dynamics control actions or external factors and time-varying current requirements of subscribers to search the timeliness of information, based on the dynamically corrected values (boundaries) of the maximum search time for each search query.

This goal is achieved by the fact that in the known information retrieval device comprising N≥2 mask storage units, N selection blocks, a frequency divider, a time shaper, a search strategy register, a transition mask address generation unit and an indication unit, N identical selection controllers are additionally included search time, intended for decryption, additional comparison and control of the S-bit code, stipulating a new value of the maximum search time for each specific search for mildew, main controller search time, adapted to dynamically adjust the maximum search time values for each keyword and a clock generator adapted to generate a synchronization pulse train. In this case, the clock input of the frequency divider is the first clock input of the device, and the output of the frequency divider is connected to the clock input of the shaper of time intervals, while K-bit, where K = (log ₂ N) +1, is the “Event code” output of the mask address generation unit transitions connected to the K-bit inputs "Event code" of the search strategy register and display unit, respectively. The recording permission inputs of the N mask storage units are combined and are the device recording permission input, L-bit information inputs, where L≥2, N selection blocks are combined and are the Z-bit information input of the device. Moreover, the first L-bit inputs “Mask 1” and “Mask 2” of N mask storage units are the first L-bit inputs, respectively, “Mask 1” and “Mask 2” of the device. The second L-bit outputs “Mask 1” and “Mask 2” of the N mask storage units are connected to the second Z-bit inputs “Mask 1” and “Mask 2” of the corresponding selection blocks. The “Initial reset” input of the time slot former is connected to the “Initial reset” input of the transition mask address generation unit and is the “Initial reset” input of the device. At the same time, the M-bit input “Time-out code” of the time slot generator, where M≥2 is the bit length of the time-out code, is the M-bit input “Time-out code” of the device, and the output of the time interval generator is connected to the “Reset” input of the block the formation of the address of the mask transitions, the signal output of the register of the search strategy is connected to the signal inputs of the shaper time intervals and the block forming the address of the mask transitions. Moreover, the K-bit address input, the control input, the N-bit information input and the register enable input of the search strategy are the K-bit address input, the control input, the N-bit information input and the device enable input, the “Choice of crystal” and “Read” inputs / write ”of the search strategy register are respectively the“ Choice of crystal ”and“ Read / write ”inputs of the device, the N-bit input“ Search termination rule ”and the“ Search result ”output of the display unit are N-bit respectively m input “Search termination rule” and output “Search result” of the device. Moreover, the “Comparison Result” output of the nth selection block, where n = 1, 2, ..., N, is connected to the “Comparison Result” input of the n-th search time controller, the “Comparison Result” output of which is connected to the nth input “Comparison Result” of the search strategy register and with the nth input “Comparison Result” of the transition mask address generation unit. The output of the clock generator is connected to the clock input of the nth selection block, the input “Zeroing” of which is the nth input “Zeroing” the device, and the S-bit correcting input of the nth selection block is combined with the S-bit checking input n -th selection search time controller and connected to the n-th S-bit output of the main search time controller, N S-bit inputs of which are the corresponding N S-bit inputs "Correction of the maximum search time" of the device.

The selection search time controller (SCWP) consists of a decoder of the corrected code for the maximum search time and a comparison-correction register for the maximum search time. In this case, the S-bit input of the decoder of the corrected code for the maximum search time is the S-bit test input of the selection controller of the search time. Moreover, the test output of the decoder of the corrected code for the maximum search time is connected to the test input of the comparison-correction register of the maximum search time, the signal input and output of which are respectively the signal input and output “Comparison result” of the selector search time controller.

The main search time controller consists of a search time recording element and a storage element of a new search time value, wherein N S-bit inputs of the search time recording element are the corresponding N S-bit inputs of the search time controller, and N S-bit outputs of the time recording element the search are connected to the corresponding N S-bit inputs of the storage element of the new value of the search time, N S-bit outputs of which are the corresponding Pulse belongs to the general structural diagram generator is commercially available.

The selection block (BS) consists of the first and second groups of two-input elements And L elements in each group, a comparator, inverter, counter, three-input element And and a correction register. In this case, the inverted output of the counter is connected to the first input of the three-input element And, connected to the inverted output of the inverter and is the output “Comparison result” of the selection block. The third input of the three-input element And is the clock input of the selection block, and the output of the three-input element And is connected to the counting input of the counter, the inverse input of the resolution of the counter count is connected to the output of the equality of the comparator and connected to the second input of the three-input element And to the input of the inverter, while S-bit the input of the correction register is an S-bit correction input of the selection block, and S outputs of the correction register are connected to the corresponding S information inputs of the counter. Moreover, the counter reset input is the “Zeroing” input of the selection block, with the l-th one, where l = 1, 2, ..., L, the input of the first group of information inputs of the comparator is connected to the corresponding output of the l-th two-input element And the first group of two-input elements And , and the l-th input of the second group of information inputs of the comparator is connected to the output of the l-th two-input element And the second group of two-input elements I. Moreover, the first input of the l-th two-input element And the first group of two-input elements And is the l-th bit of the L-bit information of the input of the selection block, the second input of the l-th two-input element And the first group of two-input elements And is connected to the first input of the l-th two-input element And the second group of two-input elements And is the l-th bit of the second L-bit input “Mask 1” of the selection block , and the second input of the l-th two-input element And the second group of two-input elements And is the l-th bit of the second L-bit input "Mask 2" of the selection block.

Thanks to a new set of essential features, due to the introduction of N≥2 identical selection search time controllers, the main search time controller and a clock pulse generator, which respectively provide decryption, dynamic correction and synchronization of the processes of decryption, control and correction of values (boundaries) of the maximum search time for each specific scenario (search query), the claimed device achieves the possibility of timely implementation of search queries, taking into account how dynam ki control actions or external factors and time-varying current subscriber requirements for timely retrieval of information. An opportunity is achieved that increases the likelihood of timely information retrieval under conditions inherent in the real functioning of modern packet-switched data transmission networks, modern information and inquiry (search) systems - in the conditions of continuous dynamics of changing states of different priority requests for information search and taking into account influencing factors.

The claimed device is illustrated by drawings, on which are presented:

in FIG. 1 is a structural diagram of an information retrieval device;

селекционного контроллера времени поиска;in FIG. 2 is a block diagram of the nth $$\left(n=\overline{\mathrm{one,}N}\right)$$

selection search time controller;

in FIG. 3 is a block diagram of a main search time controller;

блока селекции;in FIG. 4 is a block diagram of the nth $$\left(n=\overline{\mathrm{one,}N}\right)$$

selection block;

блока хранения маски;in FIG. 5 is a block diagram of the nth $$\left(n=\overline{\mathrm{one,}N}\right)$$

mask storage unit;

in FIG. 6 is a structural diagram of a shaper of time intervals;

in FIG. 7 is a block diagram of a search strategy register;

in FIG. 8 is a block diagram of a transition mask address generating unit;

in FIG. 9 is a structural diagram of a display unit;

in FIG. 10 is an example of a search script;

in FIG. 11 is an example of filling transition masks, script start masks and script end masks.

The device (see Fig. 1) consists of N, where N≥2, mask storage blocks 1 ₁ -1 _N , N selection blocks 2 ₁ -2 _N , frequency divider 3, time slot former 4, search strategy register 5, block the formation of the address of the transition mask 6, display unit 7, N selection search time controllers 8 ₁ -8 _N , the main search time controller 9 and the clock generator 10.

The elements are interconnected as follows (see Fig. 1). The clock input 38 of the frequency divider 3 is the first clock input 08 of the device, and the output 39 of the frequency divider 3 is connected to the clock input 41 of the shaper time intervals 4. Moreover. K-bit, where K = (log ₂ N) +1, the “Event Code” output 62 of the transition mask address generating unit 6 is connected to the K-bit “Event Code” inputs 52 and 71 of the search strategy register 5 and display unit 7, respectively. The recording permission inputs 10 ₁ -10 _N N mask storage units 1 ₁ -1 _{N are} combined and are the recording permission input 01 of the device. L-bit information inputs 21 ₁ -21 _N , where L≥2, N selection blocks 2 ₁ -2 _{N are} combined and are L-bit information input 04 of the device. The first Z-bit inputs “Mask 1” 12 _n and “Mask 2” 13 _{n of the} n-th block storage unit mask 1 _n , where n = 1, 2, N, are the n-th first L-bit inputs, respectively, “Mask 1” 02 _n and Mask 2 03 _n devices. The second Z-bit outputs “Mask 1” 14 _n and “Mask 2” 15 _{n of the} n-th storage unit of mask 1 _{n are} connected to the corresponding second Z-bit outputs “Mask 1” 22 _n and “Mask 2” 23 _{n of the} n-th selection block 2 _n . The input “Initial reset” 42 of the shaper of time intervals 4 is connected to the input “Initial reset” 63 of the unit for generating the address of transition mask 6 and is the input “Initial reset” 05 of the device. At the same time, the M-bit input “Time-out code” 43 of the time slot generator 4, where M≥2 is the bit length of the time-delay code, is the M-bit input “Time-out code” 06 of the device, and the output 44 of the time interval generator 4 is connected to the “Reset” input 64 of the block for generating the address of the transition mask 6. The signal output 59 of the register of the search strategy 5 is connected to the signal inputs 45 and 65 of the shaper time intervals 4 and the block for generating the address of the mask of transitions 6, respectively. The K-bit address input 53, the control input 54, the N-bit information input 55, and the enable input 58 of the search strategy register 5 are respectively the K-bit address input 09, the control input 010, the N-bit information input 011, and the enable input 014 of the device. The inputs "Choice of crystal" 56 and "Read / write" 57 of the register of the search strategy 5 are respectively the inputs of "Choice of crystal" 012 and "Read / write" 013 device. The N-bit input “Search completion rule” 72 and the “Search result” output 73 of the display unit 7 are respectively the N-bit input “Search completion rule” 07 and the “Search result” output 015 of the device. The outputs “Comparison result” 26 ₁ -26 _N selection blocks 2 ₁ -2 _{N are} connected to the corresponding inputs “Comparison result” 81 ₁ -81 _{N of the} corresponding selection controllers for search time 8 ₁ -8 _N , the outputs “Comparison result” 83 ₁ -83 _{N of} which are connected to the corresponding inputs “Comparison Result” 51 ₁ -51 _{N of the} search strategy register 5 and to the corresponding inputs “Comparison Result” 61 ₁ -61 _{N of the} block for generating the transition mask address 6. The output of 101 clock pulses 10 is connected to the clock inputs 25 ₁ -25 _{N of} each of the TV selection blocks 2 ₁ -2 _N , input rows "zeroing" January ₂₄ -24 _N respective inputs of which are "zeroing" 017 ₁ -017 _N of the device. Moreover, S-bit, where S≥2 is the bit depth of the search time correction code, the correction input 27 _{n of the} n-th selection block 2 _{n is} connected to the S-bit test input 82 _{n of the} n-th selection search time controller 8 _n and connected to n- S-bit output 92 _{n of the} main controller of the search time 9, N S-bit inputs 91 ₁ -91 _{N of} which are the corresponding N S-bit inputs "Correction of the maximum search time" 016 device.

The number “N, (N≥2)” (blocks, bits, inputs, outputs, etc.) is determined in accordance with the possible number of types of BDIs (they determine the total number of transition masks characterizing the composition of the search scripts) and, as a rule, ranges from 2 (two) to 500 (five hundred).

The number "K, (where K = (log ₂ N + 1)" characterizes the length of the code of the address of the transition mask, the address to which the transition mask is stored in the random access memory, which determines the type (s) expected according to the BDI search script. In other words, this the number of binary bits sufficient to address the N transition masks and the mask of the beginning of the search script, as a rule, is from 2 (two) to 10 (ten).

The number "M, (M≥2)" characterizes the length of the time-out code — the code of the valid time interval during which the next BDI is expected, specified by the search script and, as a rule, ranges from 2 (two) to 10 (ten).

The number "L, (L≥2)" characterizes the maximum possible number of bits in the BDI used in the search script and, as a rule, ranges from 2 (two) to 10 (ten).

The number "S, (S≥2)" characterizes the capacity of the correcting code for the search time, the capacity of the code that determines the initial or corrected (new) value of the maximum search time for each specific scenario (search request) and, as a rule, is from 2 (two ) to 10 (ten).

The selection controllers of the search time 8 ₁ -8 _{N are} identical and are intended for decryption, additional comparison and control of a new S-bit code introduced in the dynamics of controlling the process of implementing search queries, which sets a new value (boundary) for the maximum search time for each specific search query.

The selection search time controller (for example, the n-th SKVP) 8 _n , where n = 1, 2, ..., N, (Fig. 2), consists of the decoder of the corrected code for the maximum search time 8.1 _n and the comparison-correction register for the maximum search time 8.2 _n . Moreover, the S-bit input 8.1 _n -1 of the decoder of the corrected code for the maximum search time 8.1 _n is the S-bit test input 82 _{n of the} selection controller of the search time 8 _n . Test output 8.1 _n -2 of the decoder of the corrected code for the maximum search time 8.1 _{n is} connected to the test input 8.2 _n -2 of the comparison-correction register of the maximum search time 8.2 _n , the signal input 8.2 _n -1 of which is the signal input 81 _{n of the} selection controller of the search time 8 _n . The signal output 8.2 _n -3 register comparison-correction of the maximum search time 8.2 _n is the output "Comparison result" 83 _n selection controller search time 8 _n .

The decoder of the corrected code for the maximum search time 8.1 _{n of the} n-th selection controller of the search time 8 _{n is} designed to convert the S-bit code, which determines the new value entered in the control process, the value (boundary) of the maximum search time for each search request in binary code. The decoder of the corrected code of the maximum search time 8.1 _n can be technically implemented in the form of a commercially available decoder described in the book [Bogdanovich M.I., Grel I.N., Prokhorenko V.A. et al. Digital Integrated Circuits: A Guide. - Minsk: Belarus, 1991.S. 432-436, Fig. 4.46].

The register for comparison-correction of the maximum search time 8.2 _{n of the} n-th selection controller of the search time 8 _{n is} intended to additionally check (compare) the correspondence of the time of receipt of the results of the search query with the initial and newly entered maximum search time in the queue of search queries and corrections (formation based on the results of comparison ) at the output “Comparison Result” 83 _n SKVP 8 _n signal characterizing the correspondence of obtaining the results of this search query to the required time taking into account the correction. The comparison-correction register of the maximum search time of 8.2 _n can be technically implemented on the basis of a commercially available comparison unit (digital comparator), as shown in [Gusev VV, ON Lebedev, Sidorov AM Fundamentals of pulse and digital technology. - St. Petersburg: SPVVIUS, 1995.S. 149-152, Fig. 5.19].

The main search time controller 9 is designed for dynamic correction of values (boundaries) of the maximum search time for each search query from any combination of N transition masks (search scripts).

The main controller of the search time 9 (Fig. 3) consists of a recording element of the search time 9.1 and the storage element of the new value of the search time 9.2. Moreover, N S-bit inputs 9.1-1 ₁ -9.1-1 _{N of the} recording element of the search time 9.1 are the corresponding N S-bit inputs 91 ₁ -91 _{N of the} main controller of the search time 9 and the corresponding N S-bit inputs "Correction of the maximum search time »016 ₁ -016 _N device. Moreover, N S-bit outputs 9.1-2 ₁ -9.1-2 _{N of the} recording element of the search time 9.1 are connected to the corresponding N S-bit inputs 9.2-1 ₁ -9.2-1 _N of the storage element of the new value of the search time 9.2, N S-bit outputs 9.2-2 ₁ -9.2-2 _N which are the corresponding N S-bit outputs 92 ₁ -92 _{N of the} main search time controller 9.

The recording element of the search time 9.1 of the main controller of the search time 9 is designed to control and register in the S-bit code a new value entered in the dynamics of the process of searching for information, the value of the maximum search time for each specific search request. The recording element of the search time 9.1 can be technically implemented as a commercially available multi-bit shift register for left shift, as shown in the literature [Gusev VV, Lebedev ON, Sidorov A.M. Fundamentals of pulsed and digital technology. - St. Petersburg: SPVVIUS, 1995.S. 158-160, Fig. 5.28 (b)].

The storage element of the new value of the search time 9.2 of the main controller of the search time 9 is designed to record and store in S-bit code a new value, entered in the dynamics of the process of implementing search queries, of the maximum information search time. The storage element of the new value of the search time 9.2 can be technically implemented in the form of a conventional storage device based on a typical multi-bit shift register with sequential input and output of the information described in [Fast Yu.A., Velikson Ya.M., Vogman VD et al. Electronics: Reference Book / Ed. Bystrova Yu.A. - St. Petersburg: Energoatomizdat, 1996.S. 291-292, Fig. 6. 7].

The clock generator 10, which is part of the general block diagram, is designed to generate a synchronizing sequence of pulses. Technical implementation of the clock generator 10 is possible on the basis of a commercially available clock generator described in [Shilo V.L. Popular digital circuits. Directory. - M .: Radio and communications, 1987. S. 50-53].

The selection blocks 2 ₁ -2 _{N are} identical and are designed to control and identify the corresponding elements of the incoming data stream, generate a search result (identification result), control the remaining search time, and generate control signals after the set initial or newly entered in the control dynamics search time for each search query.

счетчика 2.5_n подключен к первому входу 2.6_n-1 трехвходового элемента И 2.6_n, соединен с инверсным выходом 2.4_n-2 инвертора 2.4_n и является выходом «Результат сравнения» 26_n блока селекции 2_n. Третий вход 2.6_n-3 трехвходового элемента И 2.6_n является тактовым входом 25_n блока селекции 2_n, а выход 2.6_n-4 трехвходового элемента И 2.6_n подключен к счетному входу Z счетчика 2.5_n. Инверсный вход разрешения счета $$\overline{V}$$

счетчика 2.5_n соединен с выходом равенства 2.3_n-3 компаратора 2.3_n и подключен к второму входу 2.6_n-2 трехвходового элемента И 2.6_n и к входу 2.4_n-1 инвертора 2.4_n. При этом S-разрядный вход 2.7_n-1 корректирующего регистра 2.7_n является S-разрядным корректирующим входом 27_n блока селекции 2_n, а S выходов 2.7_n-2₁-2.7_n-2_S корректирующего регистра 2.7_n подключены к соответствующим S информационным входам D₁-D_S счетчика 2.5_n. Вход сброса R счетчика 2.5_n является входом «Обнуление» 24_n блока селекции 2_n и соответствующим входом «Обнуление» 017_n устройства поиска информации. Каждый l-ый, где l=1, 2, …, L, вход первой группы информационных входов 2.3_n-1₁-2.3_n-1_L. компаратора 2.3_n соединен с соответствующим выходом 2.1_l-3 l-го двухвходового элемента И 2.1_l первой группы двухвходовых элементов И 2.1₁-2.1_L, а каждый l-ый вход второй группы информационных входов 2.3_n-2₁-2.3_n-2_L компаратора 2.3_n соединен с соответствующим выходом 2.2_l-3 l-го двухвходового элемента И 2.2_l второй группы двухвходовых элементов И 2.2₁-2.2_L. Первый вход 2.1₁-1 любого l-го двухвходового элемента И 2.1_l первой группы двухвходовых элементов И 2.1₁-2.1_L является l-ым разрядом L-разрядного информационного входа 21_n блока селекции 2_n и соответствующим l-ым разрядом L-разрядного информационного входа 04_n устройства поиска информации. Второй вход 2.1_l-2 любого l-го двухвходового элемента И 2.1₁ первой группы двухвходовых элементов И 2.1₁-2.1_L соединен с соответствующим первым входом 2.2_l-1 l-го двухвходового элемента И 2.2_l второй группы двухвходовых элементов И 2.2₁-2.2_L, и является l-ым разрядом второго L-разрядного входа «Маска 1» 22_n блока селекции 2_n, а второй вход 2.2_l-2 l-го двухвходового элемента И 2.2_l второй группы двухвходовых элементов И 2.2₁-2.2_L, является l-ым разрядом второго L-разрядного входа «Маска 2» 23_n блока селекции 2_n.The selection block (for example, the n-th BS) 2 _n , where n = 1, 2, ..., N, (Fig. 4), consists of the first 2.1 ₁ -2.1 _L and the second 2.2 ₁ -2.2 _L , groups of two-input elements AND by L elements in each group, a comparator 2.3 _n , an inverter 2.4 _n , a counter 2.5 _n , a three-input element AND 2.6 _n and a correction register 2.7 _n . Inverse output $$\overline{P}$$

The counter 2.5 _{n is} connected to the first input 2.6 _n -1 of the three-input element AND 2.6 _n , connected to the inverse output 2.4 _n -2 of the inverter 2.4 _n and is the output “Comparison result” 26 _n of the selection block 2 _n . The third input 2.6 _n -3 of the three-input element AND 2.6 _n is the clock input 25 _n of the selection block 2 _n , and the output 2.6 _n -4 of the three-input element AND 2.6 _{n is} connected to the counting input Z of the counter 2.5 _n . Inverse account resolution input $$\overline{V}$$

the counter 2.5 _{n is} connected to the output of equality 2.3 _n -3 of the comparator 2.3 _n and connected to the second input 2.6 _n -2 of the three-input element And 2.6 _n and to the input 2.4 _n -1 of the inverter 2.4 _n . In this case, the S-bit input 2.7 _n -1 of the correction register 2.7 _n is the S-bit correction input 27 _n of the selection block 2 _n , and the S outputs 2.7 _n -2 ₁ -2.7 _n -2 _{S of the} correction register 2.7 _{n are} connected to the corresponding S information the inputs D ₁ -D _S counter 2.5 _n . The reset input R of the counter 2.5 _n is the input “Zeroing” 24 _n of the selection block 2 _n and the corresponding input “Zeroing” 017 _{n of the} information search device. Each l-th, where l = 1, 2, ..., L, the input of the first group of information inputs 2.3 _n -1 ₁ -2.3 _n -1 _L. comparator 2.3 _{n is} connected to the corresponding output 2.1 _l -3 of the l-th two-input element And 2.1 _{l of the} first group of two-input elements And 2.1 ₁ -2.1 _L , and each l-th input of the second group of information inputs 2.3 _n -2 ₁ -2.3 _n -2 _{L of the} comparator 2.3 _{n is} connected to the corresponding output 2.2 _l -3 of the l-th two-input element AND 2.2 _{l of the} second group of two-input elements AND 2.2 ₁ -2.2 _L. The first input 2.1 ₁ -1 of any l-th two-input element And 2.1 _{l of the} first group of two-input elements And 2.1 ₁ -2.1 _L is the l-th bit of the L-bit information input 21 _n selection block 2 _n and the corresponding l-th bit of the L-bit information input 04 _n information retrieval device. The second input 2.1 _l -2 of any l-th two-input element And 2.1 _{1 of the} first group of two-input elements And 2.1 ₁ -2.1 _{L is} connected to the corresponding first input 2.2 _l -1 l-th two-input element And 2.2 _{l of the} second group of two-input elements And 2.2 ₁ - 2.2 _L , and is the l-th bit of the second L-bit input "Mask 1" 22 _n selection block 2 _n , and the second input 2.2 _l -2 l-th two-input element And 2.2 _{l the} second group of two-input elements And 2.2 ₁ -2.2 _L , is the l-th bit of the second L-bit input "Mask 2" 23 _n selection block 2 _n .

The first 2.1 ₁ -2.1 _L and the second 2.2 ₁ -2.2 _L , groups of two-input AND elements (L elements in each group) included in the block diagram of the selection block, for example, 2 _n , are identical, a L of the same type AND elements perform the functions of switching elements when polling the L-bit information input 21 _n of the selection block 2 _n and the type of BDI determined by the first and second bit masks, respectively, received at the second L-bit input "Mask 1" 22 _n and the second L-bit input "Mask 2" 23 _n blocks breeding 2 _n . The structure of the first and second groups of two-input elements And is known, described in the prototype (see RF patent No. 2313128 “Information retrieval device” IPC G06F 9/46 published December 20, 2007, bull. 35) and is illustrated in FIG. 4, and the AND (-2.1 _L 2.1 ₁ and 2.2 ₁ -2.2 _L), belong to these groups, are implemented as known and described in [Gusev, V., Lebedev ON, Sidorov AM pulse Fundamentals and digital technology. - St. Petersburg: SPVVIUS, 1995.S. 13-14, Fig. 1.2].

The comparator 2.3 _n , which is part of the selection block, for example, 2 _n , is designed to compare binary codes installed on its inputs and generate a comparison result. A description of the work and the comparator circuit are given, for example, in [Shilo V.L. Popular chip TTL. - M.: ARGUS, 1993, p. 183-184].

The inverter 2.4 _n , which is part of the selection block, for example, 2 _n , is designed to convert the signals of the logical unit value to the value of logical zero when the comparison results match the search script, and the inverse transformation if not. The inverter 2.4 _n can be technically implemented as an element NOT, in accordance with the description given in [Gusev VV, Lebedev ON, Sidorov AM Fundamentals of pulse and digital technology. - SPb .: SPVVIUS, 1995.S. 14, Fig. 1.3].

The counter 2.5 _n , which is part of the selection block, for example, 2 _n , is used to count the pulses (counting pulses) received at its input, to generate a control signal determined by the initial filling code from the inputs D ₁ -D _S and the repetition period of the clock pulses, then there is a custom timer. The description of the operation and the circuit of such a counter are known and are given, for example, in [Maltsev P. P., Dolidze N. S. and others. Digital integrated circuits: a reference. - M .: Radio and communications, 1994, S. 64-65].

счетчика 2.5_n в интересах контроля времени поиска для каждого поискового запроса, либо установленного изначального, либо вновь вводимого в динамике управления процессом поиска информации. Трехвходовый элемент И 2.6_n может быть технически реализован на основе серийно выпускаемого элемента И, описанного в [Гусев В.В., Лебедев О.Н., Сидоров A.M. Основы импульсной и цифровой техники. - СПб.: СПВВИУС, 1995. С. 13-14, рис. 1.2].The three-input element AND 2.6 _n , which is part of the selection block, for example, 2 _n , is designed to register the results of search queries (comparison results), as well as to switch the clock input 25 _n of the selection block 2 _n and inverse output $$\overline{P}$$

2.5 _n counter in the interests of controlling the search time for each search query, either the initial or newly entered information in the control dynamics of the search process. The three-input element And 2.6 _n can be technically implemented on the basis of a commercially available element And, described in [Gusev VV, Lebedev ON, Sidorov AM Fundamentals of pulse and digital technology. - St. Petersburg: SPVVIUS, 1995.S. 13-14, Fig. 1.2].

Correction Register 2.1 _n, part of the selection unit, for example 2 _n, for the registration and pre comparing previously inputted (the original) and re-introduced into the dynamics control S-bit code, and correcting (formation by comparing the results) at its S the outputs 2.7 _n -2 ₁ -2.7 _n -3 _S information signals characterizing the preliminary decision on the value of the maximum search time for each specific search request. The correction register 2.7 _n can be technically implemented on the basis of a commercially available multi-digit number comparison unit, as described in [Gusev VV, ON Lebedev, Sidorov AM Fundamentals of pulse and digital technology. - St. Petersburg: SPVVIUS, 1995.S. 149-152, Fig. 5.21].

The mask storage blocks 1 ₁ -1 _N included in the general block diagram are identical and are designed to store bit masks used to identify elements of the incoming data stream. The structure of the mask storage units is known, described in the prototype (see RF patent No. 2313128 “Information retrieval device” IPC G06F 9/46, December 20, 2007, bull. 35) and is illustrated in FIG. 5. The mask storage unit, for example, 1 _n , consists of the first 1.1 _n and second 1.2 _n registers. The bits of the L-bit information output 1.1 _n -3 of the first register 1.1 _n are the corresponding bits of the second L-bit output "Mask 1" 14 _n of the mask storage unit 1 _n , and the bits of the L-bit information output 1.2 _n -3 of the second register 1.2 _n are corresponding bits of the second Z-bit output "Mask 2" 15 _n mask storage unit 1 _n . The recording permission inputs 1.1 _n -1 and 1.2 _n -1, respectively, of the first 1.1 _n and second 1.2 _n registers are interconnected and are the recording permission input 10 _n of the mask storage unit 1 _n and the recording permission input 01 of the information search device. The bits of the L-bit information input 1.1 _n -2 of the first register 1.1 _n are the corresponding bits of the first L-bit input 12 _n “Mask 1” of the mask storage unit 1 _n and the corresponding bits of the first L-bit input 02 _n “Mask 1” of the information search device , and the bits of the L-bit information input 1.2 _n -2 of the second register 1.2 _n are the corresponding bits of the first L-bit input 13 _n “Mask 2” of the mask storage unit 1 _n and the corresponding bits of the first L-bit input 03 _n “Mask 2” of the device search for information.

The first 1.1 _n and second 1.2 _n , the registers of the mask storage unit 1 _{n are} identical and are designed to store the first and second bit masks, respectively. Registers can be technically implemented on the basis of a commercially available register, as described in [Maltsev P.P., Dolidze N.S. et al. Digital Integrated Circuits: A Guide. - M .: Radio and communications, 1994, p. 57-62].

The frequency divider 3, which is part of the general block diagram, is designed to increase the period of the sequence of pulses arriving at its input. The implementation scheme of the frequency divider is known and described in the prototype (see RF patent No. 2313128 "Information retrieval device" IPC G06F 9/46 published December 20, 2007, bull. 35). In particular, the frequency divider 3 can be built on the basis of the counter, as described in [Maltsev P.P., Dolidze N.S. et al. Digital Integrated Circuits: A Guide. - M .: Radio and communications, 1994, p. 62-74]. In this case, the input of the divider will be the counter input of the counter, and the output of the divider will be one of the outputs of the counter.

Shaper time intervals 4, which is part of the general structural diagram, is designed to control the time interval between the elements of the incoming data stream and the formation of the signal after it. The structure of the time interval former is known, described in the prototype (see RF patent No. 2313128 “Information Search Device” IPC G06F 9/46, December 20, 2007, bull. 35) and is shown in FIG. 6. The time interval shaper 4 consists of a first two-input element OR 4.1, a JK trigger 4.2, a first two-input element AND 4.3, an inverter 4.4, a second two-input element AND 4.5, a second two-input element OR 4.6, and a counter 4.7. Moreover, the overflow output P of the counter 4.7 is connected to the second inputs 4.5-2 and 4.1-2, respectively, of the second two-input element AND 4.5 and the first two-input element OR 4.1. The first input 4.1-1 of the first two-input element OR 4.1 is connected to the first input 4.6-1 of the second two-input element OR 4.6 and is the input "Initial reset" 42 of the shaper time intervals 4 and the input "Initial reset" 05 of the device. The output 4.1-3 of the first two-input element OR 4.1 is connected to the second information input 4.2-2 (input K) of the JK trigger 4.2, the first information input 4.2-1 (input J) of which is connected to the write enable input V of counter 4.7 and is a signal input 45 shaper time intervals 4. Moreover, the m-th, where m = 1, 2, ..., M, the information input D _m (from the composition of D ₁ -D _M information inputs) counter 4.7 is the m-th bit of the M-bit input " Time-out code "43 of the shaper of time intervals 4 and the corresponding m-th bit of the M-bit input" Code BP Meni expectations "06 device. The reset input R of the counter 4.7 is connected to the output 4.6-3 of the second two-input element OR 4.6, and the counting input C of the counter 4.7 is connected to the output 4.3-3 of the first two-input element AND 4.3. The first input 4.3-1 of the first two-input element And 4.3 is the second clock input 41 of the shaper of time intervals 4. The output 4.2-3 of the JK trigger 4.2 is connected to the second input 4.3-2 of the first two-input element And 4.3 and the input 4.4-1 of the inverter 4.4, output 4.4 -2 which is connected to the first input 4.5-1 of the second two-input element AND 4.5. The output 4.5-3 of the second two-input element AND 4.5 is connected to the second input 4.6-2 of the second two-input element OR 4.6 and is the output "Reset" 44 of the shaper time intervals 4.

The first 4.1 and second 4.6 two-input elements OR of the time interval generator 4 are identical and are intended for combining signals of a certain logical level coming from the input “Initial reset” of the device, as well as the overflow output P of counter 4.7 and the output of the second two-input element And 4.5, respectively. The structure of the first 4.1 and second 4.6 two-input OR elements is known, described in the prototype (see RF patent No. 2313128 "Information Search Device" IPC G06F 9/46, 12/20/2007, bull. 35), the elements can be technically implemented on the basis of commercially available element OR, described in detail in [Gusev VV, Lebedev ON, Sidorov AM Fundamentals of pulsed and digital technology. - SPb .: SPVVIUS, 1995.S. 24-26, Fig. 1.7].

JK-trigger 4.2 shaper time intervals 4 is intended to store a logical value that determines the mode of operation of the shaper time intervals. The structure of the JK trigger is known, described in the prototype (see RF patent No. 2313128 "Information retrieval device" IPC G06F 9/46, 12/20/2007, bull. 35), the JK trigger can be technically implemented as described in [ Tarabrin B.V., Lunin L.F., Smirnov Yu.N. and other Integrated circuits: a guide. - M .: Energoatomiz dates, 1985, p. 67].

The first 4.3 and second 4.5 two-input elements AND of the shaper of time intervals 4 are identical and perform the functions of switching elements when polling the output of the JK trigger and the second clock input 41 of the shaper, as well as the overflow outputs P of the counter 4.7 and inverter 4.4, respectively. Approaches to the implementation of AND elements are known, described in the prototype (see RF patent No. 2313128 “Information retrieval device” IPC G06F 9/46, December 20, 2007, bull. 35), these products can be built on the basis of commercially available And elements described in detail in [Gusev VV, Lebedev O.N., Sidorov A.M. Fundamentals of pulsed and digital technology. - St. Petersburg: SPVVIUS, 1995.S. 13-14, Fig. 1.2].

The inverter 4.4 of the time interval generator 4 is intended for converting signals of a logical unit value to a logical zero value and inverse transformation depending on the signal at its input, determined by the values from the output of the JK trigger 4.2. Inverter 4.4 can be technically implemented as an element NOT, in accordance with the description given in [Gusev VV, Lebedev ON, Sidorov A.M. Fundamentals of pulsed and digital technology. - SPb .: SPVVIUS, 1995.S. 14, Fig. 1.3].

Counter 4.7 of the shaper of time intervals 4 is intended for counting the pulses arriving at its input and generating a control signal after a time interval determined by the value of the code for the initial filling of the counter and the repetition period of the clock pulses, that is, it performs the function of a custom timer. The description of the operation and the circuit of such a counter are known and are given, for example, in [Maltsev P.P., Dolidze N.S. et al. Digital Integrated Circuits: A Guide. - M .: Radio and communications, 1994, p. 71].

) и «Чтение/запись» 5.2-4 (вход $$\overline{WE}$$

) оперативного запоминающего устройства 5.2 являются соответствующими входами «Выбор кристалла» 56 и «Чтение/запись» 57 регистра стратегии поиска 5, а также соответствующими входами «Выбор кристалла» 012 и «Чтение/запись» 013 устройства. При этом, k-ый вход 5.1-1_k первой группы информационных входов 5.1-1 (A_k из состава группы A₁-A_k информационных входов) селектора мультиплексора 5.1 является k-ым разрядом K-разрядного входа «Код события» 52 регистра стратегии поиска 5, а k-ый вход 5.1-2_k второй группы информационных входов 5.1-2 (B_k из состава группы B₁-B_K информационных входов) селектора мультиплексора 5.1 является k-ым разрядом K-разрядного адресного входа 53 регистра стратегии поиска 5 и соответствующим k-ым разрядом K-разрядного адресного входа 09 устройства. Управляющий вход 5.1-3 (вход SE) селектора мультиплексора 5.1 является управляющим входом 54 регистра стратегии поиска 5 и управляющим входом 010 устройства поиска информации.The search strategy register 5, which is part of the general block diagram, is designed to verify that the sequence of identified elements of the incoming data stream follows the given rules and generates a signal when an element is received that is expected in accordance with the rules. The structure of the search strategy register is known, described in the prototype (see RF patent No. 2313128 “Information retrieval device” IPC G06F 9/46, December 20, 2007, bull. 35) and is shown in FIG. 7. The search strategy register 5 consists of a selector-multiplexer 5.1, random access memory 5.2, N three-input elements OR-NOT 5.3 ₁ -5.3 _N , N-input element OR 5.4, the output 5.4-2 of which is a signal output 59 of the search strategy register 5 . Moreover, the nth input 5.4-1 _n (where n = 1, 2, ..., N) of the N-input OR element 5.4 is connected to the inverse output 5.3 _n -4 of the n-th three-input element OR NOT 5.3 _n . The first input is 5.3 _n -1 of the n-th three-input OR-NOT element 5.3 _n is the n-th input of “Comparison result” 51 _{n of the} search strategy register 5. The second input is 5.3 _n -2 of the n-th three-input OR-NOT 5.3 _n element is connected to the n-th information output 5.2-5 _{n of} random access memory 5.2, and the third inputs 5.3 ₁ -3-5.3 _N -3 of all three-input elements OR NOT 5.3 ₁ -5.3 _N are interconnected, are the permitting input 58 of the search strategy register 5 and enable input 014 of the device. Moreover, the k-th, where k = 1, 2, ..., K, the address input 5.2-2 _k (A _k from the composition A ₁ -A _K address inputs) of the random access memory 5.2 is connected to the k-th output 5.1-4 _k (Q _k from the composition of Q ₁ -Q _K outputs) of the selector of the multiplexer 5.1, and the nth information input 5.2-3 _n (D _n from the composition of D ₁ -D _N information inputs) of the random access memory 5.2 is the n-th discharge of N- bit information input 55 of the search strategy register 5 and the corresponding n-th bit of the N-bit information input 011 of the device. Inverse inputs "Choice of crystal" 5.2-1 (input $$\overline{CS}$$

) and “Read / Write” 5.2-4 (input $$\overline{WE}$$

) of random access memory 5.2 are the corresponding inputs “Choice of crystal” 56 and “Read / write” 57 of the search strategy register 5, as well as the corresponding inputs “Choice of crystal” 012 and “Read / write” 013 of the device. Moreover, the k-th input 5.1-1 _{k of the} first group of information inputs 5.1-1 (A _k from the group A ₁ -A _k information inputs) of the selector 5.1 is the k-th bit of the K-bit input "Event code" 52 registers search strategy 5, and the k-th input 5.1-2 _{k of the} second group of information inputs 5.1-2 (B _k from the group B ₁ -B _{K of} information inputs) of the multiplexer selector 5.1 is the k-th bit of the K-bit address input 53 of the strategy register search 5 and the corresponding kth bit of the K-bit address input 09 of the device. The control input 5.1-3 (input SE) of the selector of the multiplexer 5.1 is the control input 54 of the search strategy register 5 and the control input 010 of the information search device.

The selector-multiplexer 5.1 of the search strategy register 5 is intended for switching one of two groups of information inputs to its outputs. The implementation scheme of such a selector-multiplexer is known, described in the prototype (see RF patent No. 2313128 "Information retrieval device" IPC G06F 9/46, 12/20/2007, bull. 35, Fig. 5) and can be technically implemented, for example , as described in [Maltsev P.P., Dolidze N.S. and others. Digital integrated circuits: a reference. - M .: Radio and communications, 1994, p. 33-40].

Random access memory 5.2 of the search strategy register 5 is intended for storing masks containing rules that determine the required sequence of identified elements of the incoming data stream. The implementation scheme of such a random access memory device is known, described in the prototype (see RF patent No. 2313128 "Information retrieval device" IPC G06F 9/46, 12/20/2007, bull. 35, Fig. 5) and can be technically implemented, for example , as described in [Shilo V.L. Popular digital circuits. - M.: Radio and Communications, 1987, p. 164-166].

The three-input elements OR NOT 5.3 ₁ -5.3 _{N of the} search strategy register 5 are identical and are designed to obtain a logical zero at their outputs if there is a logical unit at the resolving input of the search strategy register 5 and to obtain a logical unit at the outputs otherwise, regardless of logical values set on the first and second inputs of three-input elements OR NOT. These elements are widespread, commercially available, the scheme of their implementation and the operation algorithm of such three-input elements are NOT known and described in detail in the prototype (see RF patent No. 2313128 "Information retrieval device" IPC G06F 9/46, 12.20.2007. , bull. 35, Fig. 5).

The OR element 5.4 with N inputs, built into the block diagram of the search strategy register 5, is designed to combine signals of a certain logical level coming from the outputs of the three-input elements OR-NOT 5.3 ₁ -5.3 _N. This element is widespread, commercially available, the implementation scheme and the operation algorithm of such an N-input element OR are known and described in detail in the prototype (see RF patent No. 2313128 "Information retrieval device" IPC G06F 9/46, 20.12.2007, bull. 35, Fig. 5).

из состава $${\overline{Y}}_1-{\overline{Y}}_K$$

инверсных выходов) шифратора 6.1, n-ый инверсный вход 6.1-1_n которого (вход $${\overline{X}}_n$$

из состава $${\overline{X}}_1-{\overline{X}}_N$$

инверсных входов) является n-ым входом «Результат сравнения» 61_n (из состава 61₁-61_N входов «Результат сравнения») блока формирования адреса вектора переходов 6.The unit for generating the address of the transition mask 6, which is part of the general block diagram, is designed to generate and store a code corresponding to the mask defining the next element that should be identified in the incoming data stream. The structure of the transition mask address generating unit is known, described in the prototype (see RF patent No. 2313128 “Information Search Device” IPC G06F 9/46, December 20, 2007, bull. 35) and is shown in FIG. 8. The block for generating the address of transition mask 6 consists of an encoder 6.1, K inverters 6.2 ₁ -6.2 _K , a two-input OR element 6.3 and a register 6.4, k-th (where k = 1, 2, ..., K) information output 6.4-4 _k (Q _k from the composition of Q ₁ -Q _K information inputs) which is the k-th bit of the K-bit output “Event code” 62 of the transition mask address generating unit 6. Moreover, the k-th information input is 6.4-2 _k (D _k from the composition of D ₁ -D _k information inputs) of the register 6.4 is connected to the inverse output 6.2 _k -2 of the k-th inverter 6.2 _k . The write enable input 6.4-1 (input C) of register 6.4 is the signal input 65 of the block for generating the address of transition mask 6. The reset input 6.4-3 (input R) of register 6.4 is connected to the output 6.3-3 of the two-input element OR 6.3, the first input 6.3-1 which is the “Reset” input 64 of the transition mask address generation unit 6. The second input 6.3-2 of the two-input OR element 6.3 is the “Initial reset” input 63 of the transition mask address generation unit 6 and the “Initial reset” input 05 of the device. Input 6.2 _k -1 of the k-th inverter 6.2 _k (from the composition of 6.2 ₁ -6.2 _K inverters) is connected to the corresponding 6.1-2 _k k-th inverse output (output $${\overline{Y}}_k$$

from the composition $${\overline{Y}}_{\mathrm{one}}-{\overline{Y}}_K$$

inverse outputs) of the encoder 6.1, the n-th inverse input 6.1-1 _{n of} which (input $${\overline{X}}_n$$

from the composition $${\overline{X}}_{\mathrm{one}}-{\overline{X}}_N$$

inverted inputs) is the nth input “Comparison Result” 61 _n (out of 61 ₁ -61 _N inputs “Comparison Result”) of the transition vector address generation unit 6.

The encoder 6.1 of the transition mask address generating unit 6 is intended to generate a code corresponding to the mask defining the next element to be identified in the incoming data stream by converting a low-level signal at one of its inputs to the corresponding binary code at its outputs. The implementation scheme of such an encoder is known, described in the prototype (see RF patent No. 2313128 "Information retrieval device" IPC G06F 9/46, 12/20/2007, bull. 35, Fig. 6) and can be technically implemented, for example, as described in [Maltsev P.P., Dolidze N.S. et al. Digital Integrated Circuits: A Guide. - M .: Radio and communications, 1994, p. 40-41].

Inverters 6.2 ₁ -6.2 _{K of the} block for generating the address of transition mask 6 are identical and are designed to convert signals of a logical unit value to a logical zero value and inverse conversion depending on the signals at their inputs, determined by the values from the outputs of the encoder 6.1. The implementation scheme of such inverters is known, described in the prototype (see RF patent No. 2313128 "Information retrieval device" IPC G06F 9/46, 20.12.2007, bull. 35, Fig. 6), they can be technically implemented in the form of elements NOT, in accordance with the description given in [Gusev VV, Lebedev ON, Sidorov AM Fundamentals of pulsed and digital technology. - SPb .: SPVVIUS, 1995.S. 14, Fig. 1.3].

The two-input element OR 6.3 of the transition mask address generation unit 6 is intended for combining signals of a certain logical level coming from the “Initial reset” input of the device and the “Reset” input 64 of the transition mask address formation unit 6, respectively. The structure of the two-input OR element is known, described in the prototype (see RF patent No. 2313128 "Information retrieval device" IPC G06F 9/46, 20.12.2007, bull. 35, Fig. 6), the element can be technically implemented on the basis of serial manufactured element OR, described in detail in [Gusev VV, Lebedev ON, Sidorov AM Fundamentals of pulsed and digital technology. - SPb .: SPVVIUS, 1995.S. 24-26, Fig. 1.7].

Register 6.4 of the block forming the address of the transition mask 6 is intended for storing a code corresponding to the mask defining the next element that should be identified in the incoming data stream. The implementation scheme of such a register is known, described in the prototype (see RF patent No. 2313128 "Information retrieval device" IPC G06F 9/46, December 20, 2007, bull. 35, Fig. 6), the register can be technically implemented, for example, as described in [Maltsev P.P., Dolidze N.S. et al. Digital Integrated Circuits: A Guide. - M .: Radio and communications, 1994, p. 57-62].

из состава $${\overline{X}}_1-{\overline{X}}_N$$

инверсных выходов) дешифратора 7.1, а второй вход 7.2_n-2 n-го двухвходового элемента ИЛИ 7.2_n является n-ым разрядом N-разрядного входа «Правило завершения поиска» 72 блока индикации 7 и соответствующим n-ым разрядом N-разрядного входа «Правило завершения поиска» 07 устройства. Причем k-ый вход 7.1-1_k (вход Y_k из состава Y₁-Y_K входов) дешифратора 7.1 является k-ым разрядом K-разрядного адресного входа «Код события» 71 блока индикации 7.The display unit 7, which is part of the general structural diagram, is designed to detect signs indicating the completion of the sequence of elements of the incoming data stream specified by the rules and the formation of the corresponding signal. The structure of the display unit is known, described in the prototype (see RF patent No. 2313128 "Information retrieval device" IPC G06F 9/46, 12/20/2007, bull. 35) and is shown in FIG. 9. The display unit 7 consists of a decoder 7.1, N two-input elements OR 7.2 ₁ -7.2 _N and an N-input element AND 7.3, the output 7.3-2 of which is the output “Search result” 73 of the display unit 7 and the output “Search result” 015 of the device . Moreover, the n-th input 7.3-1 _n (from the composition 7.3-1 ₁ -7.3-1 _N inputs) of the N-input element AND 7.3 is connected to the output 7.2 ₁ -3 of the corresponding n-th two-input element OR 7.2 _n (from the composition 7.2 ₁ -7.2 _N two-input elements OR). The first input 7.2 _n -1 of the n-th two-input element OR 7.2 _{n is} connected to the corresponding n-th inverse output 7.1-2 _n (output $${\overline{X}}_n$$

from the composition $${\overline{X}}_{\mathrm{one}}-{\overline{X}}_N$$

inverted outputs) of the decoder 7.1, and the second input 7.2 _n -2 of the n-th two-input element OR 7.2 _n is the n-th digit of the N-bit input "Search termination rule" 72 of display unit 7 and the corresponding n-th bit of the N-bit input " Search termination rule »07 devices. Moreover, the k-th input 7.1-1 _k (input Y _k from the composition of Y ₁ -Y _K inputs) of the decoder 7.1 is the k-th bit of the K-bit address input "Event code" 71 of the display unit 7.

The decoder 7.1 of the display unit 7 is designed to convert the binary code received at its input into a low-level signal at the corresponding output. The implementation scheme of the decoder is known, described in the prototype (see RF patent No. 2313128 "Information retrieval device" IPC G06F 9/46, 20.12.2007, bull. 35, Fig. 7), the decoder can be technically implemented, for example, as described in the book [Maltsev P. P., Dolidze N. S. and others. Digital integrated circuits: a reference. - M .: Radio and communications, 1994, p. 41-47].

The two-input elements OR 7.2 ₁ -7.2 _N of the display unit 7 are identical and are intended for combining signals of a certain logical level coming from the inverse outputs of the decoder 7.1 and the input "Search completion rule" of the device. The structure of the two-input elements OR is known, described in the prototype (see RF patent No. 2313128 "Information retrieval device" IPC G06F 9/46, 12/20/2007, bull. 35, Fig. 7), these elements can be technically implemented on the basis of commercially available element OR, described in detail in [Gusev VV, Lebedev ON, Sidorov AM Fundamentals of pulse and digital technology. - SPb .: SPVVIUS, 1995.S. 24-26, Fig. 1.7].

The N-input element AND 7.3, which is part of the display unit 7, is designed to register the results of search queries, obtain and record the final search result. The circuit of the N-input element And is known, described in the prototype (see RF patent No. 2313128 "Information retrieval device" IPC G06F 9/46, 12/20/2007, bull. 35, Fig. 7), this element can be technically implemented based on the mass-produced multi-input element And described in the book [Gusev VV, Lebedev ON, Sidorov AM Fundamentals of pulsed and digital technology. - SPb .: SPVVIUS, 1995.S. 14, Fig. 1.3].

The information retrieval device operates as follows.

It is known [1-5] that from the point of view of increasing the likelihood of timely information retrieval in conditions inherent in the real process of functioning of modern data networks with packet switching, modern information and reference (search) systems - in the conditions of continuous dynamics of changing states of information search requests and taking into account the influencing factors, it is possible to vary the time of information search. This feature is implemented on the basis of the principle of dynamic correction of values (boundaries) of the maximum search time for each search query.

It is obvious that when processing search queries, not only the control actions on the information-reference (search) system or external factors objectively change in time, but also the current requirements of the subscribers of this system to the quality and timeliness of information search. In these conditions, timely search is difficult, which directly depends on the dynamics of changes in time of parameters, modes and methods of implementing search queries, on the dynamics of internal and external influences on the information-reference (search) system, as well as on the dynamics of changes in requirements, goals and objectives of the search due to the specific situation.

An analysis of works [1-5] devoted to algorithms and principles of servicing subscriber requests within complex technical systems allows us to conclude that it is possible to implement procedures to increase the likelihood of timely information retrieval based on the technical implementation of the principle of dynamic correction of values (boundaries) of maximum search time for each search query in the context of continuous dynamics of the change of state of search queries and taking into account influencing factors.

The construction of an information retrieval device based on the proposed principle of operation allows one to gain an advantage over the prototype, providing an increase in the likelihood of timely provision of search results to users within the framework of a real information and inquiry (search) system, when subscribers' search queries in the dynamics of the functioning of this system can change threshold values of their states under the influence of control actions (current requirements) of subscribers or external factors.

The technical implementation of the principle of dynamic correction of values (boundaries) of the maximum search time in the claimed device is carried out by introducing an external dynamic control of the search time (in the claimed device - S-bit inputs "Correction of the maximum search time" of the device) and the introduction of registration, control and dynamic correction of the maximum time the search for each keyword (implemented in the claimed device respectively within the block selection February ₁ -2 _N, breeding time controllers audio search August ₁ -8 _N and seek time main controller 9 via pulses generated clock generator 10).

In this case, as in the prototype, the claimed device implements a syntactic approach to pattern recognition [6], based on the identification of individual elements of the incoming data stream - BDI, by parallel analysis of the values of identification signs and control of their sequence for compliance with the given rules. As signs of identification, bit values are used in the corresponding BDI positions. The rules for following the BDI are set by the formal grammar - the search script. To explain the parallel analysis of the values of identification signs and control the order of their sequence, it is necessary to consider the rules for specifying a search script. The SC search script can be represented by the following scheme:

Where:

- множество типов БДИ, входящих в состав сценария;P = {P _n }, $$n=\overline{\mathrm{one,}N}$$

- many types of BDI included in the script;

- множество масок переходов;MP = {MP _n }, $$n=\overline{\mathrm{one,}N}$$

- many transition masks;

MB - mask of the beginning of the search script;

MF - mask for ending the search script;

T - waiting time for the next BDI.

The identification of the type of BDI in the device is carried out by comparing the values of the identification bits of the BDI with their reference values. By identification bits are meant bits of the BDI, the values of which allow you to uniquely identify the type of BDI. For each type of BDI, a plurality of identification bits may be individual. In this regard, two bit masks are associated with each type of BDI:

Where:

M1 _n is the first bit mask of the n-th type BDI;

M2 _n is the second bit mask of the BDI of the nth type.

Bit masks contain L bits, where L is the maximum possible number of bits in the BDI used in the search script. The first bitmask is used to indicate the positions of the IDI identification bits. The values of the logical unit in the bits of the first bitmask correspond to the positions of the identification bits. In all other bits of the bitmask, logical zero values are set. The second bitmask is designed to set the reference values to which the values of the identification bits must correspond. In this case, the bits of the second bitmask, which are not identification, can have arbitrary values, since they do not affect the process of identifying the BDI.

Many transition masks are used to set the order of the BDI in the script. The set contains N transition masks, each of which contains N binary digits. Thus, each type of BDI has its own transition mask. At the same time, the nth transition mask MP _n contains information about the types of BDI, which, according to the search scenario, are expected after observing the BDI of the n-th type. The specified information is set by setting the value of logical zero in the bits of the mask transitions, the sequence numbers of which correspond to the types of expected BDI. In all other digits of the transition mask, the values of the logical unit are set.

The mask for the beginning of the search script is intended to indicate the types of the BDI that are expected first in the search script - the initial BDI. The MB mask contains N binary bits. In the bits of the mask at the beginning of the search script, the numbers of which correspond to the initial types of BDIs, logical zero values are set. In all other digits of the mask, the beginning of the search script sets the values of the logical unit.

The mask of the end of the search script is intended to indicate the types of BDI, the observation of which indicates the completion of the search script - the final BDI. The MF mask contains N binary bits. In the bits of the mask of the end of the search script, the numbers of which correspond to the final types of the BDI, the logical zero values are set. In all other bits of the mask of the end of the search script, the values of the logical unit are set.

Unlike the search time, the waiting time for the next BDI T sets the maximum allowable time interval during which the next BDI specified by the type search script is expected. In the event that during the specified time interval the expected type of the BDI is not detected, the search script is interrupted and the transition to waiting for the initial BDI is performed. The waiting time for the next BDI is set in the form of an M-bit code. In this case, the smallest waiting time corresponds to the largest code, which is an addition to the maximum number represented in the M-bit code.

With this in mind, the claimed device provides controlled servicing of search queries and the implementation of time-varying needs of subscribers in identifying elements of the incoming data stream, which increase the likelihood of timely information retrieval.

In general, the operation of the information retrieval device can be considered as the process of transition of this device from state to state. Many states

, устройства соответствует множеству типов БДИ, входящих в состав сценария. При обнаружении очередного, заданного сценарием типа БДИ, устройство переходит в состояние, номер которого соответствует типу обнаруженного БДИ. Находясь в одном из состояний устройство ожидает появления БДИ, типы которых определяются маской переходов, номер которой соответствует номеру текущего состояния устройства.W = {W _n }, $$n=\overline{\mathrm{one,}N}$$

, the device corresponds to the many types of BDI that are part of the script. When it detects the next one specified by the script, the type of BDI, the device goes into a state whose number corresponds to the type of detected BDI. Being in one of the states, the device expects the appearance of a BDI, the types of which are determined by the transition mask, whose number corresponds to the number of the current state of the device.

In FIG. 10 shows an example search script including N = 8 types of BDI. The transition mask filling, the script start mask, and the script end mask corresponding to the search scenario shown are shown in FIG. eleven.

Initialization of the device includes the following operations:

initial reset of the device;

installation of the first and second bit masks;

setting the mask for the beginning of the script and transition masks;

setting the mask for ending the search script;

setting the waiting time for the next BDI;

setting the initial maximum search time.

The initial reset of the device is as follows. At the enable input 014 of the device, the value of the logical unit is set, which goes to the corresponding input 58 of the search strategy register 5. The logical unit at the enable input 58 of the register of search strategy 5, arriving at the third inputs 5.3 ₁ -3-5.3 _N -3 of all three-input elements OR- NOT 5.3 ₁ -5.3 _N (see Fig. 7), provides a logical zero at their outputs 5.3 ₁ -4-5.3 _N -4, regardless of the logical values set on the first 5.3 ₁ -1-5.3 _N -1 and second 5.3 ₁ -2- 5.3 _N -2 inputs. In this regard, the signal output 59 of the register of the search strategy 5 will be set to a logical zero. Logical zero from the signal output 59 of the search strategy register 5 is fed to the corresponding input 45 of the shaper of time intervals 4 and then to the first information input 4.2-1 (input J) of the JK trigger 4.2. At the input "Initial reset" 05 devices set the value of the logical unit, which is fed to the inputs 42 and 63 of the shaper time intervals 4 and the unit for generating the address of the transition mask 6, respectively. The value of the logical unit from the input "Initial reset" 42 shaper time intervals 4 (see Fig. 6) through the first two-input element OR 4.1, it goes to the second information input 4.2-2 (input K) of the JK trigger 4.2, and through the second two-input element OR 4.6 to the reset input (input R) of counter 4.7. -2 (inlet K) JK- Rigger 4.2 in the presence of a logical zero at its input 4.2-1 (input J) leads to a logical zero at the output 4.2-3 of the JK trigger 4.2, which, entering the second input 4.3-2 of the two-input element And 4.3, leads to the setting of the logical value zero at its output 4.3-3, regardless of the logical values at its first input 4.3-1.The logical unit at the reset input R of counter 4.7 provides a logical zero at its overflow output P. The logical zero value from the overflow output P of counter 4.7 is fed to the second input 4.5-2 of the second two the running element AND 4.5, which leads to the unconditional installation at its output 4.5-3, and accordingly at the output "Reset" 44 of the shaper time intervals 4, the value of the logical zero. The logical unit from the input "Initial reset" 63 of the block forming the address of the transition mask 6 (see Fig. 8) through a two-input element OR 6.3 is fed to the reset input 6.4-3 (input R) of register 6.4, which leads to the setting of a logic zero at its outputs 6.4-4 (Q ₁ -Q _K ), and, accordingly, on all bits of the K-bit output "Event code" 62. Upon completion of the initial reset operation at the input "Initial reset" 05 devices set the value of logical zero, which leads to the setting value logical zero at the second information input 4.2-2 (input K) JK-t rigger 4.2 and at the input of the reset R of the counter 4.7 of the shaper time intervals 4.

The installation of the first and second bit masks, providing the identification of each of the N types of BDI, is carried out in the corresponding blocks of mask storage 1 ₁ -1 _N. For this, the first L-bit inputs of Mask 1 02 ₁ -02 _{N of the} device and the corresponding first L-bit inputs of Mask 1 12 ₁ -12 _{N of} each of N mask storage blocks 1 ₁ -1 _N are set to the corresponding first bit masks, and at the first L-bit inputs "Mask 2" 03 ₁ -03 _{N of the} device and the corresponding first L-bit inputs "Mask 2" 13 ₁ -13 _{N of} each of the N storage blocks of the mask 1 ₁ -1 _N set the corresponding second bit masks. At the write enable input 01 of the device and at the corresponding write enable inputs 10 ₁ -10 _{N of} each of the N mask storage units 1 ₁ -1 _N set the value of the logical unit, which goes to the initialization inputs (inputs C) of the first and second registers 1.1 and 1.2 of each of N mask storage units (see Fig. 5) and provides the recording of the first and second bit masks in the corresponding registers. At the end of the write operation, the write enable input 01 of the device and the corresponding write enable inputs 10 ₁ -10 _{N of} each of the N mask storage units 1 ₁ -1 _N set the logical zero value.

, должна быть записана по адресу, соответствующему ее порядковому номеру, то есть адресу, значение которого равно n.Для этого на управляющем входе 010 устройства и, соответственно, на управляющем входе 54 регистра стратегии поиска 5 устанавливают значение логической единицы, которая, поступая на управляющий вход 5.1-3 (вход SE) селектора-мультиплексора 5.1 (см. фиг. 7), обеспечивает коммутацию второй группы информационных входов 5.1-2 (B₁-B_k) селектора-мультиплексора 5.1 на его выходы 5.1-4 (Q₁-Q_k), где K=(log₂N)+1 - количество двоичных разрядов, достаточное для адресации N масок переходов и маски начала сценария поиска. На N-разрядном адресном входе 09 устройства и, соответственно, на K-разрядном адресном входе 53 регистра стратегии поиска 5 устанавливают N-разрядный адрес, по которому в оперативное запоминающее устройство 5.2 должна быть записана маска начала сценария поиска. С выходов 5.1-4 (Q₁-Q_K) селектора-мультиплексора 5.1 K-разрядный адрес поступает на адресные входы 5.2-2 (A₁-A_K) оперативного запоминающего устройства 5.2. На N-разрядном информационном входе 011 устройства и, соответственно на TV-разрядном информационном входе 55 регистра стратегии поиска 5 устанавливают маску начала сценария поиска, которая поступает на информационные входы 5.2-3 (D₁-D_N) оперативного запоминающего устройства 5.2. Запись осуществляется путем установки логического нуля на входах «Выбор кристалла» 012 и «Чтение/запись» 013 устройства, с которых логический ноль через входы «Выбор кристалла» 56 и «Чтение/запись» 57 регистра стратегии поиска 5 поступает на соответствующие входы 5.2-1 $$(\overline{CS})$$

и 5.2-4 $$(\overline{WE})$$

оперативного запоминающего устройства 5.2. По окончании записи маски на входе «Выбор кристалла» 012 устанавливают значение логической единицы. Затем на K-разрядном адресном входе 09 устройства устанавливают K-разрядный адрес, по которому в оперативное запоминающее устройство 5.2 должна быть записана первая маска переходов MP₁ (значение адреса равно 1), а на TV-разрядном информационном входе 011 устройства устанавливают маску переходов MP₁, после чего путем установки значения логического нуля на входе «Выбор кристалла» 012 инициируют операцию записи в оперативное запоминающее устройство 5.2. Аналогичным образом в оперативное запоминающее устройство записывают все N масок переходов. По окончании записи масок переходов в оперативное запоминающее устройство 5.2 на входе «Чтение/запись» 013 устанавливают значение логической единицы, а на управляющем входе 010 устройства устанавливают значение логического нуля, что обеспечивает коммутацию первой группы информационных входов 5.1-1 (A₁-A_k) селектора-мультиплексора 5.1 на его выходы 5.1-4 (Q₁-Q_K).The mask of the beginning of the search script and transition masks are set in the random access memory 5.2 of the search strategy register 5. In this case, the mask of the beginning of the search script MB must be written to the random access memory at the zero address, and the nth transition mask MP _n , $$n=\overline{\mathrm{one,}N}$$

, must be recorded at the address corresponding to its serial number, that is, an address whose value is n. For this, at the control input 010 of the device and, accordingly, at the control input 54 of the search strategy register 5, set the value of the logical unit, which, arriving at the control input 5.1-3 (input SE) of the selector-multiplexer 5.1 (see Fig. 7), provides switching of the second group of information inputs 5.1-2 (B ₁ -B _k ) of the selector-multiplexer 5.1 to its outputs 5.1-4 (Q ₁ - Q _k ), where K = (log ₂ N) +1 is the number of binary bits sufficient for a draces N transition masks and masks at the beginning of the search script. At the N-bit address input 09 of the device and, respectively, at the K-bit address input 53 of the search strategy register 5, an N-bit address is set at which the mask for starting the search script should be written to the random access memory 5.2. From the outputs 5.1-4 (Q ₁ -Q _K ) of the selector-multiplexer 5.1, the K-bit address is supplied to the address inputs 5.2-2 (A ₁ -A _K ) of the random access memory 5.2. On the N-bit information input 011 of the device and, accordingly, on the TV-bit information input 55 of the search strategy register 5, a mask for the beginning of the search script is set, which is fed to the information inputs 5.2-3 (D ₁ -D _N ) of the random access memory 5.2. Writing is performed by setting a logical zero at the inputs “Choice of crystal” 012 and “Read / write” 013 of the device from which a logical zero through the inputs “Choice of crystal” 56 and “Read / write” 57 of the search strategy register 5 is fed to the corresponding inputs 5.2- one $$(\overline{CS})$$

and 5.2-4 $$(\overline{WE})$$

random access memory 5.2. At the end of the recording mask at the input of "Crystal Select" 012 set the value of the logical unit. Then, a K-bit address is set at the K-bit address input 09 of the device, at which the first transition mask MP ₁ (the address value is 1) should be written to the RAM 5.2 and the MP transition mask is set to the TV-bit information input 011 ₁ , after which by setting the value of the logical zero at the input "Choice of crystal" 012 initiate the write operation in random access memory 5.2. Similarly, all N transition masks are written to the random access memory. At the end of writing the transition masks to random access memory 5.2, the logical value is set at the Read / Write input 013, and the logical zero value is set at the control input 010 of the device, which ensures switching of the first group of information inputs 5.1-1 (A ₁ -A _k ) selector-multiplexer 5.1 to its outputs 5.1-4 (Q ₁ -Q _K ).

Setting the mask for the end of the search script MF consists in setting the device and, therefore, on the bits of the N-bit input "Search completion rule" 72 of display unit 7 (see Fig. 9) the corresponding logical values corresponding to the values of the bits of the mask end of the search script.

Setting the waiting time for the next BDI is to set the device on the bits of the M-bit input "Time-out code" 06 and, therefore, on the bits of the M-bit input "Time-out code" 43 of the time interval shaper 4 (see Fig. 6), logical values corresponding to the digits of the timeout code.

поискового запроса - набора конкретных типов БДИ (определяющего соответствующие маски переходов и характеризующего конкретный сценарий поиска).Setting the initial maximum search time consists in installing on the bits of each of the N S-bit inputs “Correction of the maximum search time” 016 ₁ -016 _N devices (see Fig. 3) through S-bit inputs 27 ₁ -27 _N selection blocks 2 ₁ -2 _N to S-bit inputs 2.7 ₁ -1-2.7 _N -1 correction registers 2.7 ₁ -2.7 _N logical values of the code that sets the initial maximum search time for each n-th $$(n=\overline{\mathrm{one,}N})$$

search query - a set of specific types of BDI (defining the appropriate transition masks and characterizing a specific search scenario).

After performing these operations, the device is ready for operation.

будет установлено значение логической единицы. Значения логической единицы с инверсных выходов $$\text{7}{\text{.1-2}}_{\text{1}}\text{-7}{\text{.1-2}}_{\text{N}}\text{ (}{\overline{\text{X}}}_{\text{1}}\text{-}{\overline{\text{X}}}_{\text{N}}\text{)}$$

дешифратора 7.1 поступает на первые входы 7.2₁-1-7.2_N-1 соответствующих двухвходовых элементов ИЛИ 7.2₁-7.2_N. В результате на выходах 7.2₁-3-7.2_N-3 всех двухвходовых элементов ИЛИ 7.2₁-7.2_N устанавливается значение логической единицы вне зависимости от логических значений на их вторых входах. Это приводит к установке значения логической единицы на выходе 7.3-2 N-входового элемента И 7.3, а соответственно и на выходе «Результат поиска» 015 устройства. Логические значения на выходе «Результат поиска» 015 устройства имеют следующее значение: логический ноль на указанном выходе означает, что во входящем потоке БДИ обнаружен заданный сценарий поиска, а логическая единица - отсутствие заданного сценария поиска. На входе «Чтение/запись» 57 регистра стратегии поиска 5 установлено значение логической единицы, что обеспечивает перевод оперативного запоминающего устройства 5.2 в режим чтения информации. При этом на входе «Выбор кристалла» 56 регистра стратегии поиска 5 также, установлено значение логической единицы. На разрешающем входе 014 устройства и, соответственно на разрешающем входе 58 регистра стратегии поиска 5 установлено значение логической единицы, что обеспечивает установку на сигнальном выходе 59 регистра стратегии поиска 5 значения логического нуля. При этом на выходе 4.2-3 JK-триггера 4.2 формирователя временных интервалов 4 (см. фиг. 6), на его первом 4.2-1 (вход J) и втором 4.2-2 (вход K) информационных входах установлено значение логического нуля.In the initial period, when the BDIs to be analyzed do not arrive at the input of the device, clock pulses are received from the external generator to the input 38 of the frequency divider 3 through the first clock input 08 of the device. From the output 39 of the frequency divider 3, clock pulses are fed to the second clock input 41 of the shaper of time intervals 4. As a result of the operation of the initial reset of the device at all information outputs 6.4-4 (Q ₁ -Q _N ) of register 6.4, and, accordingly, at all bits K -bit output "Event code" 62 block formation mask transitions 6 set to logical zero. At the control input 54 of the search strategy register 5, a logical zero value is set, which ensures switching of logical zero values from the bits of the K-bit input "Event code" 52 of the search strategy register 5 to the corresponding address inputs 5.2-2 (A ₁ -A _K ) of random access memory devices 5.2. Thus, a zero address is set at the address input of random access memory pointing to the mask of the beginning of the search script. The values of logical zero from the bits of the K-bit output “Event code” 62 of the block for generating the address of the transition mask 6 go to the corresponding bits of the input “Event code” 71 of the display unit 7 and then to the inputs 7.1-1 ₁ -7.1-1 _N (Y ₁ -Y _K ) of the 7.1 decoder (see FIG. 9). If there is a logical zero value at all inputs 7.1-1 ₁ -7.1-1 _K (Y ₁ -Y _K ) of the 7.1 decoder, at all its inverse outputs $$\text{7}{\text{.1-2}}_{\text{one}}\text{-7}{\text{.1-2}}_{\text{N}}({\overline{X}}_{\mathrm{one}}-{\overline{X}}_N)$$

the logical unit value will be set. Logic Unit Values from Inverted Outputs $$\text{7}{\text{.1-2}}_{\text{one}}\text{-7}{\text{.1-2}}_{\text{N}}\text{(}{\overline{\text{X}}}_{\text{one}}\text{-}{\overline{\text{X}}}_{\text{N}}\text{)}$$

the decoder 7.1 is supplied to the first inputs 7.2 ₁ -1-7.2 _N -1 of the corresponding two-input elements OR 7.2 ₁ -7.2 _N. As a result, at the outputs 7.2 ₁ -3-7.2 _N -3 of all two-input elements OR 7.2 ₁ -7.2 _N , the value of the logical unit is set regardless of the logical values at their second inputs. This leads to setting the value of the logical unit at the output 7.3-2 of the N-input element AND 7.3, and, accordingly, at the output “Search result” 015 of the device. Logical values at the “Search Result” output 015 of the device have the following meaning: a logical zero at the specified output means that a specified search script has been detected in the incoming BDI stream, and a logical unit is the absence of a specified search script. At the input "Read / write" 57 register search strategy 5, the value of the logical unit is set, which ensures the transfer of random access memory 5.2 in the reading mode. At the same time, at the input "Choice of crystal" 56 register search strategy 5 also set the value of the logical unit. At the enable input 014 of the device and, respectively, at the enable input 58 of the search strategy register 5, a logical unit value is set, which ensures that the logic output 59 of the search strategy register 5 is set to a logical zero. At the same time, the output 4.2-3 of the JK-trigger 4.2 of the shaper of time intervals 4 (see Fig. 6), at its first 4.2-1 (input J) and second 4.2-2 (input K) information inputs, the value of logical zero is set.

Upon receipt of the BDI to be analyzed, the logical values corresponding to the binary bits of the BDI are set at the Z-bit information input 04 of the device. The moment of time corresponding to the installation of the BDI on the L-bit information input 04 of the device is denoted by T ₁ . From the L-bit information input 04 of the device BDI is fed to the L-bit information inputs 21 ₁ -21 _N selection blocks 2 ₁ -2 _N. Each selection block identifies the BDI of the corresponding type. The type of BDI is determined by the first and second bit masks, respectively, supplied to the second L-bit inputs "Mask 1" 22 ₁ -22 _N and the second L-bit inputs "Mask 2" 23 ₁ -23 _N selection blocks 2 ₁ -2 _N. In comparators 2.3 of each selection block 2 ₁ -2 _N (see Fig. 4), the values of the identification bits of the incoming BDI are compared with the values of the corresponding bits of the second bitmask. Identification bits are allocated in the first and second groups of two-input elements AND 2.1 ₁ -2.1 _L , 2.2 ₁ 1-2.2 _{L of} each selection block based on the corresponding first bit mask. In case of equality of the compared values at the output of the equality "A = B" 2.3-3 of the comparator 2.3, the value of the logical unit is set, otherwise, the value of the logical zero. The logical value corresponding to the comparison result from the output “A = B” 2.3-3 of comparator 2.3 in the case when only the initial maximum search time is set and there is no external dynamic control of the search time (there are no signals on the bits of each of the N S-bit inputs “Correction maximum search time "016 ₁ -016 _N devices), is inverted by the inverter 2.4 and goes to the output" Result of comparison "26 block selection 2.

In other words, if, during the analysis of incoming BDIs, there is no external dynamic control of the search time for all N search queries, on S-bit correcting inputs 27 ₁ -27 _N selection blocks 2 ₁ -2 _N , and therefore on S-bit inputs 2.7 ₁ -1-2.7 _N -1 correction registers 2.7 ₁ -2.7 _N , no code signals. In this case, the correction registers 2.7 ₁ -2.7 _N of the selection blocks 2 ₁ -2 _N (see Fig. 4) identify the initial search time codes as uncorrectable and translate (rewrite) them each through its S outputs (2.7 ₁ -2 ₁ -2.7 ₁ -2 _S ) - (2.7 _N -2 ₁ -2.1 _N -2 _S ) to the corresponding S information inputs (D ₁ -D _S ) of the corresponding counters 2.5 ₁ -2.5 _N selection blocks 2 ₁ -2 _N.

поискового запроса - набора конкретных типов БДИ (например, если изменились требования к своевременности всех, нескольких из N или конкретного поискового запроса в условиях объективно изменяющихся во времени целей и задач поиска информации и с учетом влияющих факторов), с внешнего устройства в S-разрядном коде (либо с помощью человека-оператора, либо с помощью специального управляющего устройства), через N S-разрядных входов «Коррекция максимального времени поиска» 016₁-016_N устройства на N S-разрядных входов 91₁-91_N главного контроллера времени поиска 9 (см. фиг. 3) поступают новые, дополнительно вводимые в динамике управления поиском, значения максимального времени поиска для конкретных поисковых запросов абонентов информационно-справочной (поисковой) системы.If during the identification of elements of the incoming data stream, external dynamic control of the search time for any nth $$(n=\overline{\mathrm{one,}N})$$

search query - a set of specific types of BDI (for example, if the requirements for the timeliness of all, several of N, or a specific search query have changed under the conditions of objectives and tasks of information retrieval, which take into account influencing factors), from an external device in S-bit code (either using a human operator, or using a special control device), through N S-bit inputs “Correction of the maximum search time” 016 ₁ -016 _N devices on N S-bit inputs 91 ₁ -91 _{N of the} main time controller and search 9 (see Fig. 3), new, additionally introduced in the dynamics of search control, values of the maximum search time for specific search queries of subscribers of the information-reference (search) system come in.

The main search time controller 9 may be implemented in accordance with the circuit shown in FIG. 3. Dynamic correction of the values (boundaries) of the maximum search time for all, several of N or a specific search query is carried out in the main controller of the search time 9 as follows.

New, additionally introduced in the dynamics of search control, values of the maximum search time for specific search queries of subscribers, in the S-bit code, comes through N S-bit inputs 91 ₁ -91 _{N of the} main controller of the search time 9 to N S-bit inputs 9.1-1 ₁ -9.1-1 _{N of the} recording element of the search time 9.1 for monitoring and registration. From N S-bit outputs 9.1-2 ₁ -9.1-2 _{N of the} recording element of the search time 9.1 new values of the maximum search time are supplied to the corresponding N S-bit inputs 9.2-1 ₁ -9.2-1 _N of the storage element of the new value of the search time 9.2, which writes and stores these values in the S-bit code until the next control action is introduced, as well as from its N S-bit outputs 9.2-2 ₁ -9.2-2 _N , through the corresponding N S-bit outputs 92 ₁ -92 _{N of the} main search time controller 9, transmits these new values of the maximum search time n and the correcting inputs 27 ₁ -27 _{N of the} corresponding selection blocks 2 ₁ -2 _N and the test inputs 82 ₁ -82 _{N of the} corresponding selection controllers search time 8 ₁ -8 _N.

At the same time, on S-bit correcting inputs 27 ₁ -21 _N selection blocks 2 ₁ -2 _N , and therefore on S-bit inputs 2.7 ₁ -1-2.7 _N -1 correcting registers 2.1 ₁ -2.1 _N , there are S-bit code signals. The correction registers 2.1 ₁ -2.1 _N selection blocks 2 ₁ -2 _N (see Fig. 4) register the initial code (recorded when preparing the device for operation, i.e., the initial maximum search time) and pre-compare it with the newly entered dynamics control S-bit code, which is received through the correction inputs 2 ₁ -21 _N selection blocks 2 ₁ -2 _N to S-bit inputs 2.7 ₁ -1-2.7 _N -1 correction registers 2.7 ₁ -2.7 _N.

блока селекции 2_n. Если на S-разрядном входе 2.7_n-1 корректирующего регистра 2.7_n нет S-разрядного сигнала, обуславливающего новое, вводимое в динамике управления максимальное время поиска, то приоритетными признаются ранее записанные значения кода, задающего начальное максимальное время поиска.Moreover, correction (formation based on the results of preliminary comparison) at S outputs 2.7 _n -2 ₁ -2.7 _n -2 _S for example, a correction register 2.7 _n selection block 2 _n code characterizing a preliminary decision on the value of the maximum search time for each specific n the request is as follows (see Fig. 4). If there is an S-bit signal at the S-bit input 2.7 _n -1 of the correction register 2.7 _n that causes a new maximum search time entered in the control dynamics, this signal is identified as priority, and it is it from S outputs 2.7 _n -2 ₁ -2.7 _n -2 _{S of the} correction register 2.7 _{n is} supplied to the corresponding S information inputs (D ₁ -D _S ) of the counter 2.5 _n n-th $$(n=\overline{\mathrm{one,}N})$$

selection block 2 _n . If at the S-bit input 2.7 _n -1 of the correction register 2.7 _n there is no S-bit signal causing a new maximum search time entered in the control dynamics, the previously recorded values of the code specifying the initial maximum search time are recognized as priority.

блока селекции 2_n либо изначально введенное, либо новое, вводимое в динамике управления процессом идентификации элементов входящего потока данных, значение кода, задающие максимальное время поиска. Тем самым обеспечивается инициализация счетчиков 2.5₁-2.5_N блоков селекции 2₁-2_N. Причем наименьшему времени поиска соответствует наибольший код, являющийся дополнением до максимального числа, представимого в S-разрядном коде.Thus, from S outputs 2.7 _n -2 ₁ -2.7 _n -2 _{S of the} correction register, 2.7 _n goes to the corresponding S information inputs (D ₁ -D _S ) of the counter 2.5 _n n-th $$(n=\overline{\mathrm{one,}N})$$

of the selection block 2 _{n is} either initially introduced or new, introduced in the dynamics of controlling the process of identifying elements of the incoming data stream, the code value that sets the maximum search time. This ensures the initialization of the counters 2.5 ₁ -2.5 _N selection blocks 2 ₁ -2 _N. Moreover, the smallest search time corresponds to the largest code, which is an addition to the maximum number represented in the S-bit code.

In the initial period, when the BDIs to be analyzed do not enter the input of the device, the logical value corresponding to the comparison results does not have a 2.3 _n -3 comparator 2.3 _n at the output “A = B” 2.3. Three-input elements And 2.6 ₁ -2.6 _{N of} all selection units are closed, clock pulses from the clock generator 10 through three-input elements And 2.6 ₁ -2.6 _N to the counting inputs Z of counters 2.5 ₁ -2.5 _N selection blocks 2 ₁ -2 _{N are} not received. At the outputs “Comparison result” 26 ₁ -26 _N selection blocks 2 ₁ -2 _N signal is absent.

счетчиков 2.5₁-2.5_N через установленный интервал времени, определяемый кодами начального заполнения счетчиков и частотой тактовых импульсов.If the logical values corresponding to the comparison results from the outputs “A = B” 2.3 ₁ -3-2.3 _N -3 comparators 2.3 ₁ -2.3 _N selection blocks 2 ₁ -2 _N are received, at the outputs 26 ₁ -26 _N these blocks through inverters 2.4 ₁ -2.4 _N preset low level signals. To the counting inputs Z of counters 2.5 ₁ -2.5 _N selection blocks 2 ₁ -2 _N , pulses are received from the output of 101 clock pulses 10 along the circuit: clock inputs 25 ₁ -25 _N selection blocks 2 ₁ -2 _N , open three-input elements And 2.6 ₁ -2.6 _N selection blocks 2 ₁ -2 _N. Counters 2.5 ₁ -2.5 _{N of} each selection block perform the function of timers that control the expiration of the allowable time (initial or entered as part of the control) of the search by summing the clock pulses arriving at their counting input Z and generate an overflow signal at the inverse outputs $$\overline{P}$$

counters 2.5 ₁ -2.5 _N after a set time interval determined by the codes for the initial filling of the counters and the frequency of the clock pulses.

The signals from the outputs of the “Comparison Result” 26 ₁ -26 _N selection blocks 2 ₁ -2 _N are received through the inputs “Comparison Result” 81 ₁ -81 _{N of the} search time selector controllers 8 ₁ -8 _N (see Fig. 2) to the signal inputs 8.2 ₁ -1-8.2 _N -1 registers of comparison-correction of the maximum search time 8.2 ₁ -8.2 _N , to the test inputs 8.2 ₁ -2-8.2 _N -2 of which come in binary code from the test outputs 8.1 ₁ -2-8.1 _N - 2 decoders of the corrected code of the maximum search time 8.1 ₁ -8.1 _N signals characterizing the new value (limits) of the maximum entered in the control process search time for a specific request. At the same time, the decoders of the corrected code for the maximum search time 8.1 ₁ -8.1 _N convert the S-bit code, which determines the new values entered in the control process, of the value (boundary) of the maximum search time into binary code and transmits this code for checking the truth to the maximum comparison-correction registers search time 8.2 ₁ -8.2 _N.

The comparison-correction registers of the maximum search time 8.2 ₁ -8.2 _N carry out an additional check (comparison) of fulfilling the requirements for timeliness in accordance with the initial and newly entered maximum search time and, acting as relay nodes, form 8.2 ₁ -3-8.2 at their outputs _N -3 and at the outputs “Comparison Result” 83 ₁ -83 _N selection search time controllers 8 ₁ -8 _N sequence of signals describing logical values corresponding to the comparison results.

Thus, at the outputs “Comparison Result” of 83 ₁ -83 _N selection controllers for search time 8 ₁ -8 _N we have logical values corresponding to the comparison results and obtained taking into account the dynamic correction of the maximum search time.

After satisfying the need for information search, the n-th search query is removed, at the output “A = B” 2.3 _n -3 of the comparator 2.3 _{n there is} no signal, the counter 2.5 _{n of the} corresponding selection block 2 _n at the nth input “Zeroing” is reset 017 _n device and input "Zeroing" 24 _{n of the} corresponding selection block 2 _n .

, а, следовательно и на выходах «Результат сравнения» 26₁-26_N соответствующих блоков селекции 2₁-2_N сигнала переполнения, инициирующего блокирование выхода 2.4_n-2 инвертора 2.4_n и разовое поступление с данного инверсного выхода логических значений, соответствующих результатам сравнения на данный, конкретный момент времени, без возможности продолжения поиска, что соответствует процедуре динамического управления поиском - переносу поисковых запросов заново в очередь на места, соответствующие их приоритетам.If one or several search queries reached the maximum search time or the maximum search time decreased as a result of dynamic correction (control), the counters 2.5 ₁ -2.5 _{N of the} corresponding selection blocks 2 ₁ -2 _{N are} overflowed, and overflow outputs form on their inverted outputs $$\overline{P}$$

, and, consequently, at the “Result of comparison” outputs 26 ₁ -26 _{N of the} corresponding selection blocks 2 ₁ -2 _{N of} the overflow signal, which initiates the blocking of the output 2.4 _n -2 of the inverter 2.4 _n and a one-time input of logical values corresponding to the comparison results from this inverse output at this particular moment in time, without the possibility of continuing the search, which corresponds to the dynamic search management procedure - transferring search queries again to the queue at the places corresponding to their priorities.

In this case, the corresponding three-input elements And 2.6 ₁ -2.6 _N are locked (Fig. 4), prohibiting the arrival of clock pulses to the counting inputs Z of the corresponding counters 2.5 ₁ -2.5 _N of the selection blocks 2 ₁ -2 _N.

Logical values corresponding to the comparison results and obtained taking into account the dynamic correction of the maximum search time from the “Comparison Result” outputs 83 ₁ -83 _N selection search time controllers 8 ₁ -8 _N are sent to the corresponding “Comparison Result” inputs 51 ₁ -51 _N strategy register search 5 and the corresponding inputs “Result of comparison” 61 ₁ -61 _N block formation address of the mask transitions 6.

At the same time, upon receipt of a BDI, the type of which corresponds to one of the BDI types provided in the search script, the output is “Comparison Result” 26 _n , for example, a selection block 2 _n and the corresponding output “Comparison Result” 83 _n selection search time controller 8 _n, where a match is found values BIA identification incoming bits with the corresponding values of the second bitmask is set to logic zero and the outputs of all other selection blocks and, consequently, selection controllers bp Search Meni - value logical one. Upon receipt of the BDI, not provided by the search script, at the outputs “Comparison Result” of all the selection units and, as a result, the outputs “Comparison Result” of the search time selector controllers, the logical unit value will be set.

In the register of the search strategy 5 (see Fig. 7), the correspondence identified by the selection blocks 2 ₁ -2 _N and checked, taking into account the dynamic correction of the maximum search time, is checked by the selection controllers for the search time 8 ₁ -8 _N , of the type of OBD type, expected according search script. The check is carried out regardless of the results of the identification of BDI in the selection blocks 2 ₁ -2 _N and correction (verification) in the selection controllers search time 8 ₁ -8 _N. The type (s) of the expected BDI are determined by the mask of the beginning of the search script or by the transition masks stored in the random access memory 5.2. The mask against which compliance is checked is determined by the K-bit address set on the address inputs 5.2-2 (inputs A ₁ -A _K ) of the random access memory 5.2. The address used is the code installed on the K-bit input “Event Code” 52 of the search strategy register 5. From the K-bit input “Event Code” 52, this code is sent to the first group of information inputs 5.1-1 (A ₁ -A _K ) selector-multiplexer 5.1, where if there is a logic zero value on the control input 5.1-3 (SE) of the selector-multiplexer 5.1, it is switched to the address inputs 5.2-2 of the random access memory 5.2. The corresponding mask is read by setting the logic zero value at the “Choice of Crystal” input 56 of the search strategy register 5. Setting the logic zero value at the “Choice of Crystal” input 56 of the search strategy register 5 should be carried out with a time delay relative to the time T ₁ determined by the delay time signal in the selection block and in the selection controller of the search time. Let us designate the time of setting a logic zero at the input “Choice of Crystal” 56 of the search strategy register 5 as T ₁ . Checking the correspondence of the identified BDI type to the type expected according to the search script is carried out by three-input elements OR-NOT 5.3 ₁ -5.3 _N. In this case, the first inputs 5.3 ₁ -1-5.3 _N -1 of the three-input elements OR NOT 5.3 ₁ -5.3 _N receive logical values from the outputs 83 ₁ -83 _{N of the} corresponding selection controllers for the search time 8 ₁ -8 _N , and the second inputs logical values corresponding to the mask read from the random access memory 5.2. The test results come from the outputs 5.3 ₁ -4-5.3 _N -4 of the three-input elements OR NOT 5.3 ₁ -5.3 _N to the corresponding inputs 5.4-1 ₁ -5.4-1 _{N of the} N-input element OR 5.4 after setting the logic zero value on the enable input 014 devices. Setting the value of logical zero at the enable input 014 of the device should be carried out with a time delay relative to time T ₂ , determined by the time of reading information from random access memory 5.2. Let us designate the time of setting a logical zero at the enable input 014 of the device as T ₃ . If the identified type of BDI coincides with one of the types expected according to the search scenario, the output of the corresponding three-input OR-NOT element, and, therefore, the signal output 59 of the search strategy register 5, will be set to the value of the logical unit, which is fed to the signal input 65 block forming the address of the mask transitions 6 and to the signal input 45 of the shaper time intervals 4.

шифратора 6.1 (нулевой вход $${\overline{X}}_0$$

шифратора 6.1 не используется, при этом на нем всегда должно быть установлено значение логической единицы «1»). Если поступивший БДИ идентифицирован одним из блоков селекции 2₁-2_N с учетом максимального времени поиска, на инверсном входе шифратора 6.1, номер которого соответствует номеру блока селекции, идентифицировавшего БДИ и номеру соответствующего селекционного контроллера времени поиска, будет установлено значение логического нуля, а на всех остальных инверсных входах - значение логической единицы. При этом на инверсных выходах $$\text{6}{\text{.1-2}}_{\text{1}}\text{-6}{\text{.1-2}}_{\text{K}}\left({\overline{\text{Y}}}_{\text{1}}\text{ - }{\overline{\text{Y}}}_{\text{K}}\right)$$

дешифратора 6.1 установится код, соответствующий инверсному представлению номера входа дешифратора, на котором установлено значение логического нуля. Инверторами 6.2₁-6.2_K данный код преобразуется в код типа БДИ, то есть код, соответствующий номеру блока селекции, идентифицировавшего поступивший БДИ и номеру соответствующего селекционного контроллера времени поиска. Данный код используется в качестве адреса, по которому в оперативном запоминающем устройстве 5.2 регистра стратегии поиска 5 хранится соответствующая маска переходов. С выходов 6.2₁-2-6.2_K-2 инверторов 6.2₁-6.2_K K-разрядный код типа БДИ поступает на соответствующие информационные входы 6.4-2₁-6.4-2_K(D₁-D_K) регистра 6.4. Запись кода типа БДИ в регистр 6.4 осуществляется только при поступлении на сигнальный вход 65 блока формирования адреса маски переходов 6 значения логической единицы, то есть только в том случае, когда в блоке стратегии поиска 5 будет обнаружено соответствие типа поступившего БДИ типу, ожидаемому согласно сценария поиска. В противном случае в регистре 6.4 сохраняется предыдущее значение кода типа БДИ. Таким образом, на K-разрядном выходе «Код события» 62 блока формирования адреса маски переходов 6 всегда установлен код, соответствующий адресу, по которому в оперативном запоминающем устройстве 5.2 регистра стратегии поиска 5 хранится маска переходов, определяющая тип (типы) ожидаемых, согласно сценария поиска, БДИ. С K-разрядного выхода «Код события» 62 блока формирования адреса маски переходов 6 код типа БДИ поступает на соответствующие K-разрядные входы «Код события» 52 и 71 регистра стратегии поиска 5 и блока индикации 7 соответственно.If you find, within a time period not exceeding the specified (maximum search time), that the type of incoming BDI matches the type expected according to the search script, in the block for generating the address of transition mask 6, based on the identification results of the received BDI, the address is generated by which in the random access memory 5.2 of the search strategy register 5, a transition mask is stored that defines the type (s) of the BDI that follows it. Logical values corresponding to the BDI identification results, taking into account the dynamic correction of the maximum search time, from the outputs of “Comparison Result” 83 ₁ -83 _N selection controllers for search time 8 ₁ -8 _N are sent to the corresponding inputs “Comparison Result” 61 ₁ -61 _N of the forming unit transition mask addresses 6 onwards (see Fig. 8) to the corresponding inverse inputs $$\text{6}{\text{.1-1}}_{\text{one}}\text{-6}{\text{.1-1}}_{\text{N}}\left({\overline{X}}_{\mathrm{one}}-{\overline{X}}_N\right)$$

6.1 encoder (zero input $${\overline{X}}_0$$

6.1 encoder is not used, and the logical unit value “1” must always be set on it). If the incoming BDI is identified by one of the selection blocks 2 ₁ -2 _N , taking into account the maximum search time, the inverse input of the encoder 6.1, whose number corresponds to the number of the selection block that identifies the BDI and the number of the corresponding selection search time controller, will be set to logical zero, and all other inverse inputs - the value of the logical unit. At the same time on inverse outputs $$\text{6}{\text{.1-2}}_{\text{one}}\text{-6}{\text{.1-2}}_{\text{K}}\left({\overline{\text{Y}}}_{\text{one}}\text{-}{\overline{\text{Y}}}_{\text{K}}\right)$$

of the decoder 6.1, a code is set corresponding to the inverse representation of the decoder's input number, on which the value of logical zero is set. Inverters 6.2 ₁ -6.2 _K, this code is converted into a code of type BDI, that is, a code corresponding to the number of the selection block that identified the incoming BDI and the number of the corresponding selection controller for the search time. This code is used as the address where the corresponding transition mask is stored in the random access memory 5.2 of the search strategy register 5. From the outputs of 6.2 ₁ -2-6.2 _K -2 inverters 6.2 ₁ -6.2 _K K-bit code type BDI is fed to the corresponding information inputs 6.4-2 ₁ -6.4-2 _K (D ₁ -D _K ) register 6.4. Writing a code of type BDI in register 6.4 is carried out only when a logical unit value is received at the signal input 65 of the unit for generating the transition mask address 6, that is, only when the type of the received BDI matches the type expected in the search script in the search strategy block 5 . Otherwise, in register 6.4, the previous value of the code of the BDI type is stored. Thus, on the K-bit output “Event Code” 62 of the transition mask address generation unit 6, a code is always set corresponding to the address at which the transition mask is stored in the random access memory 5.2 of the search strategy register 5, which determines the type (s) expected according to the scenario search, BDI. From the K-bit output “Event Code” 62 of the transition mask address generation unit 6, a BDI type code is supplied to the corresponding K-bit inputs “Event Code” 52 and 71 of the search strategy register 5 and display unit 7, respectively.

In the case of finding, for a given time, determined by the code of the maximum search time, matching the type of incoming BDI with the expected type, the value of the logical unit from the signal output 59 of the search strategy register 5 is fed to the corresponding signal input 45 of the time interval generator 4 (see Fig. 6). From the signal input 45 of the time interval shaper 4, the value of the logical unit is fed to the write enable input V of the counter 4.7 and the first information input 4.2-1 (input J) of the JK trigger 4.2. At the same time, the code for the waiting time for the next BDI installed on the M-bit input “Time-out code” 06 of the device is recorded in the counter 4.7 and generation of the logical unit value at the output 4.2-3 of the JK-trigger 4.2 (since at its second information input 4.2 -2 (input K) set to logical zero). The value of the logical unit from the output 4.2-3 of the JK trigger 4.2, arriving at the second input 4.3-2 of the first two-input element And 4.3, allows the receipt of clock pulses from the second clock input 41 of the shaper of time intervals 4 to the counting input From the counter 4.7. Thus, in the shaper of time intervals 4, a countdown of the waiting time of the next BDI is initiated.

The end of the analysis of the received BDI and the transition to waiting for the next BDI for a given time determined by the maximum search time code is carried out by setting the value of the logical unit at the enable input 014 of the device, which leads to the unconditional setting of the value of logical zero at the signal output 59 of the search strategy register 5. For correct operation of the device setting value of logical one to enable input unit 014 should be carried out with a time delay ΔT relative to the instant of time T _3, GER fissioning latency parallel switching elements trehvhodovyh NOR ₁ 5.3 -5.3 _N and N-OR input elements 5.4 Search Strategy register 5, the maximum delay time of the register write address generation unit 6.4 mask 6 transitions, time delay tripping JK-flip-flop 4.2, and the delay time of writing to the counter 4.7 of the shaper time intervals 4:

ΔT = ΔT _5.3 + ΔT _5.4 + max [ΔT _6.4 , ΔT _4.2 , ΔT _4.7 ],

where: ΔT _5.3 is the delay time of the parallel operation of the three-input elements OR NOT 5.3 ₁ -5.3 _N register search strategy 5; ΔT _5.4 is the delay time of the N-input element OR 5.4 register search strategy 5; ΔT _6.4 is the delay time of writing to the register 6.4 of the block forming the address of the transition mask 6; ΔT _4.2 is the delay time of the JK trigger 4.2 of the shaper time intervals 4; ΔT _4.7 - the delay time of recording in the counter 4.7 of the shaper time intervals 4.

Simultaneously with setting the value of the logical unit at the enable input 014 of the device, the setting of the value of the logical unit at the input “Crystal Choice” 012 of the device is carried out.

If before the expiration of the waiting time for the next BDI, but within the maximum search time set through the main search controller 9, the next BDI arrives, the type of which corresponds to the type expected according to the search script, then the value of the logical unit at the signal output 59 of the search strategy register 5 will lead to re-initialization of the counter 4.7 of the shaper of time intervals 4 (re-recording in the counter of the code for the waiting time of the next BDI). In this case, the logical value at the output 4.2-3 of the JK-trigger 4.2 of the shaper of time intervals 4 will not change (since its second information input 4.2-2 (input K) is set to a logical zero), and clock pulses will continue to be supplied to the counting input C counter 4.7. Thus, the countdown of the waiting time for the next BDI within the specified maximum search time will start from the beginning.

If the next BDI corresponding to the search script does not arrive before the timeout expires, but within the specified maximum search time, then overflow counter 4.7 of the shaper of time intervals 4. At the same time, at the output P of the overflow of counter 4.7 of the shaper of time intervals 4, the value of the logical unit is set, which will go to the second input 4.5-2 of the second two-input element And 4.5 and through the first two-input element OR 4.1 to the second information input 4.2-2 (input K) of the JK trigger 4.2. The values of the logical unit at the output of the overflow P of the counter 4.7 and at the signal input 45 of the shaper time intervals 4 can be set at arbitrary points in time, but within the specified maximum search time. In this regard, at the information inputs 4.2-1 (input J) and 4.2-2 (input K) of the JK-trigger 4.2 of the shaper of time intervals 4, the following combinations of logical values may appear:

at the first information input 4.2-1 (input J) of the JK-trigger 4.2, a logic zero value is set, and at its second information input 4.2-2 (input K), the value of a logical unit is set;

on the first 4.2-1 (input J) and second 4.2-2 (input K) information inputs of the JK-trigger 4.2, the values of the logical unit are set.

In the first case, at the output 4.2-3 of the JK-trigger 4.2 of the time interval shaper 4, a logic zero value is set, which will go to the second input 4.3-2 of the first two-input element And 4.3 and to the input 4.4-1 of the inverter 4.4. The value of logical zero at the second input 4.3-2 of the first two-input element And 4.3 will stop the receipt of clock pulses from the second clock input 41 of the shaper of time intervals 4 to the counting input C of the counter 4.7 (see Fig. 6). The value of logical zero at the input 4.4-1 of the inverter 4.4 will lead to the setting of the value of the logical unit at the first input 4.5-1 of the second two-input element AND 4.5, which, if there is a value of the logical unit at its second input 4.5-2, will lead to the setting of the value of the logical unit at the second input 4.6-2 of the second two-input element OR 4.6 and the output "Reset" 44 of the shaper time intervals 4. The value of the logical unit at the second input 4.6-2 of the second two-input element OR 4.6 will reset the counter 4.7, and the value of the logical unit at the output de “Reset” 44 will reset the register 6.4 of the block for generating the address of the transition mask 6. Resetting the counter 4.7 of the shaper of time intervals 4 will cause the overflow P to be set to a logic zero value at its output, which will go to the second information input 4.2-2 (input K) JK -trigger 4.2 and to the second input 4.5-2 of the second two-input element AND 4.5. In this case, the output "Reset" 44 of the shaper time intervals 4 is set to a logical value of zero. Resetting the register 6.4 of the block for generating the address of the transition mask 6 (see Fig. 8) will result in the installation of address inputs 5.2-2 (inputs A ₁ -A _K ) of random access memory 5.2 of the search strategy register 5 (see Fig. 7) of zero address . Thus, the search for the next BDI determined by the current (within the specified maximum search time) transition mask is interrupted and the device goes to wait for the BDI, the types of which are determined by the mask of the start of the search script (initial BDI).

In the second case, the logical value at the output 4.2-3 of the JK-trigger 4.2 of the shaper time slots 4 will not change. In this case, clock pulses will continue to be supplied to the counting input C of the counter 4.7, and the output of 4.5-3 of the second two-input element And 4.5 will remain the value of logical zero (despite the value of the logical unit at its second input 4.5-2). The value of the logical unit at the signal input 45 of the shaper time intervals 4 (see Fig. 6) will lead to the recording of the waiting code of the next BDI installed on the M-bit input "Code timeout" 06 of the device in the counter 4.7. At the same time, at the output of the overflow P of counter 4.7, a logic zero value will be set, which will go through the first two-input element OR 4.1 to the second information input 4.2-2 (input K) of the JK trigger 4.2 and to the second input 4.5-2 of the second two-input element AND 4.5. Thus, the reset of register 6.4 of the block for generating the address of the transition mask 6 (see Fig. 8) will not occur and the address corresponding to the address 5 will be set at the address inputs 5.2-2 (inputs A ₁ - A _K ) of the random access memory 5.2 of the search strategy register 5 another transition mask. In this regard, the operation of the device to search for next (according to the search script) BDI, within the specified maximum search time, will continue.

инверсном выходе 7.1-2_n (выходе $${\overline{X}}_n$$

из $${\overline{X}}_1-{\overline{X}}_N$$

выходов) дешифратора 7.1, номер n которого соответствует коду типа БДИ, установится значение логического нуля, а на всех остальных выходах дешифратора - значение логической единицы. Логические значения с выходов 7.1-2₁-7.1-2_N (выходов $${\overline{X}}_1-{\overline{X}}_N$$

) дешифратора 7.1 блока индикации 7 поступают на первые входы 7.2₁-1-7.2_N-1 соответствующих двухвходовых элементов ИЛИ 7.2₁-7.2_N, где происходит их сравнение со значениями маски окончания сценария поиска, установленными на N-разрядном входе «Правило завершения поиска» 07 устройства. При совпадении логических значений на входах двухвходового элемента ИЛИ, номер которого соответствует коду типа БДИ, на его выходе установится значение логического нуля, которое через N-входовый элемент И 7.3 поступит на выход «Результат поиска» 015 устройства, что соответствует обнаружению во входящем потоке БДИ за заданное максимальное время поиска последовательности БДИ, соответствующей сценарию поиска.Within the specified maximum search time, upon receipt of a BDI, the type of which corresponds to one of the BDI types specified in the mask for the end of the search script (end BDI), a logical zero value is generated at the output “Search Result” 015 of the device. The formation of the value of logical zero at the output "Search Result" 015 of the device is as follows (see Fig. 9). From the bits of the K-bit input "Event Code" 71 of the display unit 7, a code of the BDI type is supplied to the corresponding inputs 7.1-1 ₁ -7.1-1 _K (inputs Y ₁ -Y _K ) of the decoder 7.1. Moreover, on the nth $$\left(n=\overline{\mathrm{one,}N}\right)$$

inverse output 7.1-2 _n (output $${\overline{X}}_n$$

of $${\overline{X}}_{\mathrm{one}}-{\overline{X}}_N$$

outputs) of the descrambler 7.1, the number n of which corresponds to the code of the BDI type, the value of logical zero is set, and at all other outputs of the decoder - the value of the logical unit. Logical values from outputs 7.1-2 ₁ -7.1-2 _N (outputs $${\overline{X}}_{\mathrm{one}}-{\overline{X}}_N$$

) of decoder 7.1 of indication block 7 are supplied to the first inputs 7.2 ₁ -1-7.2 _N -1 of the corresponding two-input elements OR 7.2 ₁ -7.2 _N , where they are compared with the values of the mask of the end of the search script set on the N-bit input "Search termination rule »07 devices. If the logical values coincide at the inputs of the two-input OR element, the number of which corresponds to the code of the BDI type, the output will be set to a logic zero, which through the N-input element And 7.3 will go to the output “Search Result” 015 of the device, which corresponds to the detection in the input stream of the BDI for a given maximum search time for the BDI sequence corresponding to the search script.

Thus, the proposed information retrieval device increases the likelihood of timely information retrieval in conditions inherent in the real process of functioning of modern data networks with packet switching, modern information and reference (search) systems - in the conditions of continuous dynamics of changing states of requests for information search and taking into account influencing factors. The probability of a timely search for information increases due to the identical search time controllers 8 ₁ -8 _N implemented in N≥2, the main search time controller 9 and the clock pulse generator 10, respectively, of decryption, dynamic correction and synchronization of decryption processes, control and correction of values (boundaries ) the maximum search time for each specific scenario (search query). This result is due to the receipt (for a given maximum search time) at the outputs of the “Comparison Result” 83 ₁ -83 _N search time selection controllers 8 ₁ -8 _{N of the} sequence of signals from the results of search queries - a sequence of logical values corresponding to the results of the identification of BDI, formed taking into account how dynamics of control actions or external factors, as well as the current requirements of subscribers of the information-reference (search) system to the timeliness of information search and.

An analysis of the operating principle of the claimed device shows the evidence of the fact that, along with the saved and described in the prototype capabilities for parallel identification of incoming BDI, monitoring the order of BDI, monitoring the intervals of BDI and signaling the detection of a BDI sequence specified by the search script, the device is able to timely perform search queries under the conditions inherent in the real process of functioning of modern data networks with packet switching, modern and information and reference (search) systems - when in the dynamics of work, for example, of a managed search system, not only the properties of the system and the environment objectively change in time, but also the requirements for the timely search of information.

This device provides an increase in the likelihood of timely search (identification) of information in conditions inherent in the real process of functioning of a data transmission network and information and inquiry (search) system - in the conditions of continuous dynamics of changing states of search queries and taking into account influencing factors, which significantly expands the scope of application of the device , expands the functionality of search queuing subsystems in packet-switched data networks, in modern information reference systems where the claimed information retrieval device will be used.

INFORMATION SOURCES

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3. Blakhnov L. L., Ignatenkov V. G., Kuznetsov V. E. Infocommunication networks: architecture, technology, standardization / Ed. A.A. Sakhnina. - M .: Radio and communications, 2004 .-- 208 p.

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Claims (4)

1. An information retrieval device containing N≥2 mask storage units, N selection blocks, a frequency divider, a time interval shaper, a search strategy register, a transition mask address generating unit and an indication unit, the clock input of the frequency divider being the first clock input of the device, and the output of the frequency divider is connected to the clock input of the time slot generator, and K-bit, where K = (log ₂ N) +1, the “Event code” output of the transition mask address generation unit is connected to the K-bit inputs of the “Event code” reg Istra of the search strategy and the indication block, respectively, the recording permission inputs of N mask storage units are combined and are the device recording permission input, L-bit information inputs, where L≥2, N selection blocks are combined and are the L-bit information input of the device, the first L- the Mask 1 and Mask 2 bit inputs of N mask storage units are the first L-bit device inputs of Mask 1 and Mask 2, respectively, the second Mask 1 and Mask 2 L-bit outputs of N blocks storage masks connected to a second L-discharge to the input inputs “Mask 1” and “Mask 2” of the corresponding selection blocks, the input “Initial reset” of the time interval generator is connected to the input “Initial reset” of the transition mask address generation unit and is the input “Initial reset” of the device, while the M-bit input The “time-out code” of the time slot former, where M≥2 is the bit length of the time-out code, is the M-bit input of the “Time-out code” of the device, and the output of the time-interval shaper is connected to the “Reset” input of the ma ski transitions, the signal output of the search strategy register is connected to the signal inputs of the time slot generator and the transition mask address generating unit, the K-bit address input, the control input, the N-bit information input and the search register enable input are the K-bit address input, a control input, an N-bit information input and a device enable input, the “Choice of crystal” and “Read / write” inputs of the search strategy register are respectively the “Choice” inputs crystal ”and“ Read / Write ”of the device, the N-bit input“ Search completion rule ”and the“ Search result ”output of the display unit are respectively the N-bit input“ Search completion rule ”and the“ Search result ”output of the device, characterized in that additionally introduced N search time selector controllers designed for decryption, additional comparison and control of the S-bit code, where S≥2 is the bit depth of the search time correction code, causing a new value for the maximum search time d I have each search query, the main controller of the search time, designed to dynamically correct the values of the maximum search time for each search query, and a clock generator, designed to generate a synchronizing sequence of pulses, and the output is “Compare result” of the nth selection block, where n = 1, 2, ..., N, is connected to the input “Comparison Result” of the nth selection search time controller, the output “Comparison Result” of which is connected to the nth input “Comparison Result” of register p search tags and with the nth input “Comparison result” of the transition mask address generation unit, the output of the clock generator is connected to the clock input of the nth selection block, the “Zero” input is the nth “Zero” input of the device, and S- the bit correction input of the nth selection block is combined with the S-bit test input of the nth selection search time controller and is connected to the nth S-bit output of the main search time controller, N S-bit inputs of which are corresponding to N S-bit input “Correction of the maximum search time” device. 2. The device according to claim 1, characterized in that the selector search time controller consists of a decoder of the corrected code of the maximum search time and a comparison-correction register of the maximum search time, while the S-bit input of the decoder of the corrected code of the maximum search time is an S-bit check the input of the search time selection controller, the test output of the corrected code decoder of the maximum search time is connected to the test input of the comparison-correction register ma maximum search time, the signal input and output of which are respectively the signal input and output of the “Result of comparison” of the selection controller of the search time. 3. The device according to claim 1, characterized in that the main controller of the search time consists of a recording element of the search time and the storage element of a new value of the search time, while the N S-bit inputs of the recording element of the search time are the corresponding N S-bit inputs of the main controller search time, wherein N S-bit outputs of the recording element of the search time are connected to the corresponding N S-bit inputs of the storage element of the new value of the search time, N S-bit outputs of which are corresponding N S-bit output main controller search time. 4. The device according to p. 1, characterized in that the selection block consists of the first and second groups of two-input elements AND L elements in each group, a comparator, inverter, counter, three-input element And and a correction register, while the inverse output of the counter is connected to the first input of the three-input element And is connected to the inverse output of the inverter and is the output "Compare result" of the selection block, the third input of the three-input element And is the clock input of the selection block, and the output of the three-input element And is connected to the account to the counter input, the inverse counter resolution enable input is connected to the comparator equality output and connected to the second input of the three-input element And and to the inverter input, while the S-bit input of the correction register is the S-bit correction input of the selection block, and S outputs of the correction register are connected to the corresponding S information inputs of the counter, and the counter reset input is the “Zeroing” input of the selection block, with the lth, where l = 1, 2, ..., L, the input of the first group of information inputs of the comparator dinen with the corresponding output of the l-th two-input element And the first group of two-input elements And, and the l-th input of the second group of information inputs of the comparator is connected to the output of the l-th two-input element And the second group of two-input elements And, the first input of the l-th two-input element And the first group of two-input elements And is the l-th bit of the L-bit information input of the selection block, the second input of the l-th two-input element And the first group of two-input elements And is connected to the first input of the l-th two-input element And And the second group of two-input elements And is the l-th bit of the second L-bit input "Mask 1" of the selection block, and the second input of the l-th two-input element And the second group of two-input elements And is the l-th bit of the second L-bit input " Mask 2 "of the selection block.

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