SU1441399A1 - Device for distributing tasks among processors - Google Patents

Abstract

The invention relates to automation and computing, and (specifically, to priority devices for assigning tasks to processors, and is intended for use in multiprocessor and multi-machine computing and control systems. The purpose of the invention is to expand the field of application of the device by restarting incomplete tasks. tasks to processors contains a group of counters; two blocks of memory, five groups of elements AND, two groups of elements OR, eighteen elements AND nineteen OR elements, a WN-NE element, a comparison circuit, four flip-flops, five registers, six counters, two multiplexers, three encoders, five decoders, five delay elements, 2-2-2IL-2IL-NOT elements, three formers impulses, two groups of elements OR-NE. The device provides tracking for executing tasks and restarts incomplete tasks on the same processor, and when re-hanging programs - on one of the free processors with disconnection of the failed processor. 8 il. a (L

Description

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with

with

The invention relates to automation and computing, in particular, to priority devices for assigning tasks to processors, and is intended for use in multiprocessor and multi-machine computing and control systems.

The purpose of the invention is to expand the scope by restarting outstanding tasks,

FIG. 1-3 shows a functional diagram of the device; 4-8 are timing diagrams describing individual stages of the device operation.

The device contains the first group of elements OR 1, the group of counters 2, the first 3 and repeat the 4 groups of elements OR NOT, the second group of elements AND 5, the first memory block 6, the first group

if

elements AND 7, the first - the fourth elements AND 8-11, the first element OR 12, the group of code inputs 13 of the device, the group of address inputs 14 of the device, the input 15 of the start of the device, the input 16 of the initial installation of the device, the element 2-2-2И-2ИЛИ- NOT 17, the address output 18 of the device, the first 19 and second 20 signal outputs of the device, the second memory block 21, the fifth - the eighteenth elements AND 23-35, the second - the seventeenth elements OR 36-51, the clock input 52 of the device, the element OR-NOT 53, the first - the third shaper 54-56 pulses, the first - the third encoder 57-59, the first 60 and the second 61 th mu liplexers, the first - the fourth triggers 62-65, the third and seventh groups of elements AND 66-70 ,, the second group of elements OR 71 comparison circuit 72, the first - the fifth registers 73-77, the first - the sixth counters 78 - 83, the first - the fifth decoders 84-88, a group of synchronous inputs 89 devices, a signal group BkoAOB 90 devices, information input 91 devices first to a sixth group of signal outputs 92-97 devices, a delay element 98.

The device works as follows.

Before starting operation by applying a pulse, all elements of the device memory are reset to the input 16 of the device. The cleaning circuits of the memory block 21 are not shown in FIGS. 1-3. In doing so, registers 73-77, counters 78-83, and counters of group 2 are zeroed out. Triggers 62-64 set

with

g

five

0

five . O s d 45

P

five

c is set to the zero state, and the trigger 65 is set to one state. The zero signal at the forward output of the trigger 62 prohibits the passage of sync pulses from the inputs 89 of the device to the device. The zero signal at the output of the element OR 29. Prohibits the passage of signals from an external timer to the device. Signal outputs 92 and 93, as well as 95-97, have zero signals. On the signal outputs 19 and 20, as well as on the group of signal outputs 94, single signals are installed. At the address output 18 of the device zero signal.

Memory block 6 contains information about the topology of the graph describing a set of information related tasks. At the address corresponding to the number (i 1, n-1) of a certain vertex of the graph, in block 6 of the memory, an n-digit number is entered that has a unit in the corresponding qM bit if the arc leading to q the top of the graph. At the zero address corresponding to the final vertex of the graph, zero is recorded in memory block 6.

Next, counters 2 from the like (groups of inputs 13 are entered in the forward; code, the degree of entry of the corresponding graph vertices, representing the number of arcs entering the corresponding graph vertices.

The correspondence of the vertex of the gryphus and the counter 2 is determined by the weight of the vertex, which is the maximum P5 from this vertex to the final vertex of the graph describing the set of information related tasks and having task arcs as weights. The first counter 2 (the topmost one in FIG. 1) should correspond to the top of the graph with the greatest weight, the second counter 2 to the second: by weight, the top of the graph, etc. The last counter 2 will correspond to the final vertex of the graph having zero weight. Such a correspondence between vertices and counters 2 minimizes the time needed to solve the entire package of information-related tasks, since from a certain set of requests for solving tasks (for solving which there is all the necessary information), the task with the greatest weight is solved first.

Further, in the counter .80 from the input 91 of the device, the code is entered in the forward code

the 79 ti counter records in it the number of the selected hc processor (used as the cell address of the second memory block 21).

According to the sync pulse, at the output of element P1 23 a pulse signal is generated, which is fed to the inputs of elements AND 68 of the fifth group and calling the number of tasks in the package of information related tasks. At the completion of each task, a unit is subtracted from counter 80 and the equalization signal at the output of the counter indicates that the package of information related tasks has been completed.

The operation of the device begins with the arrival of the start signal at the input 15 arranges at the signal output 96.

properties. When this trigger 62 is transferred to the group corresponding to the selected

in one state and by the signal you - the processor, the signal

level from the direct output of the task.

Sharks the arrival on the device of the series Zero signals at the control pulses. The device has 15 times multiplexers 60 and 61 allow four modes of operation: the transfer mode to the output of signals from the input of the task ready for the assignment; to the information input, the reception mode of the code of the completed task-second memory block 21 is ionized; the polling mode of the readiness of the task-measure of the task being issued, and on its litters; The processing mode of the situation, the 2-address input, is given the number of the selected task of the processor, which serves as the first mode of operation of the address of the cell. Single builds. Since the outputs of the element from the output of the element OR A6 are post-OR-NOT 3 groups, corresponding to the inputs of the element 2-2-2 and 2 or the meters 2, in which the zero BNE 17 is entered and creates conditions for the implementation of the counter 79 ti, puts in it the number of the selected section processor (used as the cell address of the second memory block 21).

According to the sync pulse, at the output of element P1 23 a pulse signal is generated, which is fed to the inputs of elements AND 68 of the fifth group and calls

code of the degree of entry, single request signals are set, then the output of the OR 12 element will be a single signal

The input to the first inputs is 2I-2IL-NOT 17, and the 22 and 23 elements are skidded. On the second inputs of the executed task in the cell, the elements 22 and 23 dips come in the same signal as the selected processor. output element of RSHI

The sync pulse L, J arrives at the input of the element OR 36 and triggers reset 64. A single

.50, which indicates the presence of free processors. A single signal from the output of the element OR NOT allows the operation of the decoder 87, which generates a signal at one of its outputs corresponding to the priority processor from among the free. At the outputs of the decoder 88 zero signal levels.

A sync pulse (5 at the output of the element And 22 produces a pulse signal, which is fed to the inputs

The sync pulse L, J arrives at the input of the element OR 36 and triggers reset 64. A single

The signal at the inverse output of the trigger 64 initiates a pulse signal at the output of the pulse generator 56, which is fed to the inputs of the AND 66 elements and is output from the zero state

40, the counter 2, corresponding to the task being started, is fed to the inputs of the elements And 70 and causes the signal at the signal output 97 of the group corresponding to the selected processor to issue

Elements And 67 groups and causes a 45 Start, initiating the delivery of the signal of the given task to the selected processor. The same initialization signal is sent to the initial state. It arrives at the corresponding input by the output address, the device 18 when the register is set to 74, and the number of the task ready for the process is eliminated. At the same time, the same 50 P & from among the free,

At the next cycle, the next ready task is issued, and so on. Having issued all the tasks that are ready for execution, the device switches to the ready polling mode.

processors. This mode is characterized by the fact that the sync pulses with the help of register 76 produce an increase in the states of the signal inputs 90

the signal arrives at the synchronization of the third flip-flop 64 and translates it into a single state (issue mode number ready for the task), enters the counting input of the first counter 78 and increments its contents (another task in the System is in the execution state) and also enters sync on the second

laziness record operation,

According to the sync pulse C, which arrives at one of the inputs of element 2-22 and 2, or non-17, the number of the set task is entered into the cell corresponding to the selected processor.

The sync pulse L, J arrives at the input of the element OR 36 and triggers reset 64. A single

the signal at the inverse output of the trigger 64 initiates a pulsed signal at the output of the pulse driver 56, which is fed to the inputs of the elements And 66 and transits from the zero state

the counter 2 corresponding to the task being started enters the inputs of the elements 70 and causes the signal at the signal output 97 of the group corresponding to the selected processor to be output

514413996

devices to which potential single signals from the selected processor outputs come in the form of a command are selected by the selected processor, the task completion code. With the arrival of the task, In response to this first signal of the completion of the command, the selected processor exposes the device to receive mode at the address inputs 14 of the device of the completed task code of the completed task.

In the reception mode of the code completed On the ZT clock pulse, the incoming job of the device performs the following at the inputs of the And 7 elements, the actions that take place. The sync pulse Td vu vchachach on the address inputs of block 6 parigister 76 remembers the signal to read the code of the solved problem, as a result of the task from the processor, which forms a pulse signal that generates a single signal to the outputs on those the outputs of the memory block 6, the element OR 44, the incoming one that corresponds to the tasks, the non-cutting element AND 30 to the informational 15, an informationally connected trigger input 63. The priority cipher is a solved task, and a 58 is generated. on e It’s one of the codes of the degree of the processor from among the signals that signaled the progress of these tasks (in this case, requests for solving some of the synchro t pulse flip-flop 63 20 of these tasks can be solved if their zero-degree codes turn out to be 1). call), (the mode of reception of the code of the completed task- According to the sync pulse with the decoder ni). A single signal from the direct one generates a second signal to the corresponding trigger 63 through the element OR 46 of the appropriate output 92 of the group, which is fed to the inputs of element 2-2-2I-25 by the selected processor and is interrupted by the signal 2ILI NOT 17 and creates conditions for the completion of the task and the completion code of the operation Record, the commented task. With inputs 90 and 14 it sets to the second inputs of the elements AND 7 and solids.

creates conditions for the passage of the code. By the sync pulse, a complete task is performed from the address inputs of reset flip-flop 63 (exit from the device 14 mode to the memory block 6, reception of the completed task code) and goes to the control inputs of the multi-update in register 76 information of typelexers 60 and 61 and permits pro processors that have completed execution of signals from the jobs to their outputs. The next mode of operation, Dow X1, enters the input of element 5 of the device, is determined by the presence of GO-28 and creates conditions for the tasks to be carried out and the presence of a sync pulse. At the same time, the processors that completed the execution of the same signal initiate the execution of tasks, and the priority belongs to the shaper 54 pulses of the pulse-to the mode of execution of tasks for the execution of the signal, which goes to Fig. 4 shows the time dia -. The subtracting input of the counter 80 and the pro- grammes illustrating the reception process leads to a mark on the completion of its one code (nl) -ro completed task, is received through the OR element from the f-ro processor and the start of the nth 48 to the subtracting input of the counter 78 and the tribute on the 5th processor will take into account the number of jobs, g the device will continue until being executed in the system, until the last is sent through the element OR 43 to the task, corresponding to the final reset input of the counter 82 and completes the top of the graph after its signal on the control of the duration of the execution of the output of the counter set 80, as well as the signal through the element with the zero signal, which passes OR 47 enters the control input through the element AND 32 on the information decoder 84, Last at the output, trigger input 62, and also enters the corresponding processor, the signal output 19 of the device and generates a pulse signal, which indicates the end of the solution is fed to the corresponding input gig packet of tasks. The next clock reset of the register 74 and the pulse G, arrives at the synchronous input, exhausts the indication of the release of the trigger 62 and converts it to the zero processor, and also enters the correlation (the stop state of the device 92 signaling groups). Zero signal from the direct output.

7id 13998

and trigger 62 enters the second, the zero-cell address, the inputs of the elements 8-11 and prohibits the corresponding zero processor), the arrival of the sync and myles on the device goes through the element OR 40 to the device. input reset register 76 and clears

Consider the mode of searching for a hung one (conditions are removed for the transition of the task to which the device of the transition device enters the code reception mode if the duration of the time reference is violated before the completion of the entire interval set aside for restarting the task) the longest task from u enters the counting input of the counter 83 of the packet and the controlled counter 82. and initiates the registration of the quantity

With the presence of tasks hanging in the run-and-run process on the processor, the off-topic counter 78 has a non-zero sign that has completed the task. Zeroing, as a result, a signal is generated that arrives at the control - a single signal at the output of the 15 input element of the multiplexer 61 , permit- ting 49, permitting the passage also of the passage of signals of composite signals to its output to the counting input of the account from the input X2. Thus, at the address 82, the violation of the temporary intermittent input of the memory block 21 enters the shaft (no reset signal on the contents of the counter 78, which forwards the next task) leads 20 mi sequential addresses of the cells to the formation of the zero signal of the transient memory block 21 by nose sync at the signal output of the counter. "

82, which arrives at the information on the following sync pulse trigger input 65. The next so-S register 73 carries out the overwrite pulse T, arrives at synchronization 25 remembering the contents of the cells of the block 21 trigger input 65 and translates it into memory. In the memory cell, there is a corresponding zero state (processing mode n) to the processor that did not complete the task hangup situation). Zero value, the number of this call will be recorded from the direct output of the trigger 65 dan, and in the remaining cells - zero will be input to the input of the And 26 element and the secret code. When a cell is detected, it solves the passage of clock pulses with a nonzero content at the output of the circuit, a synchronous input of the trigger 64, after a 72 comparison, a single drop is formed at the input of the AND 24 element and the suppression signal, which is sent through the synchro pulses through the pulse SH 45 at the input control input for multi-processor readiness. Unit 5 of type 60 and permits the passage of a signal from the inverse output of a trigger to its output signals from input 65 enters the input of element And 25 and, XI ,, enters the input of element And 29 and allows the formation of a counting series to create conditions for the passage of syn counter 79, enters the input of an impulse, enters the input of an AND 27 and allows the register to work for element 2-2-2И-2ИЛИ-НЕ 17 and creates a 73, enters the input of the element AND conditions for implementation: 29 and enables the output of signals with an impulse from the Record operation. Thus, the progress of the comparison circuit 72, proceeds in a manner, a zero code is fed to the information input of the block to the input of the element 2-2-2IL-2IL-NOT 17 and 21 of the memory. creates a mode Write, read, for According to the sync pulse € j output of the memory block 21. The same unit AND 29 forms a pulse signal, the signal initiates the issuance of a driver that enters through the element 55 of a pulse of a pulsed signal, OR 51 to the synchronous input of the trigger 65 and which arrives through the element OR sets it to one state - 43 to the reset input counter 82 and clearing gQ (exiting the processing mode it is in a situation (at the transfer output of the hang-up), comes through a single signal), enters the indoor signal with a single signal from the output through SHSh 48 to the subtracting counter 83 element and 34 n synchronizing the input of counter 78 and decrementing its input to register 77 and recording the contents into it (if more than one measurement of the found processor is hung, not closure, then signals from input 52 of the task that continues the task go to the device ) j post-. to the control input of the decoder 85 passes through the OR element 42 to the input and generates at its output a reset signal of the counter 79 and clears it (restarting the detected hung 2 meter group), using the same sync pulse of the memory block 21 corresponding to the hung processor The zero signal from the output of the OR-NOT 52 element prohibits the operation of the decoder 87 and the counter 79, as a result of which the processor on which the task has hung up is selected for the execution of the task. A single signal from the direct output of flip-flop 65 permits polling the lines, and the system maintains at least the required response. With a larger number of faulty processors at the output of the transfer of the counter 81, a zero signal is generated, which through the element 32 arrives

processors. Resetting the group 2 counter, corresponding to the information input of the trigger 62, to your task, leads to the appearance as well as to the signal output 20 of the stray signal at the output of the OR 12 element, resulting in a prerequisite for switching the device to the number is ready- 20 and puts it in the zero state to perform the task. Start-up (device stop state). Nurovstva and indicates the accident system. Another sync pulse arrives at trigger sync 62

Dani is produced as described.

In the event that the restart of the task to the previously hung processor (the number of restarts determined by the counting depth of the counter 83) did not lead to a normal completion of the task, the following sequence of actions is performed. Similarly to the described 30, one of the free processors. The unit searches for the hung task and the processor, the corresponding memory cell of the block 21 is zeroed, and the zero outflow signal is removed from the hangup handling mode (translation of the trigger 65 to one). from the output of the counter 83 prohibits the passage

The signal from the output of the element OR-HE 53 permits the passage of a single signal from the output of the element 22 And (generated by the sync pulse from

)

35

through element 35 to the synchronous input of the counter 79, and also enables the operation of the decoder 87. Thus, the task is restarted on the priority processor from among the free, pulse signal from the output of element 40. The task number is issued AND 29 to the synchronous input of the register 77 and similarly described, decides its passage through the element. In FIG. 5 and 6 show temporary AND 33. A pulsed signal from the output of the ele-i diagrams describing the perement process. And 33 is fed to the counting input of starting the n-th task of the stuck on the second counter 81, recording the number of 45 P. processor on the kth clock.

FIG. 7 and 8 are temporary

unworkable system processors, and increments it. The same signal is fed to the control input of the decoder 86 and forms on

charts describing the shutdown of the second processor and the restart of the nth job on the first processor. Decision

its output (corresponding to the failed gg about the failure of the second processor processor) is a pulse signal that arrives at the group signal output 93 of the same name and shuts down the processor, and also enters the regigg setting of the register 75 and makes a mark about excluding processors containing a processor group from the system configuration. Inverted Echo Signals

Claims (1)

is taken at the kth bar. Invention Formula counters, memory block, a group of elements OR, two groups of elements SH- NOT, the chip of the element AND, the element OR, register bits 75 using Elenie to disabled processors, and also enter the group of outputs 94 devices and initiate in the unitary code of the number of faulty processors. The counting depth of the counter 81 is determined by the maximum number of faulty processors at which the system performance is not less than the required one. With a larger number of faulty processors at the output of the transfer of the counter 81, a zero signal is generated, which through the element 32 arrives to the information input of the trigger 62, as well as to the signal output 20, the device sets it to the zero state (the device stop state). Nun informational input of the trigger 62, as well as to the signal output 20, is set and translates it to the zero state (device stop state). Nurovstva and indicates the accident system. Another sync pulse arrives at trigger sync 62 the left signal from the direct output of the flip-flop 62 goes to the second inputs of the element; Ents And 8-11 and prohibits the passage of 25 on the device sync pulses o - Cj. If the system performance does not become lower than the required one after shutting down the failed processor, the hung task on the The signal from the output of the element OR-HE 53 permits the passage of a single signal from the output of the element 22 And (generated by the sync pulse from ) charts describing the shutdown of the second processor and the restart of the nth job on the first processor. Decision malfunction of the second processor A device for assigning tasks to processors containing a group of is taken at the kth bar. Invention Formula malfunction of the second processor A device for assigning tasks to processors containing a group counters, memory block, group of faults of the second processor A device for distributing tasks to processors, containing cops OR, two groups of elements SHSHNE, the chip of the element AND, the element OR, each input of the group of address inputs of the device is connected to the first input of the element of the same name AND the first group, the output of which is connected to the address input of the memory unit of the same name, the group of code inputs of the device is connected to information inputs and synchronous inputs of the group of the same name, the outputs of which are connected to the inputs of the same name OR - NOT the first group, the output of the M-th element OR-NOT the first group (, N, N - the number of code inputs of the device) is connected to the first input of the M-th element AND of the second group and to the (M-1) -th input of the AND element LI, the output of each element OR is NOT the first group from the first to the K-th (where K is the whole part of the number 0.5p) is connected with the corresponding input of the same name 2o dinene with the unit input of the first 25 thirty 35 And the next element OR is NOT the second group to K-th inclusive, the output of each element OR is NOT the first group from (K + 1) -th to (n-1) -th is connected to the corresponding input of the same name and  the subsequent elements OR of the second group up to (n-1) -th, inclusively, the output of each element of the OR group of the second group is connected to the second input of the element of the same name AND the second group, characterized in that, with the aim of expanding the area by restarting outstanding tasks and restarting them to one of the free processors of the system, it additionally contains the second block of memory, the group of elements AND from the first to the fifth, the second group of elements OR, the elements AND from the fifth to the eighteenth, the elements OR from the second to the seventeenth, the element OR NOT scheme first to fourth triggers, first to fifth registers, first to sixth counters, first and second multiplexers, first to fifth encoders, first to fifth decoders, a delay element, 2-2-2I element 2IPI-NOT, pulse formers from the first to the third, with each output of the first memory block connected to the subtractive input of the counter of the same name of the group, the output of each element OR NOT of the first group from the first to K-and connected to the corresponding input (K + 1) - first and subsequent elements - 55  Comrade OR NOT of the second group to (n-l) -ro of the element inclusive, the output nepBoi o of the element of the IPI-NOT of the first group is connected to the first input of the first element trigger, the direct output of which is dinine with the second inputs of the first to fourth elements, the output of the first element AND is connected to the second to the home of the element K, with the first input from the second element AND, as well as the first inputs of the second and third elements OR, the output of the second element And is connected to the second input of the sixth ment And, with the first inputs of the eighth and ninth elements And, as well as with the synchronous inputs of the first and second tags, the output of the third element And with the first input of the tenth element And, with the first input of the element 2-2-2I-2ILI-NOT, as well as with the second inputs And the first switch of the fourth element is And is connected to the first inputs of the eleventh and 40 of the twelfth elements AND, to the second input of element 2-2-2И-2ИЛИ-НЕ, and also to the first input of the fourth element OR, the output of the fifth element AND is connected with the first inputs element 45 And the fourth group, with the first input of the thirteenth element And, as well as with the counting input of the first counter, in the course of the sixth element And connected to the first inputs of elements And the fifth group, the information input of the third trigger is connected to the bus unit unit, output first cartoon plexor onnym connected with the information input of the second memory unit, whose output is connected with the information input of the first register onnym, WMOs reset device is connected to the zero input of the first flip-flop, the first inputs of the first OR element gtrupp 50 Q 139912 Both the third group and the first input of the first encoder, the output of each i-ro element AND the second group (, nl) is connected to the first input of the (i + 1) -ro element AND of the third group, as well as with the (i + 1) -M input the first encoder, the output of the first encoder is the address output of the device and connected to the first information input of the first multiplexer, the second information input of which is connected to the logical zero bus of the device, each input of the group of synchronous inputs of the device connected to the first input of the first fourth elements And, respectively, the output of the first lementa OR connected to the first inputs of the fifth and sixth AND gates, the input device start soe15 five 0 five five trigger, the direct output of which is connected to the second inputs of elements I from first to fourth, the output of the first element AND is connected to the second input of element K, to the first input of the seventh element AND, as well as to the first inputs of the second and third elements OR, the output of the second element AND connected to the second input of the sixth element And, with the first inputs of the eighth and ninth elements And, as well as with the synchronous inputs of the first and second triggers, the output of the third element And connected to the first input of the tenth element And, to the first input of the element 2-2-2I- 2OR, NOT, and so e with the second inputs of the elements And the first grztpy, the output of the fourth element And is connected, with the first inputs of the eleventh and 0 of the twelfth elements And, with the second input of the element 2-2-2И-2ИЛИ-НЕ, as well as with the first input of the fourth element OR, the output n of that element And connected to the first inputs of elements 5 and the fourth group, to the first input of the thirteenth element And, as well as to the counting input of the first counter, the output of the sixth element And connected to the first inputs of elements And the fifth group, the information input of the third trigger is connected to the bus unit of the device, the output of the first multiplexer is connected to the information input of the second memory block, the output of which is connected to the information input of the first register, the device reset input is connected to the zero input of the first trigger, to the first inputs of the OR elements of the first group, 0 13 with reset inputs of the first, third and fourth counters, second and third registers, with a single input of the fourth trigger, as well as with the second inputs of the OR elements from the second to the fourth and the first inputs of the OR elements from the fifth to the ninth, the group of signal inputs of the device is connected to the information input of the fourth register, the output of which is connected to the input of the second encoder, the outputs of which are connected to the inputs of the tenth element SH, to the information inputs of the first decoder, as well as to the first information input second second multiplexer, the output of the second element OR is connected to the reset input of the first register, the output of which is connected to the information input of the second decoder, as well as to the first input of the comparison circuit, the second input of which is connected to the logical zero bus of the device, the output of the third element OR is connected to the zero input of the second the trigger, the direct output of which is connected to the second input of the eleventh AND element, to the third inputs of the AND elements of the first group, to the first inputs of the eleventh and twelfth OR elements, to the control input the house of the second multiplexer, as well as through the first pulse shaper with the first inputs of the thirteenth and fourteenth elements OR, with the second inputs of the seventh and ninth elements OR, with the subtractive input of the third counter, the output of the unequal comparison circuit is connected to the second input of the twelfth element AND, with the third input of the element 2-2-2И-2ИЛИ- NOT, with the second input of the eleventh element OR, the output of the fifth element ШШ is connected to the reset input of the fifth | register, the outputs of the first counter are connected to the inputs of the fifteenth element ШШ, / tact input devices connected to the first input of the fourteenth AND gate whose output is connected to the counting input of a fifth schet14 connected to the informational input of the fourth trigger, the direct output of which is connected to the second inputs of the seventh and ninth elements And, the inverse output of the fourth trigger connected to the second inputs of the eighth and tenth elements And, to the third input of the twelfth element And, with the fourth ten 20 , 15, p. 4139914 input element 2-2-2И-2ИЛИ-НЁ, as well as the second pulse shaper with the second inputs of the sixth, eighth and fourteenth elements OR, with the counting input of the sixth counter, with the third input of the ninth element OR, the outputs of the first decoder are the first group of signal exits. devices and connected to similar inputs of bit reset of the second register, inverse outputs of which are connected to the first inputs of elements of the same name AND the sixth group, outputs of the second decoder are connected to the second inputs of the elements of the same name OR of the first group, outputs of which are connected to reset inputs of the same name of the group, the output of the shielding element OR is connected to the reset input of the fourth register, the output of the seventh element OR is connected to the reset input of the sixth counter, the output of the eighth element OR is connected to the input om 25 reset the second counter, the second input of the second counter is connected to the information inputs of the fifth register and the third decoder, as well as the second information input of the second type 30 multiplexer, whose output is connected to the address input of the second block of memory, the outputs of the third decoder are The second group of signal outputs of the device and connected to the same-name & t inputs of the bit setting of the third register, the inverse outputs of which are the third group of signal outputs of the device and connected to the second inputs of one 40 The elements of the sixth group, the outputs of the elements of the sixth group are connected to the same inputs of the third encoder, the outputs of which are connected to the simultaneous information inputs of the fourth decoder and the sixteenth element shsh, as well as the information input of the second counter, the output of the seventh element I is connected to the synchronous input of the fourth, register; the output of the eighth element is connected to the counting input of the second counter; the output of the ninth element I is connected to the first input of the seventeenth element SH, the output of the tenth element This AND is connected to the synchronous input of the first register, the output of the eleventh element AND is connected to the second input of the thirteenth element OR, the output of the ninth element SH) is connected to the input of the switch 50 55, the fifth counter, the output of the tenth element OR is connected to the first input of the fifteenth element AND, the output of the eleventh element OR is connected to the control input of the first multiplexer, the direct output of the third trigger is connected to the second input of the twelve IDI element, the inverse output of the third trigger is connected with the second input of the fifteenth element And, as well as through the third pulse shaper with the second inputs of the elements And the third group, with the first inputs of the elements And the seventh group and through the delay element with the second input of the fifth el OR, the output of the twelfth element OR is connected to the fifth and sixth inputs of the element 2-2-2И-2Ш1И-НЕ, the first and second outputs of which are connected to the control inputs of the second memory block, the output of the thirteenth element SH) is connected to the gate input of the first decoder , the output of the capped element OR is connected to the subtractive input of the first counter, the output of the fifteenth element OR is connected to the second input of the fourteenth element AND, the output of the sixteenth element OR is connected to the third input of the fifth and sixth elements AND, the information The on-line input of the device is connected to the information and synchronous input of the third counter, the transfer output of which is the first signal output of the device and connected to the first input of the sixteenth element I, the transfer output of the fourth counter is the second signal output of the device and connected to the second input of the sixteenth element AND the transfer output of the sixth counter is connected to the first inputs of the seventeenth and eighteenth elements And, the output of the twelfth element And is connected to the gate input of the second decoder, 5 with the second th inputs of the seventeenth and eighteenth elements And, as well as the second input of the seventeenth element OR, the output of which is connected to the sync input of the fourth trigger, output 0 of the thirteenth element And is connected to the synchronous input of the second counter, the output of the fifteenth element And connected to the information input of the second trigger, output sixteenth element 5 is connected to the information input of the first trigger, the output of the seventeenth. element and connected to the gate input of the third decoder, as well as the counting input of the fourth counter , the output of the eighteenth element AND is connected to the sync-input of the fifth register, the outputs of which are connected to the same inputs of the element OR-NOT and the fifth depfractor, the output of element 5 OR-NOT is connected to the second input of the thirteenth element And, and. also with the gate input of the fourth deprafratora, the outputs of which are connected to the first inputs of the same OR elements of the second group, the outputs of the fifth decoder are connected to the second inputs of the same elements of the second group of the second group, the outputs of which are connected to the second inputs of the corresponding 5 elements And the fourth, fifth and the seventh groups, the groups of outputs of which are from the fourth to the sixth groups of the signal outputs of the device, respectively, the outputs of elements AND 0 of the seventh group are connected to the corresponding inputs setting a second register. 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