SU1644169A1 - Interruptions processing system controller - Google Patents

Description

one

(21) 4675634/24 v (22) 04/11/89 (46) 04/23/91. Vul. R 15 (72) N.N. Novikov, Yu.A.Romanenko, V.V.Kalyuk, B.B.Cymko and A.N. Grishutkin

(53) 681.325 (088.8)

(56) USSR Author's Certificate P 855665, cl. G 06 F 9/46, 1979.

USSR author's certificate R 1425673, cl. G 06 F 9/46, 1987.

(54) DEVICE FOR THE CONTROL OF THE INTERRUPTION TREATMENT SYSTEM

(57) The invention relates to computing technology and can be used, in particular, in computer interrupt systems. The aim of the invention is to increase the reliability of the device. The goal is achieved by controlling the operation of all elements of the device. The device contains elements AND 1, 5, 6, H, 10, 13, 14, 22, 23, elements OR 2, 4, 11, 15, 18, 24, register 3, triggers 7, 25, group of comparison circuits 8, Formers 12, 16 pulses, self-diagnosed encoder 17, a group of elements NOT 19, a decoder 20, a counter 21 pulses. These elements provide the formation of a signal interruption at the output 31, and in the event of a malfunction, the control outputs 29, 30, 32, 34, 35. 36 generate signals indicating the presence of a malfunction. 1 il.

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The invention relates to computing and can be used in computer interrupt systems.

The purpose of the invention is to increase the reliability of the device.

The drawing shows a structural diagram of the proposed device.

The device contains the first group of elements AND 1, the group of elements OR 2, the register 3, the fourth element ISH1 4, the fifth element AND 5, the sixth element AND 6, the first trigger 7, the group of comparison circuits 8, the first element AND 9, the second element AND 10 , the second element OR 11, the first pulse shaper 12, the third 13 and the fourth 14 elements AND, the first element OR 15,

second shaper 16 pulses, encoder 17, third element OR 18, group of elements NOT 19, decoder 20, counter 21 of pulses, second group of elements AND 22, third group of elements AND 23, - fifth element OR 24, second trigger 25, information inputs 26, the first 27 and second 28 setup inputs, the register status control output 29, the encoder status control output 30, the interrupt signal control output 31, the device installation control output 32, the information output 33, the device logic control output 34, the output state control 35 no decoder, output 36 to The state of the encoder and decoder.

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The device works as follows.

When the power is turned on, input 28 is given a signal that drives the device to its initial state. In the course of the operation of the device, it is brought to its initial state by applying a control signal to input 27.

Interrupt requests are received at inputs 26 of them are already written to register 3.

In the absence of signals at inputs 26 (in the initial state), the zero code is removed from the output of the encoder 17. It enters through a group of elements HE 19 at the input of the decoder 20. At its output, the output o is excited.

When a request for an interrupt arrives at the i-th input of the device (26,), it is recorded in the i-th bit of the register 3, i.e. The i-th bit of register 3 is transferred to the single state. In this case, the output signal from the 1st bit of register 3 is fed to the first input of the AND 14 element, opening it. A signal equivalent to a logical unit from the output of the AND 14 element, through the OR 15 element and the pulse shaper 16, is fed to the i-th input of the encoder 17. At its output, a binary code is generated, which is fed to the information output 33. Simultaneously through the OR 18 element the Interrupt signal is generated, which is fed to the code 31. The same information from the encoder 17 through the group of elements NOT 19 enters the inputs of the decoder 20. The i-th output is now excited at its output. This leads to the appearance of a signal equivalent to one at the output of the element And 13, as well as preparing the opening for the elements And 1, i.e. the circuit is prepared for resetting the register 3. It will be reset to the initial state upon the arrival of the control signal at input 27. The same signal is reset into the initial state by the trigger 25 and the pulse counter 21. As a prerequisite for the correct functioning of the device, the control signal at input 27 must always be after the signal at output 31. If the signal at input 27 does not arrive after the signal at output 31 appears, then

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In this case, two impulses will be written to the counter 21 pulses. The signal removed from output 32 indicates the absence of a control signal at input 21 after the generated signal at output 31.

In the case where the signal at output 31 was generated as a result of an accidental failure, then after the appearance of the control signal at input 27 at output 31, there is no signal. If a signal at input 26 is also present after the signal arrives at input 27, then this indicates the presence of a stable interrupt signal at inputs 26.

In the event of malfunctions in the device itself, the signal generation at the control output 29 indicates the presence of a malfunction in the register 3. The signal at the output 29 will be formed when the direct and inverse outputs are simultaneously excited in the jth bit of the register 3. Signal appearance exit 30 indicates a fault in the encoder 17.

The appearance of the signal at the output 34 indicates the occurrence of a malfunction in the elements 9, 10, 11, 13, 14, 15.

The appearance of the signal at output 35 indicates the occurrence of a malfunction in the decoder 20.

The presence of a signal at output 36 indicates the absence of the initial state of the encoder 17 and the decoder 20 when the control signal arrives at the input 28.

The invention makes it possible to increase the reliability of a device by an amount proportional to the probability of a malfunction occurring in its elements; reduce the time of localization of the fault site due to the possibility of generating signals at control points (the appearance of signals indicates the presence of faults in its corresponding elements); increase the testability of the device by increasing the value of the coefficient of unambiguous localization of the fault

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Where

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detected faults in the device at a given level and a given class;

F is the number of detected faults in the device at a given level and a given class. If K Ln tends to 1, then F.

l about rm at l and inventions

A device for monitoring an interrupt handling system containing the first group of elements AND, a group of elements OR, a register, a group of comparison circuits, the first and second triggers, the first to fourth elements AND, the first and second elements OR, the coder, the decoder, the group of elements NOT, the third the OR element, the outputs of the AND elements of the first group are connected respectively to the first inputs of the OR elements, the outputs of which are connected to the group of the installation inputs of the register, the group of information inputs of which are information inputs The triplets, the group of direct outputs are connected to the first inputs of the first and fourth elements and to the first inputs of the group comparison circuits, the second inputs connected to the inverting register outputs, and the outputs to the register state monitoring outputs, the control and data outputs of the encoder are outputs monitoring the state of the encoder and information outputs of the device, respectively, and through a block of elements are NOT connected to the corresponding inputs of the decoder, the outputs of the first and second elements AND are connected to the corresponding yuschim inputs of the second OR gate, the outputs of the third and fourth AND gates are connected to respective inputs of the first OR gate, to distinguish. auschie

20

The second elements of AND are the second installation input of the device, the output of the fifth element I is connected to the second input of the sixth element AND and to the installation input of the first trigger,

15 by the reset input of the sixth element I connected to the output, and the output to the output of the encoder and decoder state control device, the decoder output is connected to the second inputs of the second, fourth and fifth AND elements, the output of the third element OR is the output of the interrupt control signal and connected to the third input of the fifth element, And, with the first inputs

25 elements AND of the third group and with a counting input of the counter, the output of which is the output of the device installation control, and the reset inputs of the counter and the second trigger are connected to the output of the third element And, the group

the outputs of the decoder are connected to the second inputs of the first and third elements Nick the second inputs of the elements of the first group, the outputs of the first and volts

35 of the shaper drivers are connected respectively with the second inputs of the AND elements of the third group, with the first inputs of the AND elements of the second group and with the group of inputs of the encoder, the direct outputs

40 Dy register is connected to the second inputs of the elements And the second and to the third inputs of the elements And the third group, the outputs of the elements And the second group are the outputs of the control logic

The 45 outputs, the outputs of elements AND of the third group are connected to the inputs of the fifth OR element, the output of the second trigger connected to the synchronous input, the output of which is the output of the device that, in order to improve the reliability of the decoder state paths, the outputs of the device, the fourth of the first and The second OR elements are the co and fifth OR elements, the fifth and the sixth elements are united with the inputs of the second and first elements AND, the pulse counter, and the pulse converters.

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the second and second pulse shapers, the second and third groups of elements AND, the first installation input of the device is connected to the first inputs of the AND elements of the first group and the first input of the fourth OR element, the second input of which, the second inputs of the OR elements of the group, the first inputs of the fifth and sixth elements And are the second installation input of the device, the output of the fifth element I is connected to the second input of the sixth element AND and to the installation input of the first trigger,

5, the reset input of the sixth element I connected to the output, and the output to the output of the encoder and decoder state control device, the decoder output connected to the second inputs of the second, fourth and fifth elements AND, the third element output OR is the control output of the interrupt signal and connected with the third input of the first element And, with the first inputs

5 elements AND of the third group and with a counter input of the counter, the output of which is the output of the device installation control, and the reset inputs of the counter and the second trigger are connected to the output of the third element AND, group

the decoder outputs are connected to the second inputs of the first and third elements Nick, the second inputs of the AND elements of the first group, the outputs of the first and second shaper units are connected respectively to the second inputs of the AND elements of the third group, to the first inputs of the AND elements of the second group and to the group of inputs of the encoder, the direct outputs of the register are connected to the second inputs of the elements of the second and to the third inputs of the elements of the third group, the outputs of the elements of the second group are the outputs of the control logic

5, the outputs of the elements AND of the third group are connected to the inputs of the fifth element OR, the output connected to the synchronous input of the second trigger, the output of which is the output of 25, 26;

27

Claims (1)

Claim. A device for monitoring an interrupt processing system 15, comprising a first group of AND elements, a group of OR elements, a register, a group of comparison circuits, first and second triggers, first to fourth AND elements, 20 first and second OR elements, an encoder, a decoder, a group of elements NOT , the third OR element, the outputs of the And elements of the first group are connected respectively to the first inputs of the 25 OR elements of the group, the outputs of which are connected to the group of installation inputs of the register, the group of information inputs of which are information inputs devices, a group of direct 3Q outputs is connected to the first inputs of the And elements from the first to the fourth and to the first inputs of the group comparison circuits, the second inputs are connected to the inverting outputs of the register, and 35 outputs are with the outputs of the register status control, the control and information outputs of the encoder are control outputs the state of the encoder and the information outputs of the device, respectively, and through the block of elements are NOT connected to the corresponding inputs of the decoder, the outputs of the first and second elements AND are connected to the corresponding the corresponding inputs of the second OR element 45, the outputs of the third and fourth AND elements are connected to the second and second pulse shapers, the second and third groups of AND elements, the first installation input of the device is connected to the first inputs of the AND elements of the first group and to the first input of the fourth OR element , the second input of which, the second inputs of the elements OR groups, the first inputs of the fifth and sixth elements AND are the second installation input of the device, the output of the fifth element And is connected to the second input of the sixth element And and with the installation input the first trigger, the reset input connected to the output of the Sixth AND element, and the output to the output of the encoder and decoder status monitor, the decoder output connected to the second inputs of the second, fourth and fifth AND elements, the output of the third OR element is the output of the interrupt signal control and connected to the third input of the fifth AND element, with the first inputs of the AND elements of the third group and with the counter input of the counter, the output of which is the output of the device installation control, and the counter reset inputs and the second trigger are sub are directed to the output of the third element And, the group of outputs of the decoder is connected to the second inputs of the first and third elements / and And to the second inputs of the elements And the first group, the outputs of the first and second formers are connected respectively to the second inputs of the elements And the third group, with the first inputs of the elements And the second group and with the group of inputs of the encoder, the direct outputs of the register are connected to the second inputs of the elements And the second and third inputs of the elements And the third group, the outputs of the elements And the second group are the outputs of the logic control device VA, the outputs of the AND elements of the third group are connected to the inputs of the fifth OR element, the output connected by the corresponding inputs of the first OR element, characterized in that, in order to increase the reliability of the device50, the fourth and fifth OR elements, the fifth and sixth AND elements, and the pulse counter are introduced , a lane with a second trigger sync input, the output of which is the decoder status control output, the outputs of the first and second OR elements are connected to the inputs of the second and first pulse shapers.