SU1341645A1 - Device for interfacing two computers - Google Patents

Abstract

The invention relates to computing and can be used in computer complexes for interfacing digital computers. The aim of the invention is to improve the reliability of information transmission by implementing real-time monitoring. The device contains a shift register 1, two groups of elements And 2 and 3, the first element And 4, counter 5, shaper 6 pulses, decoder 7, the third group 8 elements And, the first element OR 9, the first to fourth registers 10 - 13, block 14 comparisons, the fifth, fourth groups of AND 15 and 16 elements, the second element AND 17, the second element OR 18, the trigger 19, the delay element 20, the third element OR 36. The device provides for bidirectional information transfer between digital computers with serial-to-parallel conversion and with the control of each about words. 1 il. (L with 4 TsTL. O5 4 SL

Description

The invention relates to computing and can be used in computer systems for interfacing digital computers.

The purpose of the invention is to increase the reliability of information transfer due to real-time monitoring.

The drawing shows a block diagram of the proposed device.

The device contains a shift register t, secondly a group of 2 elements And, the first group of 3 elements And, the first

woo, sequential code. In both cases, the number of transmitted sync pulses at input 21 is equal to the number of transmitted words multiplied by the word width.

The exchange of information between two computers is carried out as follows.

ten

25

thirty

The transmitting digital computer (34 or 35) generates an interrupt signal from the receiving digital computer. After a period of time (previously agreed and laid down in

element 4, counter 5, shaper t5 algorithm) the digital computer transmits a sync pulse 6, a decoder 7, a third sy to input 21 and information to the input of a group of 8 AND elements, the first element 22, if it is transmitting or OR 9, from the first on the fourth register - sync pulses to the input 21 and receivers 10 - 13, the fourth block of the group

the second element AND 17, the second element OR 18, the trigger 19, the delay element 20, the inputs 21 and 22 of the device for connecting, respectively, the synchronization outputs and information of the first digital computer, the outputs 23 and 24 of the device for connecting respectively the information input and the interrupt input of the first digital computer, input- output 25 of the device for connecting the data output / output of the second digital computer, inputs 26 - 29 of the device for connecting the outputs of the read signal, the third address signal of the write, the second address signal of the second digital computer, output 30 of the device for connecting the start of the second digital computer, input 31 of the device for connecting the first address output of the second digital computer, interrupt inputs 32 and 33, the second 34 and the first 35 digital computers, the third

element OR 36.

s

The device works as follows.

The digital computer 35, when transmitting information on input 21, transmits a continuous series of clock pulses, the accompanying information on input 22. The information is an array of words equal to one or more of sixteen bits, i.e. each word is sixteen bits. The coincidence of sync pulses at inputs 21 and 22 means the presence of 1, and if there is a sync pulse only at input 21, then O. TsVM 35 at the reception of information transmits on input 21 only sync pulses, and at output 23, CMV 34 transmits an array through the information exchange device one or more comparison terms, the fifth information from the output 23, if it is

15 and 16 elements AND, on is a receiver. The number of words transmitted is transmitted by a separate sending of one word. I

Register 11 can be in two states: the Write state, in which the AND elements of group 2 are prepared for opening, and the Read state, in which the AND elements of group 3 are prepared for opening. Translation of register 11 into one state or another is carried out DVM 34 according to the information received at input 29 (since (access occurs to register 11), from input-output 25 and with the help of a control signal supplied to

35 input 28. Recording from the digital computer 34 to the register 10 is made according to information received from the output 30, from the input-output 25 and from the input 28. The reading from the register 10 to the digital computer 34 is carried out

40 at the input-output 25 in the presence of information (ie, single signals) at the output 30 and input 26.

If it is necessary to transfer information from the digital computer 34 to the digital computer 35, then you need 45 to send a signal to Record on input 28 and select the address on input 27. In this case, using input-output 25, one word is written to register 10. This word means the following: the information recorded in the first bit, i, is received or transmitted by the information (1 or O, respectively), and the meaning of the remaining bits is determined by the number of transmitted words.

50

55

In the presence of signals at inputs 28 and 29 and the units in the first discharge of input-output 25, the register 11 forms

woo, sequential code. In both cases, the number of transmitted sync pulses at input 21 is equal to the number of transmitted words multiplied by the word width.

The exchange of information between two computers is carried out as follows.

In the presence of signals at inputs 28 and 29 and the units in the first discharge of input-output 25, the register 11 forms

discovery

elements AND 2. The signal from the output of the element OR 9 provides the opening of the elements AND of the second group 2, thereby overwriting the information from register 10 into register 1. DVM 34 after transmitting the interrupt signal enters the stop state.

If there are signals at inputs 31 and 28 and units in the first bit at input-output 25 at the output of the first element I 4, an interrupt signal is generated for the digital computer 35. The digital computer 35, after processing the interrupt signal, transmits to input sixteen sixteen for sixteen bits of sync pulses that provide Overwriting information from register 1 to digital computer 35, the clock pulses are counted by counter 5, and each clock pulse is a shift pulse for register 1. After counting sixteen pulses, counter 5 is reset to zero state. Upon the arrival of the six-second clock pulse, counter 5 generates a signal to driver 6, which in turn transmits to output 30 a signal for starting the digital computer 34. To interrupt the operation of digital computer 34, digital computer 35 generates a signal at output 32, which is fed to input 33 of digital computer 34.

When monitoring the operation of the device is as follows.

When transmitting information from the digital computer 35 to the digital computer 34, the counting pulses at input 21 simultaneously arrive at the shift register .1 and at counter 5, from the output of which signals arrive at the inputs of the decoder 7. Information from input 22 through the corresponding open element I 8 of the third group is equal to is written to the register 12. From the register output, the recorded information is fed to the first information inputs of the comparison unit 14. At the same time information from the shift register 1 through the open signal Read from the register

11 elements AND of the first group are recorded at 50. The digital computer containing the shaper imets into register 10 and is read at input-output 25 at digital computer 34. The same information from input-output 25 is fed to the inputs of elements AND 15 of the fifth group, which are opened upon receipt signal to read input 26. The output information from elements AND 15 of the group enters through the elements OR 16 to the second information inputs.

pulses, shift register, first, second groups of elements AND, counts first element. And the first element is the first, second registers, and 55 the serial input of the SD register is connected to the input of the device and connected to the information output of the first digital computer, the first input of the first element AND connected to device input

block 14 comparison. The comparison in block 14 is made when it arrives from the readout signal at input 26. This signal passes through the delay element 20, which delays the control signal by the time required for the information from input / output 25 to the inputs of the comparison unit 14.

When transferring information from the digital computer 34 to the digital computer 35, information is recorded simultaneously in register 10 and register 13. Then, from register 10 information And opened by a signal received from register 11, elements And 2 are overwritten into shift register 1. In accordance with the operation of the device, the information begins to flow into the digital computer 35 at the input 23. At the same time, the information is recorded in the register 12. The recording algorithm is similar to that indicated above.

When the sixteenth pulse arrives at counter 5, the signal from the decoder arrives at the first input of the element 17, the second input of which contains the signal from the trigger output 19. The trigger 19 is switched to one state by a signal recording from the register 11. From the output of the element 17 the signal through the element OR 18 enters the control input of the comparator unit 14. This command takes place

comparison of the information received. In the case of equality of codes, the signal from the output Equal to the comparator block 14 is fed to the input P of the flip-flop 19 and to the control input of the register 12 and transfers them to the initial state. In case of inequality of information, the signal from the output Not equal to the comparison block 14 is fed to the control bus, signaling the presence of a fault in the device.

Claims (1)

Claim device for coupling two pulses, shift register, first, second groups of elements AND, counter, first element. AND, first element OR, first, second registers, with the 55 serial input of the shift register connected to the device input for connecting to the information output of the first digital computer, first input of the first element And connected to the input device 5134 for connecting to the write code of the second digital computer, the output of the first element I is connected to the first input of the first element OR, the information input-output of the first register is connected to the input-output of the device for connection to the data input-output of the second digital computer, the output of the parallel shift register code is connected to the first inputs of the elements of the first group, the input of the device for connecting to the recording output of the second digital computer is connected to the recording inputs of the first, second registers, the information input of the second register and the second input of the first element And are connected to input home-output device to connect to the input-output data of the second digital computer, the input sample of the second register is connected to the input of the device to connect to the first address output of the second digital computer, the third input of the first element I is connected to the input of the device to connect to the second address output of the second digital computer, input reading the first register is connected to the input of the device for connecting to the output of the read signal of the second digital computer, the i-th output of the group (i - T, where n is the size of the information word) of the first register connected to the first input of the i-ro element th group, the i-th input of the first register group is connected to you; the i-ro element of the AND element of the first group; with the first, second outputs of the second register, the clock inputs of the shift register and the counter are connected to the input of the device for connecting to the synchronization output of the first digital computer, the output of the i-ro element And the second group is connected to the i-th input of the shift register group, the serial output of the register move in! coupled to an output device for connecting the data input of the first digital computer, the pulse shaper output is coupled to a second input of the first OR gate and to the output device for connection to the triggering input of the second output of first digital computer and connected to the output a device for connecting to the interrupt input of the first digital computer; an input of the device for connecting to the third address output of the second digital computer is connected to 0 645. 6 the sample input of the first register, about that. that, with a., increasing the reliability of information transfer, it was introduced from the third to the fifth group of elements AND, the decoder, the second., the third element OR, the second element AND, the delay element; trigger, third, fourth registers, q comparison unit, with the counter output connected to the decoder input, the i-th output of which is connected to the first input of the i-ro element G; The third group, the pth output of the decoder is connected to ig by the first input of the second element Ik to the input of the pulse formers, the output of equality of the saavnie unit is connected to the zero trigger input and to the synchronization input of the third register ,,: and its information input connect1: ;; - w with the output of the i-ro element And the third group, a single trigger input is connected to the first output of the second register, the trigger output is connected to the second 25 input of the second element AND, the output of which is connected to the first input of the second element OR the second input and output whom connect enes respectively yield element g and the control input of the H-r audio, the first, second c / pch:; .xoflvV; which are connected respectively .g. ,:; the third register of the third register and from::; odag; to the elements of the fourth l of the group, the first, second inputs of the 1st element and the fourth group are connected respectively with the iM output of the group of the fourth register and the code of the i-ro element and the fifth group the input device for connecting to the output of reading the second digital computer is connected to the first inputs of elements of the fifth group and to the input of the delay element 5 input-output of the device for connecting to the data input-output of the second digital computer connected to the information input of the fourth register and to the second inputs of elements of the fifth groups , the input of the device for connecting to the recording output of the second UBM is connected to the screen input of the Thursday 50th register, the output of the failure of the comparison unit is output C1 of pb; to the device, first, ct1-rsk of the third element OR sae, s – g: -: Yen coov-, at the entrance to the whit; PL 55 connections to I1-141Ormatio1-1-5 in; : 1D first. Digital computer and last: shtz G - register shift ,; ., EKCOD tr € be-; gp of the element OR is connected. With the second inputs of the elements AND the third group .. 35 40 45