SU1594555A2 - Interface between two computers - Google Patents

Abstract

The invention relates to computing and can be used to interface two data processing devices. The aim of the invention is to increase speed. The goal is achieved by the fact that the device along. N 1291996 comprising two communication units and two operation code generation units, each communication unit comprising a firmware control unit, a comparison unit, an exchange unit and an OR element, and each operation code generation unit contains a delay element, a control register, two AND elements , the OR element and the bus driver, the exchange node contains two decoders, the command register, the data register, the address register, eleven groups of AND elements, three OR elements, and the AND counter into each communication unit, are entered into each communication unit yre group elements and with respective linkages. 6 Il.

Description

The invention relates to computing, can be used to interface two data processing devices and is an improvement to the device by author. No. 1291996;

The purpose of the invention is to increase the speed: by eliminating the set of commands for entering the address and combining the operation time of the microprogram automat with the operations of entering information into the data register.

On. Fig. I shows a block diagram of a device for interfacing two electronic computers; Fig. 2 illustrates the microprocess control unit; Ia fig.Z - node exchange; Figures 4 and 5 show an algorithm for the operation of a firmware control node; 6a, b shows the flow of the data transfer operation (the time intervals spent by the known and proposed devices, where t, t, is the time of entering information into the address register and the data register of the known device, respectively; t is the time of entering information into the command register; t ,, is the operation time of the firmware automat according to the algorithm; .tg, is the time of recording the information in the address counter of the proposed device; the time of entering the information into the second data register of the proposed device).

The device contains (Fig. 1) communication blocks 1 and 2, blocks 3 and 4 formads

with

4 SP

ate sd

1H

to one operation, with evil 5 and micro-software control, information exchange nodes 7 and 8, elements AND 9 and 10, first 11 and second 12 elements OR, nodes 13 and 1L of comparison, delay elements 15 and 16, registers 17 and 18 controls, second elements AND 19 and 20, first elements AND 21 and 22, third 23 and fourth 24 elements OR, bus drivers 25 and 26, groups 27 and 28 of the command inputs / outputs of communication units, groups 29 and 30 of the address / information inputs / outputs of communication units, codes of 31 and 32 bus drivers, inputs 33 and 34 of the group address, lines 35 and 36 of the group of inputs / outputs of the first second and second communication units, lines 37 and 38

At the initial time, the computer 1 and computer 2 in the groups of interface control signals generate Reset signals received via one of the input / output circuits 27 (28) of the communication unit to the input of the setting in the register 47 of the microinstruction addresses (RAM) and provide the RAM outputs 47 address of the first

groups of outputs of the first and second block of 20 microcommands of the working microprogram.

generation of the operation code, lines 39 and 40 of the outputs of the first and second: blocks of forming the operation code (the operation code chain Input), lines 41 and 42 of the outputs of the first and second blocks of forming the operation code (chain of the operation code Output).

The firmware control node contains (FIG. 2) buffer amplifiers 43 and 44, multiplexer 45, master oscillator 46, microcommand address register 47, read-only memory 48, rpiynny inputs 49 of the microprocess control node, and microcode control codes 50-54 , group of outputs 55 of the firmware control node.

The exchange node contains (fig.Z) the decoder 56, the decoder 57 commands, the group of elements And 58-68, the elements OR 69 and 70, the counter 71 addresses, the register 72 data, the element OR 73, the register 74 commands, the second group of inputs 75 the exchange node, the first input 76 of the exchange node, the third 77 and the second 78 inputs of the exchange node, the first group of inputs 79 of the exchange node, the fourth input 80 of the exchange node, the first 81, the second 82 and the third 83 groups of inputs / outputs of the exchange node, the group of 84 codes exchange, code of the exchange node, the group of elements And 86-89, register 90 addresses

(second data register).

l

We consider the device operation using the example of using it to contain two universal ones. Computer-type Electronics-60, having a common bus type interface.

Node 5 (6) is a firmware automaton (MA) implemented on register 47 (automaton memory elements) permanently memorized.

25 to the device (ROM) 48 (firmware memory of the automaton), multiplexer 45 (the element providing the conditional transitions of the automaton), while the automatization is synchronized by the master oscillator 46, which forms the pulse sequence supplied to the dynamic control input PAM 47 o

In the initial state MA at the output

35 53-55 forms the code that arrives at the inputs 73 and 76 of the node 7 (8) of the exchange and the input of the element 9. This code provides at the output of the decoder 56 a signal that opens And 62 elements.

40 this signals from the highway 29 (30) through the group of inputs / outputs 81 of the node 7 (8) of the exchange through the elements 62 and arrive at the group of inputs / outputs 82: the node of the exchange.

45

50

55

Preparation of the interface device for operation and transfer of information is carried out by cycles of writing (reading) information in (from) registers 72 (90), 74 and the counter 71 of the node address 8 (7) of the exchange.

The transfer of the first word of information from the computer 1 and computer 2 initiated by computer 1 includes a cycle of recording the address of the first cell of the computer 2 into the counter 71 of the node address 8 for the first array of the transmitted information module, the cycle of writing to the register 72 (or 90 node 8 exchanges transmitted daink and

four

0

five

In this case, the inputs / outputs 27 and 28 are connected to groups of interface control signals, respectively, from the first and second computers.

The inputs 29 and 30 are supplied with groups of data address signal signals, respectively, from the first and second computers. Outputs 31 and 32. Bus drivers are connected to the CIP of the interface of the computer 1 and the computer 2.

At the initial time, the computer 1 and computer 2 in the groups of interface control signals generate Reset signals received via one of the input / output circuits 27 (28) of the communication unit to the input of the setting in the register 47 of the microinstruction addresses (RAM) and provide the RAM outputs 47 address of the first

0 microcommand working firmware.

Node 5 (6) is a microprogrammed automaton (MA) implemented on register 47 (automaton memory elements) permanently memorizing.

device (ROM) 48 (automaton firmware memory), multiplexer 45 (element providing automatic transitions of the automaton), while the automaton synchronization is performed by master oscillator 46, which forms the pulse sequence supplied to the dynamic control input of RAM 47 o

In the initial state MA at the outputs

53-55 generates a code that arrives at the inputs 73 and 76 of the node 7 (8) of the exchange and the input element And 9. This code provides at the output of the decoder 56 a signal that opens the elements And 62. When

In this case, the signals from the highway 29 (30) through the group of inputs / outputs 81 of the node 7 (8) of the exchange, through the elements 62, arrive at the group of inputs / outputs 82: of the exchange node.

Preparation of the interface device for operation and transfer of information is carried out by cycles of writing (reading) information in (from) registers 72 (90), 74 and the counter 71 of the node address 8 (7) of the exchange.

The transfer of the first word of information from the computer 1 and computer 2 initiated by computer 1 includes a cycle of recording in the counter 71 of the address of node 8 the exchange of the address of the first cell of computer memory 2 for the first post, the array of transmitted information, the cycle of writing to the register 72 (or 90 a) node 8 exchange transmitted dink and

51594555

in register 74 node 8 exchange- Output.

write cycle

on the opcode

The transfer of information from computer 2 to computer 1 initiated by computer 1 includes a write cycle in the counter 71 of the node address 8 exchange address of the first memory cell of the computer 2 for the first element of the array of information transmitted, the write cycle in the register 74 of the node 8 exchange operation input code and read cycle register 72 (or 90) node 8 exchange the required information.

The transfer of information on the initiative of computer 2 is similar, but the registers of the exchange node 7 are used. The exchange of information between the register 72 (or 90) and the memory of the computer 2 (1) is carried out in the mode

direct memory access under the control of the MA of the corresponding node 6 (5) at the end of the cycle of recording the operation code in the register 74. The simultaneous operation of the computer I and the computer 2 is ensured by the presence of two communication lines 35, 37, 39, 41 and 36, 38, 40, 42, allowing each of the computers: to carry out an independent exchange with registers 74 and 72 and the counter 71 of the address of the corresponding nodes 8 (7) of exchange.

Consider the cycles of writing (reading) information from the computer 1 to (from) registers 72, 74 and the counter 21 of the address of node 8 of the exchange.

In accordance with the logic of the interface, the Community in the first phase of each exchange cycle by group

the address / information I / O 29 is transferred the address of the register,

With which the exchange will take place, with some delay in relation to the transfer of the address, the SIL signal is transmitted over the I / O group 27. The address signals are transmitted by the exchange node from the I / O 81 via elements 62 to the outputs 82, the higher bits are fed to the second inputs Comparison nodes 13, to the first inputs of the comparison nodes 13, supply the code of the group, the address of the interface device assigned to it in the address space of the computer. When the address coincides, the second inputs 33 of the node 13 are compared with when the first inputs at its output form a signal of a logical unit arriving at the information input of the control register 17. On the group of inputs of the register 17 control post10

15

20

25

in mi ni che

40 on about on with

45 no more

50 cent to

. to u on

55 about 57 log in 71

thirty

35

0

five

0

five

From the highway 35, lower address bits determine the address of one of the registers 72, 74 or counter 71. The SIL signal through amplifiers 44 is fed to output 52 of node 5 and then to the input of the installation in O of control register 17 and input of delay element 15. At the same time, the presence of the SIL signal at the setup input of the register 17 ensures the inactive state of this input.

From the output of the delay element 15, the SIL signal by the active level is fed to the input of the register register 17 and records the address code of one of the registers 72, 74 or the counter 71 applied to the group of information inputs of the control register 17 and the signal from the output of the comparison node 13

The second phase of the exchange cycle will be considered separately for the write and read operations of registers 72, 74 and the counter 71 of the exchange node 8.

Record operations. The second phase of the exchange cycle begins with the removal of the address from the group of address / information inputs / outputs 29, setting the recorded information and signal arrival. Output from the interface of the computer 1 through one of the circuits of the group of inputs / outputs 27 through amplifiers 44 of node 5 to its output 51 and the output of the communication unit 1, to the input of the operation code generation unit 3 and the input of the first element 21 of the operation code generation unit 3. The entered information comes through the chains 29, 81 through the elements And 62 of the node 7 of the exchange

0 to the group of I / O 82 of the exchange node 7 and through the highway 35 further to the group of I / O 83 of the node 8 of the exchange of the second communication unit 2. With the coincidence of the signals on the two inputs

5 of the first element AND 21 (signal Output and the recorded information from element 13) of the operation code generation unit 3, the signal supplied through the output of the element 21 is generated

0 circuit 41 to the input 78 of the node 8 exchange, which, together with a group of signals

the address code from the outputs of the control register 17 supplied via the chains 37 to the group of inputs 79 of the node 8 of the exchange,

5 provides, at the output of the decoder 57, a signal for recording information from the I / O group 83 of the exchange node 8 into,: one of the registers 72, 74 or the address 71 counter of the exchange node 3.

0

five

You can write one of the registers or go directly to the input. About the account

The number of the register or address counter is provided with a code supplied from the outputs of the register 17 control through chains 37 to input groups 79 of exchange node 8, and a signal at input 78. Signals from the output of the decoder 57 (recording signals) ensure the opening of one of the element groups And 59 and (з1 and information supply to the registers 72 and 74 and the counter 71. At the same time, through the corresponding elements OR 70 and 73, the recording signals go to the input 72 "74

71

addresses and write information to the selected node. The formation of the response signal (CIP) at the computer interface is carried out by the SHSh 23 element and the bus driver 25, from which the CIP signal is fed to the computer interface.

The computer J, having received the SIP signal from the device, removes the output signal, which results in the removal of the recording signal generated by the decoder 57.

Signal Dismissing The output provides a snip off of the CIP signal formed by the element OR 23 and the bus driver 25 o

Phase The output is completed by removing the SIL signal at the inputs / outputs 27 of the first communication unit 1. In this case, the output of the installation in the O register of the control 17 is set to the active level and the register 17 is reset to the zero state, ensuring the removal of the enabling signal at the input of the first And 21 element

This causes the formation at the output of the element 21 of a logical zero, which causes the exchange node 57 to be replaced in the neutral state.

Operation Reading g The second phase of the exchange cycle begins with the removal of the address from the group of address / informational inputs / outputs 29 and the signal input. Input from the computer interface through one of the circuits of the group of inputs / outputs 27 through amplifiers 44 of node 5 to output 50 of the control node and further To the input of the second element AND 19 of the operation code generation unit 3, From the second element AND 19, the coincidence signal (the Input signal and the recorded information from the element 13) is fed to the input of the OR element 11 of the communication unit 1 at one of the inputs of the OR element 23 and

0

five

0

five

0

five

0

five

0

five

chain 39 to the input 77 of node 8 exchange. From the output of the element OR 11, the signal enters the input 76 of the node 7 of the exchange of the first communication unit and ensures the formation at the output of the decoder 56 of the node 7 of the signal exchange opening the AND 63 elements and blocking the elements. 62. Further, the processes are similar to the Write operation, except that the code on the decoder 57 of the exchange node 8, is fed together via the chains 37, 39 and the decoder 57 of the exchange node 8 forms one of the signals (read signal), which opens one of the AND elements 66-68 and providing the translation of the contents of one of the registers 72, 74 or the address counter 71 to the I / O group 83 of the exchange node 8 and then through the I / O group 82 of the exchange node 7, And 63 elements, I / O group 81 of the node 7 exchange circuit 29 into the computer interface 1.

There is no MA function. After setting the RAM 4 to the zero state, the first microcommand of the microprogram is selected from the ROM 48, which provides the logic of the operation of the node 7 (8).

Figures 4 and 5 illustrate the algorithm for the operation of the node 7 (8) for an Electronics-60 type computer.

The firmware is started by analyzing the signals coming from register 74 through circuits 84 and 85 and representing the command code for the MA on the group of inputs 49 of node 6 (5), and the control signal on the first input of the AND 9 element. From the commands (Input or Output), the MA issues the output from ROM 48 through amplifiers 43 through one of the I / O circuits 27 (28) of the TFD signal, ensuring the requirement to access the computer interface 2 (1). The receipt of the acknowledgment signal from the computer 2 (1) via one of the circuits of the group of inputs / outputs 27 (28) through amplifiers 44 and multiplexer 45 provides branching of the microprogram and setting the output signal through the amplifiers 43 to the interface of the computer 2 (1 ). This signal is kept by the MA until the transfer of information to (from) the computer memory is completed.

The transfer of information to (from) the computer begins with the installation of the code 6 (5) at the outputs 55 and 54, respectively, arriving at the group of inputs 5 of the exchange node 8 and through LI element 12 at the input 76 of the exchange node 8 and.: Providing the output of the decoder 56 the signal that opens element 64. At the same time, the contents of address counters j 1 go through group I / O 81 to line 30 (29) address / data of computer 2 (1) and are interpreted by the computer as the address from which the operation will be performed. Then, at the output of the ROM 48, a SIL signal is generated, which is fed through amplifiers 43, inputs / outputs 28 (27) to the computer interface 2 (1). After that, MA through multiplexer 45 performs an analysis of the type of command on the group of inputs 49 and proceeds to the execution of the Input and Output operations. Upon detection of the command, the MA Output at the outputs 55, 54 and 53 generates a code arriving respectively at the inputs 75 and 76 of the exchange node 8 and, through the AND 10 element at the input 80 of the exchange node 8. This code provides, at the output of the decoder 56, the removal of the signal opening the element 64 and the appearance of the signal opening the element 65 and increasing the contents of the address counter 71 on circuit 53, the input of element 10 and input 80 of the exchange node 8.

At the same time, the contents of the data register 72 goes through the input-output / output group 81 of the exchange node 8 (7) to the computer 2 (1), and the contents of the address counter 71 are incremented by one. Then from the ROM 48 through the amplifiers 43 to the inputs / outputs 27 (28) the output signal is output to the computer. then MA waits from the computer 2 (1) the confirmation signal SIP, which comes from the computer 2 (1) through one of the circuits through amplifiers 44 to the multiplexer 45. When the signal is received, the MAI removes the previously generated signal from the ROM 48 to the output 28 (27). The MA then analyzes the CIP signal coming from the computer interface 2, and at the same time re-activates the signal at input 80, increasing the number of counters 71 by one. When a CIP MA signal is reset in the computer interface, the MA resets all previously generated signals (if the loop has been executed) and returns to the initial state. At the same time, at outputs 55 and

4555. 10

54 generates a code that provides the output at the output of the decoder 56 of the reset signal of the command register 74. When the Input MA command is detected at the inputs 49, the MA enters the memory from the ROM through the signal amplifiers 43 to the device inputs / outputs 28 (27). The receipt of a CIP signal from a computer along one of the input / output circuits 27 (28) through amplifiers 44 to multiplexer 45 means that the required information is supplied to circuits 30 (29). MA performs the formation at the output of the ROM 48 and at the outputs 55 and 54 of the code, which ensures the removal of the signal that opens the element 64, and the appearance at the output of the decoder 56 signal 10

15

0

five

0

five

0

five

0

five

the input element 60 and through the information OR 70 recording information in the register 72 data from the inputs / outputs 81. At the same time, the signal at input 80 is activated, providing an increase in the content of the address counter by one. Further, the MA completes the execution of the Enter operation, similar to the completion of the Vsod operation.

During the execution of the MA operation, the Input or View computer I produces, in the same way as described, the cycle of writing (reading) information to (from) the second data register 90.

The transfer of the address of register 90 and the generation of control signals at the output of the operation code generation unit occurs as in the first phase of the exchange cycle.

In the second phase of the exchange cycle, the operation Write and Read is similar to the operations with the data register 72.

Simultaneously with the considered operations executed by the first computer, the exchange operations initiated by the second computer are similarly carried out.

In this case, the transfer of information between the communication units is carried out via the highway 36, the control information. chi is transmitted on lines 38, 30 and 42, i.e. the simultaneous transmission of information words from the first and second computers is carried out with a simultaneous increase in two by the contents of the counter 71 of the address.

An increase in the two contents of the counter 71 of the address occurs only when the array of information is transferred after the execution of a certain command.

DM, sent to the command register (for example, Input + 1 / Output +1). In other cases, the +1 input of the counter 71 of the address is blocked by sending commands to the register of I / O commands, at which B; An additional bit appears to be a potential that prohibits the passage of pulses through valve 9 (10) to the | 1yt input of the address counter.

Formula of the invention. I Device for conjugation of two. ;. er;) 1 computer on. Св. No. 1291996, which differs from the fact that, in order to increase speed, an I element is entered into each block of the C4, and an address counter is added to each block of the exchange, and from the twelfth to the fifteenth group of AND elements, and in the communication block the first input of the AND element is connected to the output of the bit increment of the instruction register address, and the second input of the element 4 AND is connected to the fifth code output 12

0

the house of the firmware control node, the output of the AND element is connected to the counting input of the address counter of the exchange node, in which the group of information inputs of the address counter is connected to the pairwise combined outputs of the AND elements of the twelfth and thirteenth groups, and the synchronization input of the address counter is connected to the seventh output of the first decoder and the second inputs elements of the thirteenth group, the group of information outputs of the address counter is connected to the combined

5 first inputs of the elements of the fourteenth and fifteenth groups, the outputs of which are respectively connected to the outputs of the elements of the third / third and seventh groups, the ninth and tenth

The Q outputs of the second decoder are connected to the second inputs of the elements of the fourteenth and twelfth groups, respectively, and the eighth output of the first decoder is connected to the BTopw5 inputs of the elements of the fifteenth group.

27 (28)

7 to gp

, SIA, GPDPPA

.pv, 8bod, reset output,

2

 START

Analysis of the presence of commands from {registers on the first group of inputs 49

Setting the TFD signal on the first group of inputs / outputs 27

Setting the PV signal on the first group of inputs / outputs 27

IT

Installation at the exit: code 54.55 odes for opening the valves 64

Setting the STR signal on the first group of inputs / outputs 27

Type Inlet Analysis 49

FIG. four

Installation at vy.53,54,55

code CHATCHES P & 72, activation of signal 80

Set the signal output. on the first I / O group 27

CIP Verification Signal Analysis

Not

 ignal CIP in interface reset

Setting the ENTER signal on the first group

I / O 27

CIP Verification Signal Analysis

 chased CL from entry 27 entered

Not

Installation of 53,54,55 RECORD code on PG-72, activation of signal 80

5

2 array element

MilELEEl

  p - array element

51Ш717Л

6

Claims (1)

The claims of the device for pairing two: electronic computers auth.St. No. 1291996, characterized in that, in order to increase speed, an I element is entered into every block, an address counter and a twelfth to fifteenth I group of elements are entered into each exchange block, and the first input of the element is in the communication block And connected to the output of the discharge increment the address of the register of commands, and the second input of the element I is connected to the fifth code output 12 ten 15 20 25 the house of the firmware control node, the output of the AND element is connected to the counting input of the address counter of the exchange node, in which the group of information inputs of the address counter is connected to the pairwise combined outputs of the AND elements of the twelfth and thirteenth groups, and the synchronization input of the address counter is connected to the seventh output of the first decoder and second inputs elements of the thirteenth group, the group of information outputs of the address counter is connected to the combined first inputs of the elements of the fourteenth and fifteenth groups, the outputs of which are x respectively connected to the outputs of the AND third groups .i seventh, ninth, and tenth outputs of the second decoder coupled to the second inputs of AND gates of the twelfth and fourteenth groups, respectively, and the eighth output pervo'go decoder coupled to second inputs of AND gates of the fifteenth group. 1594555 PhyvZ 1594555 Setting the PV signal on the first group of inputs / outputs 27 Installation on.outputs 54.55 code for opening valves 64 Setting the STR signal on the first group of inputs / outputs 27 Analysis of the type of command at the entrance 49 FIG. four 1594555 Installation on the vy.53,54,55 code READING RS-72, activation of the signal 80 ..................... V "........................... .. Set signal OUTPUT. on the first group of inputs / outputs 27 SIP confirmation signal analysis Setting the ENTER Signal on the First I / O Group 27 Installation on the out. 53,54,55 RECORD code in RS-72, activation of signal 80 g Taking signals INPUT (OUTPUT) and signal 80 * CIP signal analysis, signal activation 80 Not "" CIP signal . ^ '' 'interface reset? well Reset all signals at the output of ROM 48, reset the command to RO-74 (end ) 5 1594555 1 array element 2 element | array ^ d / rd / [7 / g p - array element Dl1Lg / km Rmd | pa2 1d11 1st one* 1st • · one "M *D 7 ΪΑ1 or 6