SU1417002A1 - Device for identifying the address of peripheral module - Google Patents

Abstract

The invention relates to computing and can be used in computer interface devices with peripheral modules. The aim of the invention is to enhance the functionality by more fully utilizing the address space and speeding up. by combining in time the processes of initialization and verification of peripheral modules. The goal is achieved by introducing into the device containing the register 2 addresses, trigger 3, comparison circuit 5 and the element AND-NOT 7, the element OR 1, the trigger 4 and the element 2И-OR 6. The signal at the output of the element 2И-OR 6 makes sense device readiness, address identification in write mode (signal at input 17) and readiness of peripheral - module in read mode (signal at input 16). 1 il. i (L

Description

83 10

eleven

J

ABOUT

The invention relates to computing and can be used in computer interface devices with peripheral modules.

The aim of the invention is to expand the functionality by: more fully utilizing the address space and improving speed by combining the initialization and verification processes of the peripheral modules in time.

The drawing shows a diagram of the device.

The device contains the element OR 1, the address register 2, the first 3 and second 4 triggers, the comparison circuit 5, the element 2И-OR 6, the element AND 7, is connected to the control lines 8, addresses 9 and computer data 10 and has an input AND and an initialization output 12, a bus 13 for communication with a peripheral module, a sample output 14, a sample confirmation input 15, read and write inputs 17, a reset input 18 and a ready output 19.

The device works as follows.

After turning off the power to the device input 18, a reset signal is given. A unit level is input to the device initialization 11 if the device is not the first in a chain of such devices connected in series and zero level if the device is the first. After the initial installation, a unit level is maintained at the outputs 12 and 14 of the device. Initialization begins with the filing of a zero level on the input 11 of the device. After that, the information input of register 2 of the address receives the address assigned to the peripheral module, and the input 17 of the device receives a write signal, which writes the value of the address to register 2 and sets trigger 3, the output of which blocks the OR element 1. For checking the response of the device to the address input 9 is given the assigned value of the address; a single signal appears at the output of the comparison circuit 5: the upper half of the element 2И-OR 6, from the output of which a single signal arrives at the output 19 of the device's readiness.

Next, the response of the peripheral module is checked, for which a read signal is sent to the input 16, which records

5 0 5

0

five

0

five

50

55

trigger 4 1 from the output of trigger 3. Signals from the outputs of trigger 4 open the element AND-NOT 7, the lower half of element 2И-OR 6 and close the upper half of element 2И-ШШ 6, simultaneously issuing a zero signal to output 12 to initialize the next one in the chain devices. At output 14 of the peripheral module sample, a signal appears, having received that, the healthy module confirms the sample at input 15 of the device. The signal from the input 15 through the open lower half of the element 2-OR 6 arrives at the output 19 of the readiness of the device.

Unlike the prototype for the operation of the proposed device is not required. It is necessary to reserve one of the bits of entry 9 of the address as a service one.

Claims (1)

Invention Formula A device for identifying an address of a peripheral module that contains an address register, a trigger, a comparison circuit, and an NAND element, the information input of the address register being the information input of the device, the output of the address register is connected to the first input of the comparison circuit, the second input of which is the address input of the device the output of the comparison circuit is connected to the first input of the NAND element, the reset inputs of the address register and the first flip-flop are connected to the reset input of the device, characterized in that, in order to expand the class of Because of the more complete use of the address space and speeding by combining the initialization processes and checking the peripheral devices in time, the OR element, the trigger and the 2I-OR element are entered into it, the first input of the OR element is the recording entry of the device, the second input of the element OR is the device initialization input, the third input of the OR element is connected to the output of the first trigger, with informational information: the house of the second trigger, to the first input of element 2I-1-SHI and to the second input of the AND-NOT element, the third the input of which is connected to the direct output of the second trigger, the inverse output of which is connected to the initialization output of the device and to the second input of element 2I-OR, the third of which is 3U17002. dinene with the output of the comparison circuit, even-carrying devices, the reset input is the second input of the element 2И-OR of the connected trigger connected to the reset input with the direct output of the second trigger, the device, the synchronization input, the second input of the 2I-OR element is the trigger input is the read input the input of the device device sample acknowledgment, the output of the OR element, the output of the AND-NOT element is not. with register sync input the device sample output, the output of the e-address and the installation input Cop 2I-OR is a ready-flip-flop output.