SU1580385A1 - Device for interfacing computers - Google Patents

Abstract

The invention relates to computing and can be used to interface two computers in multi-machine computing systems. The device contains two communication units and two operation code generation units, each communication unit contains a firmware control unit, an exchange unit, a comparison unit and the first OR element, each exchange unit contains two decoders, command register, data register, eleven groups of AND elements , three elements OR - NOT. In order to increase the speed of the device by eliminating the operation of entering the address and combining the operation of communication blocks, the device contains an AND element and an NOT element, each communication unit contains an AND element and a second OR element, each exchange unit contains an address counter with the twelfth to sixteenth group elements AND, two elements NOT, nine elements OR, and ten elements I. 2 Il.

Description

The invention relates to computing and can be used to interface two computers in multi-machine computing systems.

The purpose of the invention is to increase the speed of the device by eliminating the operations of entering the address and combining the work of the communication units.

Figure 1 is a diagram of the device; 2 is a diagram of a communication unit; FIG. 3 is a block diagram of the formation of the operation code; Fig. 4 is a diagram of a firmware control block; figure 5 - diagram of the exchange unit.

The device (figure 1) contains blocks 1, 2 communications, blocks 3, 4 of the formation of the operation code, element 5, element 6, NOT 6, command inputs-outputs 7.8 of block 1 (2) communications, the first information inputs-outputs 9, 10 of block 1 (2) communication, address inputs 11, 12 of block 1 (2) of communication, outputs 13 ,, 14 clock signal of blocks 1, 2 of communication, group of outputs 15, 16 of operation code of block 1 (2) prohibitions, outputs 17, 18 of the prohibition of communication block 1 (2), first control input 19 (20) of communication block 1 (2), input 21 (22) of communication block 1 (2), output 23 (24) output of block 1 (2) of communication, output 25 (26) of interface of block 1 (2) of communication, output 27 (28) of equality of block 1 (2) with zi, the second information inputs-inputs 29, 30 of communication block 1 (2), the first and second inputs 31, 32 of controlling the second address of communication blocks 1, 2, the first and second inputs 33, 34 of controlling the first address of blocks 1, 2 links, output 35 (36) increment of block 1 (2) links, first

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entry 37f 38 of the recording unit 1 (2) communication, output 39 (40) mode of the unit 1 (2) communication, the second control input 41 of the blocks 1, 2 communication, the third control input 42 of the blocks 1, 2 communication, group of outputs 43, 44 of the control code of the 1 (2) communication block.

The communication unit (Fig.2) contains a block

45 microprogrammed control unit

46 exchange, the first element OR 47, the element AND 48, the second element OR 49, the comparison unit 50, the group of code inputs 51 of the exchange unit, the group of code outputs 52 of the exchange unit, the control output 53 of the firmware control unit, the input 54 of the increments of the exchange unit, output 55 the increment code of the interchange block, the first input 56 of the interchange block reading.

The operation code generating unit (FIG. 3) contains a delay element 57, a control register 58, AND 59, 60 first elements, AND 61 element, and a bus driver 62.

The microprogram control unit (Fig. 4) contains a multiplexer 63, two buffer amplifiers 64, 65, a pulse generator 66, an AND 67 element, a microcommand address register 68, a persistent storage device 69.

The exchange unit (figure 5) contains the first and second elements OR 70, 71, the first element AND 72, two decoders 73, 74, the second element AND 75, the first element OR-NOT 76, the third, fourth and five elements OR 77- 79, the third element AND 80, the sixth and seventh elements OR 81, 82, the fourth, fifth and sixth elements AND 83-85, the eighth element OR 86, the seventh element

And 87, the second element OR-NOT 88, the first and second groups of elements And 89, 90, the third element OR-NOT 91, from the third to the sixth group of elements And 92-95, the eighth and ninth elements And 96, 97, the address counter 98, the data register 99, the command register 100, the ninth element OR 101, the element NOT 102, from the seventh to the sixteenth group of elements AND 103-112.

The operation of the device is shown by the example of its use for interfacing two electronic computers of the type of Electronics-60. In this case, the inputs-outputs 7, 8 are connected to groups of interface control signals, respectively, from the first and second computers.

The inputs 9, 10 are served by groups of data address signal signals, respectively, from the first and second computers. The outputs 13, 14 of the bus formers 62 are connected to the CIPs of the interface of the computer 1 and the computer 2.

At the initial time, computers 1 and 2 computers in groups of interface control signals generate Reset signals received via one of the input output circuit 7, 8 of the communication unit to the input of the register of micro-commands (RAM) register O and the address of the first micro-command on its outputs working firmware. Block 45 is a microprogrammed automaton (MA) implemented on register 68 (automaton memory elements), persistent storage device (ROM) 69 (automaton microprogram memory), multiplexer 63 (element providing automatic transitions of the automaton), automaton synchronization implemented by generator 66, forming a pulse sequence fed to a dynamic control input of PAM 68.

The device performs two types of information exchange between the computer 1 and the computer 2:

simultaneous bi-directional, in which information is simultaneously transmitted from the first to the second and from the second to the first computer;

sequential unidirectional, in which alternate transmission of information from one computer to another occurs.

The transfer of information in both types of exchange is accompanied by a simultaneous increase in the two contents of the account.

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Chica 98 addresses. The type of exchange is specified by the operation code written to the command register.

Bidirectional exchange. In the initial state, the microprogram automat at the outputs 39 (40), 17 (18), 43 (44), 35 (36), 53, 51 forms the following code:

39, 40 - high level signals;

17, 18 - high level signals;

43, 44 - signals at the inputs of the decoder 74;

35, 36 - low level signals;

53 - low level signal;

51 - signals to the inputs of the decoder 73.

The code at the input of the decoder 73 provides at its first output a signal that opens the elements AND 104. At the same time, the signals from the inputs-outputs 9, 10 through the group of inputs-outputs of the exchange unit 46 arrive at the group of inputs-outputs 29, 30.

Preparation of the interface device for operation and transfer of information is carried out by cycles of writing and reading information from registers 99, 100 of counter 98 of address block 46 of the exchange of the second 2 and first communication blocks.

The transfer of the first word of information from the computer 1 and computer 2 on the initiative of computer 1 includes:

a write cycle in the counter 98 of the address of the block 46 of the exchange of the block 2 of the communication of the address of the first cell of the computer 2 for the first element of the array of information transmitted;

a write cycle in the register 99 of the block 46 of the exchange unit 2 of the communication of the transmitted data;

the write cycle in the register 100 of the block 46 of the exchange unit 2 communication operation code Output.

The transfer of information from computer 2 to computer 1 on the initiative of computer 1 includes:

a write cycle in the counter 98 of the address of the block 46 of the exchange of the block 2 of the communication of the address of the first cell of the computer 2 for the first element of the array of information transmitted;

the write cycle in the register 100 of the block 46 of the exchange unit 2 communication operation code

a read cycle from register 99 of block 46 of the exchange of block 2 for communication of the required information.

The transfer of information on the initiative of the computer 2 is similar, but

The registers of the communication block 46 of the communication block 1 are used. The exchange of information between the register 99 and the computer memory 2 (1) is carried out in the mode of direct memory access under the control of the MA of the corresponding block 45 of the communication block 2 (1) at the end of the cycle of recording the operation code in register 100. Simultaneity of operation of jg of computer 1 and computer 2 is ensured by the presence of two lines 29, 33, 37, 31, 19 and 30, 34, 38, 32, 20 of communication, allowing each of the computers to An independent exchange with registers -100, 99 15 and the counter 98 of the address of the blocks 46 of the exchange of the corresponding blocks 2 (1) of communication. Consider the cycles of writing (reading) information from the computer .1 into registers 99, 100, the counter 98 of the address of the exchange unit 46 20 and the communication unit 2. In accordance with the logic of the Common Bus interface, in the first phase of each exchange cycle, the address / data lines 9 transmit the address of the register with which the exchange will take place, with some delay in relation to the transfer of the address, a signal is issued for the group of inputs -exits 7.

Address signals are transmitted by exchange exchange block 46 of communication block 1 from input-output 9 through elements 104 to output 29, high bits are fed to the second inputs of comparison blocks 50, to the first inputs 11 of blocks 50, the comparison code is supplied with the group address code devices associated with it in the address space of a computer. When the address coincides, the second inputs 29 of the comparison unit 50 with the first inputs code 40 at its output 27 form a signal of a logical unit arriving at the information input of the control register 58. The group of inputs 29 of the control register 58 on the D5 is stepped from the trunk 29 by the lower order bits, which determine the address of one of the registers 99, 100 or the counter 98 of the address. The signal SIA through the amplifiers 64 is fed to the output 25 of the node-JQ la 45 and then to the input of the installation in the O register of the control 58 and vhrd element 57. delay; At the same time, the presence of a SIA signal at the setup input of the register 58 ensures the inactive state of this input. From the output of delay element 57, the SIA signal, the active level, enters the input of register entry 58 and

recording the address code of one of the registers 99, 100 or the counter 98, fed to a group of information inputs of the control register 58, and a signal from the output of the comparison node 50.

The second phase of the exchange cycle will be considered separately for the write and read operations of registers 99, 100 and the counter 98 of the exchange unit 46 of the communication unit 2.

Record operations. The second phase of the exchange cycle begins by removing the address from setting the recorded information on lines 9 and signal arrival. Output from the computer interface 1 through one of the circuits of the input-output group 7 through the amplifier of the block, 45 to its output 23 and the output of the communication block 1 the input of the operation code generation unit 3 and the input of the first element AND 60 of the operation code generation unit 3. Recorded information enters the chains 9 through the elements AND 104 of the exchange unit 46 to the input-output group 29 of the exchange unit 46 of the communication unit 1 and through the trunk 29 further to the input-output group 30 of the exchange unit 46 of the second communication unit 2. When the signals at the two inputs of the first element AND 60 (the Output signal and the recorded information from block 50) of the operation code generation unit 3 coincide, the output signal of the element 60 produces a signal supplied through the circuit 37 to the input element AND 83 of the communication unit 46 of the communication unit 2, which, together with the signal group of the address code from the outputs of the control register 58, fed through circuits 31, 33 to the inputs of the elements And 87 ,. 97 of the exchange unit 46 of the communication unit 2, at the output of the decoder 74, the signal for recording information from the group of input-outputs 30 of the exchange unit 46 to one of the registers 99, 100 or the counter 98 of the address of the exchange unit 46 of the communication unit 2.

The number of the register or address counter is provided with a code supplied from the outputs of the control register 58 in circuits 31, 33 to the inputs of the elements 87 of the exchange unit 46 and a signal at the input 39. The signals from the outputs of the decoder 74 (recording signals) provide the opening of one of the groups of elements And 90, 93, 94 and the supply of information to the registers 99, 100 or counter 98. At the same time, through the corresponding elements OR 91, 76, 88, the recording signals arrive at the recording inputs of one of the registers 99, 100 or the counter 98 of the address

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and recording information in the selected unit. The formation of the response signal (CIP) at the computer interface is carried out by the element OR 61 and the bus driver 62, from the output of which the CIP signal is fed to the computer interface

The computer, receiving the CIP signal from the device, removes the output signal, which ultimately leads to the removal of the recording signal generated by the decoder 74. Clearing the output signal ensures the removal of the CIP signal generated by the OR 61 element and the bus driver 62.

Phase The output is completed by removing the BIA signal at the inputs-outputs 7 of the first communication unit 1. At the same time at the entrance to the installation in the register O 58

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from the 1CO register through AND 112 elements along chains 52 and representing the command code for the MA on the group of inputs 52 of the block 45 of the block 2 by communications of the control signal received through the circuit 55 to the first input of the element 48. Upon detection of the mode code and one of the commands (.the input or output) MA performs the output from ROM 69 through amplifiers 65 through one of the input-output circuits 8 of the TFD signal, providing requirements for access to the computer interface 2. The receipt of the confirmation signal of the FPW from the computer 2 outputs 8 through amplifiers 64 to multiplexer 63 provides ve development of the microprogram, and installation at the output of the ROM 69 of the PV signal, coming in through

The active level of the 20 amplifiers 65 on the interface of the computer 2 is set. The torque and the register 58 are reset to the zero state, ensuring the removal of the enable signal at the input of the first element 60. This causes the formation of the output element 60 of the logical zero, which causes a decoder 74 of the exchange unit to the neutral state.

Read operation. The second phase of the exchange cycle begins with the removal of the address from lines 9 and the signal input. Input from the computer interface through one of the circuits of the input-output group 7 through the amplifiers 64 of block 45 to the output 21 of the control unit and further to the input of the second element AND 59 of the code generation unit 3 operations. From the output of the second element I 59, the coincidence signal (the signal Input and the recorded information from block 50) is fed to the input of the element. OR 49 of the communication unit 1, to one of the inputs of the element OR 61 and through the circuit 19 to the input of the element AND 75 of the communication unit 46 of the communication unit 2. From the output of the element OR 49, the signal enters the input 56 of the exchange unit 46 of the first communication unit 1 and provides a signal that opens the AND 105 elements and blocks the AND 104 elements. Further, the processes are similar to the Record operation.

The order of operation of the MA. After setting the RAM 68 to the zero state, the first microcommand of the microprogram is selected from the ROM 69, which provides the logic of the operation of the block 46.

Firmware execution begins with an analysis of the signals coming in.

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The signal is stored on the MA until the transfer of information to (from) the computer memory is completed.

The transfer of information to (from) the computer begins with the installation at outputs 51, 53 of block 45 of communication block 2 of a code that enters the group of inputs 51 of exchange block 46 of communication block 2, respectively, and through the OR 49 element to input 56 of exchange block 46 and provides output 9 is a signal opening elements AND 106. In this case, the contents of the counter 98 of the address are fed through a group of inputs-outputs 10 to the highway 10 address / data of computer 2 and are interpreted by the computer as the address of the cell from which work will be performed. Then, at the output of the ROM 69, a signal is generated from the PIA arriving through amplifiers 65,

Q inputs-outputs 8 in the computer interface 2.

After that, the MA, through multiplexer 63, performs an analysis of the type of command on the input group 52 and proceeds to the execution of the Input or

e Conclusion. Upon detection of the command, the MA terminal at the outputs 53, 51,, 35 forms a code that arrives respectively at the inputs 56, 51 of the exchange unit 46 and through the OR element 47 and the And 48 element at the input 54 of the exchange unit 46 of the communication unit 2. This code provides the removal of the signal opening the elements AND 106, the appearance of the signal opening the elements AND 107, and the signal increasing the contents of the counter 98 address along the circuit: output 35, element OR 47, input of element AND 48, input 54 of device 46 of the exchange block 2 connection. In this case, the contents of the data register 99 comes

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through the group of inputs-outputs 10 of the exchange unit 46 of the communication unit 2 in the computer 2, and the contents of the address counter 98 is increased by 1. Then from the ROM 69 through the amplifiers 65 to the inputs-outputs 8 in the computer a signal is output, then the MA waits COMPUTER 2 SIP confirmation signal, which comes from COMPUTER 2 through one of the circuits through amplifiers 64 to multiplexer 63. When an SIP signal arrives, M removes the previously generated signal from ROM 69 and then outputs the SIP signal received from computer interface 2, simultaneously re-activate signal 54, increasing the content of the counter 98 by 1.

When resetting, from the computer interface of the CIP signal, the MA resets all previously generated signals (the end of the cycle) and returns to the initial state. In this case, a code is formed that ensures that a reset signal appears at the output of the decoder 73, the command register 100. When the input command 52 is detected at the inputs 52, the MA enters the ROM through the amplifiers 65 of the input signal to the inputs-outputs 8 of the device. The receipt of a CIP signal from a computer along one of the input-output circuits 18 through amplifiers 64 to multiplexer 63 means that the required information has been supplied to circuit 10. The MA generates a code at the output of the ROM 69 and at the outputs 53, 5D, 35, which ensures the removal of the signal opening the AND 107 elements, and the appearance at the output of the decoder 73 of the signal entering through the OR 79 element and the opening And 92 elements, and the OR 91 element recording information from the inputs / outputs 10 into the data register 99. At the same time, the signal in the circuit 54 is activated, increasing the address counter contents by 1. Then the MA completes the Input operation in the same way as the Output operation.

Simultaneously with the considered operations performed by the first computer, similarly, exchange operations are initiated by the second computer. At the same time, the transfer of information between communication units is carried out via line 30, the control information is transmitted via lines

38, 34, 20, 32, i.e. the simultaneous transmission of information words from the first and second computers c.

simultaneous increase by 2 of the contents of the counter 98 addresses.

The increase by 2 of the contents of the counter 98 addresses occurs only when sending arrays of information

after the execution of a specific command sent to the command register (for example, Input + 1 / Output + 1).

In other cases, the input of the +1 counter 98 is blocked.

5 addresses by sending commands to the register of commands I / O commands, in which, in an additional discharge, the potential 35 on the circuit 35 prohibits the passage of pulses through

0 element 48 of communication unit 1 (2) to the counting input +1 of the address counter 98.

Unidirectional exchange. Unidirectional exchange increases the speed of information transfer between computers

5 and is used when one of the computers operates in the mode of collecting information from peripheral devices, controlling external processes, etc.

The operation of the device in this mode

0 begins after the information has been recorded in the address and data registers and the instruction code with the bit set (busy) and the unidirectional exchange in the command register of block 46 (for example,

5 communication block 2). In this case, the microprogram automat 45 of the communication unit 2 at the outputs 40, 18, 44, 36 forms the following code:

40 is a low level signal, arriving at the input of element 5 and forming at its output a low level potential, entering at inputs 41 of block 46 exchanging blocks 2 and 1 of communication and prohibiting the flow of control signals from block 3 forming an operation code through elements 72 , 83, 85, 96 block 46 exchange block 2. connection and from block 4 of the formation of the operation code through the elements 72, 83, 85,

96 of the exchange unit 46 of the communication unit 1, the high level signal at the output of the element 6 enters through the circuit 42 to the inputs of the elements AND of the exchange units and permits the passage of control signals from the operation code generation unit 3 through the elements 75, 84, 87,

97 block 46 exchange unit 1 communication and

from block 4 forming the operation code

through the elements 75, 84, 87, 97 of the exchange block 46 of the communication block 2;

18 is a low level signal, which enters the input element And 67 of block 45 of communication block 1 and prohibits the operation of this microprogramming automat; at the output of the decoder 73 of block 46 of the exchange of communication block 1, a potential is formed that allows information to pass through And 104 elements;

44 is a signal input to the decoder 74 of the exchange unit 46 of the communication unit 1 and having a high voltage level;

36 is a low level signal arriving at the input of the OR element 47 of the exchange block 46 of the communication block 1, and starts the execution of the firmware similar to that described.

At this time, the computer 1 transmits the second word of information to the computer 2.

The transfer of information on computer 1 to computer 2 on the initiative of computer 1 includes:

a write cycle in the counter 98 of the exchange block 46 of the block 1 of the communication of the address of the memory cell of the computer 2, with which the exchange will take place;

the write cycle in the register 99 of the block 46 of the exchange unit 1 of the communication of the transmitted data;

cycle write to the register 100 of the block 46 of the exchange unit 1 communication operation code Output.

The transfer of information from computer 2 to computer 1 on the initiative of computer 1 includes:

a write cycle in the counter 98 of the exchange block 46 of the block 1 of the communication of the address of the memory cell of the computer 2 from which the exchange will take place;

the write cycle in the register 100 of the block 46 of the exchange unit 1 communication operation code

a read cycle from register 99 of block 46 of the block 1 of communication of the required information.

The transfer of information on the initiative of computer 2 takes place in the same way, but the counter and registers of the communication block 46 of the communication block 2 are used. The exchange of information between the register 99 and the memory of the computer 2 (1) is performed in the direct memory access mode controlled by the MA 45 of the corresponding block 2 (1) communication at the end of the cycle of writing the operation code to the register 100.

Consider the cycles of writing (reading) information from the computer 1 to the counter 98 and the registers 99, 100 of the exchange block 46 of the communication block 1. In accordance with the logic of the Common Bus interface, in the first phase of each exchange cycle, the address of the register is transmitted via the address / data line. The register address with which the exchange will take place, with some delay in relation to the address transmission, an IAM signal is issued for the I / O group 7 Address signals are transmitted by block 46 of the block of communication block 1 from input-output 9 through elements 104 to outputs 29, the higher bits are sent to the second inputs of comparison unit 50, and the group address of the interface device is supplied to the first inputs of comparison block 50 at military it in the address space of the computer. If the address on the second inputs of the block 50 is matched with the code of the first inputs

5, a signal of a logical unit is inputted at its output to the information input P0 of the control register 58 of the operation code generation unit 3. Per input group D15 Ct

0, the control register 58 comes from the trunk 29 and the lower order bits, which determine the address of the counter or one of the registers 99, 100.

The signal SIA through the amplifiers 64 is fed to the output 25 of the block 45 of the communication block 1 and then to the input of the installation in O of the control register 58 and the input of the delay element 57 of the operation code generation unit 3. At the same time, the QA of the liaison signal of the SIA at the setup input of the register 58 provides the inactive state of this input.

From the output of the delay element 57, the SIA active level signal arrives at the input of the record of register 58 and records the address code of the counter or one of the registers 99, 100, applied to the group of information inputs of the control register 58, and

0 signal from the output of the unit 50 comparison. The second phase of the exchange cycle will be considered separately for the write and read operations of the counter and the registers 100, 99 of the exchange unit 46 of the communication unit 1.

e Recording Operation. The second phase. the exchange cycle begins by removing the address from lines 9, setting the recorded information on lines 9, and arriving at a signal.

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Computer 1 along one of the circuits of the group of input-output 7 through amplifiers 64 of block 45 of block 1 of communication to its output 23 and output of block 1 of communication, n-and block input (, 3 generating the operation code and input of the first element I 60 of block 3 generating an operation code.

When the signals coincide at the two inputs of the first element AND 60 (signal W. Output and recorded information from element 50) of the operation code generation unit 3, the output of the element 60 produces a signal supplied through input 37 to the input element AND 84 of the exchange unit 15 46 of the unit 1 connection, which, together with the group of signals of the address code from the outputs of the control register 58 supplied via the circuits 31, 33 to the inputs of the elements 87, 97 of the block 46 of the exchange of the communication block 1, provides at the output of the decoder 74 an information recording signal with a group of inputs-outputs 9 of the block 46 of the exchange unit 1 communication in a counter or one of the registers 100, 99 25 of the exchange unit 46 of the communication unit 1.

The register number is provided by the code supplied from the register outputs.

58 through the circuits 31, 33 to the group of inputs 31, 33 of the exchange unit 46 of the communication unit 1, the signal at the input 37 acts as a strobe. The signals from the outputs of the decoder 74 (recording signals) ensure the opening of one of the groups of elements AND 89,92,95 and the flow of information to the counter 98 or registers 99, 100 simultaneously through the corresponding elements OR 88, 91, 76. The recording signals are received to the inputs of the record of the counter or one of the registers up to 99, 100 and record information in the selected register.

The CIP signal is generated at the computer interface by the OR element 61 and the bus driver 62, 45 from the output of which the CIP signal is fed to the computer interface. The computer, having received (the CIP signal from the device, removes the output signal, which ultimately leads to the removal of the recording signal generated by the decoder 74. Clearing the output signal provides the removal of the CIP signal generated by the element OR 61 and the bus driver 62.

Phase The output is terminated by removing 55 the BIA signal at the inputs-outputs 7 of the first communication unit 1. In this case, at the input of the installation, an active

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the level and the register 58 is reset to the zero state, providing a clearing of the enable signal at the input of the first element 60. This causes the logical zero to form the output of the 60 element, which causes the decoder 74 of the exchange unit 46 of the communication block 1 to be set to the neutral state .

Read operation. The second phase of the exchange cycle begins with the removal of the address from lines 9 and the signal input. Input from the computer interface via one of the circuits of the input-output group 7 through amplifiers 64 of block 45 of communication unit 1 to output 21 of control block 45 and further to the input of the second element AND 59 block 3 forming the operation code. From the output of the second element AND 59, the coincidence signal (input signal) and the recorded information from block 50 is fed to the input of the element OR 49 of the communication block 1, to one of the inputs of the element OR 61 and through the circuit 19 to the input of the element 75 of the exchange block 46 of the block 1 connection.

From the output of the element OR 49, the signal is fed to the input 56 of the block 46 of the exchange of the first block 1 of communication and ensures the formation at the output of the decoder 73 of the block 46 of the signal exchange, blocking the element AND 104. Next, the processes are similar to the Write operation, except that the code to the decoder 74 46 on the exchange unit 1 of the communication unit is fed together via the chains 19, 33, 31 and the decoder 74 of the exchange unit 46 of the communication unit 1 forms one of the output signals (read signals), opening one of the AND elements 106, 111, 107 and providing translation of the contents of the counter or one of the ISTRY 100, 99 on the group of exchange outputs input unit 46 9 1 communication unit and further to a computer interface 1.

Upon completion of the operation Enter / You-. water with registers and a counter of the exchange unit 46 of the communication unit 2, the microprogram automat of the communication unit 2 resets all previously generated signals (the end of the cycle execution) and is set to the state at which the outputs are generated at outputs 51, 53 At the output of the decoder 73 of the signal reset register 100, the command of block 46 of the communication unit 2 communication. Then the next command appears at the output of the MA, in which the output of the decoder 73 is a signal that blocks the elements 112 and opens the elements 103 to pass the code ope radios from the register of 100 commands of block 46 of interchange 1 of block of communication through chains 15 to the inputs of 16 elements 103 of block 46 of exchange block 2 of communication. Next, execution of the microprogram begins in accordance with the algorithm.

The execution of the microprogram begins with the analysis of the signals from the register 100 of the block 46 of the communication block 1 and representing the command code for the MA on the group of inputs 52 of the block 45 of the control of the communication block 2. When an exchange mode code is detected, one of the MA commands issues the following code from ROM 69:

outputs 51, 53, 44 — code for returning to the initial state (bidirectional exchange mode);

outputs 51, 53, 44 — code for returning-25. In this case, the contents of the register 99 of Danta to the initial state (unidirectional exchange mode);

output 40 is a high level signal to unblock inputs 31, 33, 19, 37 of communication unit 2.

The MA then performs the issuance from the ROM. 69 through amplifiers 65 through one of the I / O circuits 8 of the TFD signal, providing the requirement for access to the computer interface 2. The receipt of the confirmation signal from the computer 2 via one of the circuits of the input-output group 8 through the amplifiers 64 to the multiplexer 63 provides branching of the microprogram and setting at the output of the ROM 69 of the signal of the PV, coming through the amplifiers 65 to the computer interface 2. This signal is stored by the MA until the completion of the data transfer operations in (from) the computer memory.

The transfer of information to (from) the computer begins with the installation at outputs 5 53 of block 45 of block 2 of communication code entering the group of inputs 51 of block 46 of exchange block 2 of communication through an OR 49 element at input 56 of block 46 of block exchange 2 of communication and providing at the output of the decoder 73 of the exchange unit 46 of the communication unit 2 of the signal opening the AND 105 elements, and at the output of the decoder 74 of the communication unit 1 of the signal opening the AND elements 109 And the contents of the counter 98 of the address of the communication unit 1 are fed through

a group of inputs / outputs 30, And elements 105 of the exchange unit 46 of the communication unit 2 to the trunk 10, the address / data of the computer 2, and is interpreted by the computer as an address. Then, at the output of the ROM 69, a SIL signal is generated, which is fed through the amplifiers 65 to the inputs-outputs 8 to the computer interface 2.

After that, the MA, through multiplexer 63, analyzes the type of command on the input group 52 and proceeds to perform Input or Output operations. When a command is detected, the MA terminal at outputs 44 generates a code which, at the output of the decoder 74, removes the signal opening AND 109 elements and the output of the decoder 74 signal opening the element 108 and the signal increasing the content of the counter 98 address by circuit 36; element OR 47, element 48, circuit 54 of exchange unit 46 of communication unit 1.

The exchange unit 46 of the communication unit 1 enters through a group of input-output 30 through the element 105 of the exchange unit 46 of the communication unit 2 into the computer 2. At a time from the ROM 69 through the amplifiers 65, the inputs-outputs 8 and further into the computer 2 is output Signal output, then MA waits from computer 2 for confirmation signal CIP, which comes from computer 2 through one of the circuits through amplifiers 64 to multiplexer 63 .. When a signal is received, CIP MA removes from the output of ROM 69 the previously formed signal Output

Q to the outputs 8, and to the outputs 44 generates a code providing the output at the output of the decoder 74 of the exchange block 46 of the block 1 of the communication of the reset signal of the command register 100.

Then MA performs the analysis of the CIP signal coming from the computer interface 2, at the same time re-increasing the contents of counter 98 by 1. When resetting the signal in the computer interface

0 MA CIP clears all previously generated signals (end of cycle execution) and returns to the initial state. When an input command is detected at the inputs 52, the MA performs the output from the ROM through amplification.

five

Is 65 signal Input to the inputs-outputs 8 of the device. The receipt from the computer signal SIP on one of the circuits of the inputs-outputs 8 through amplifiers 64 to

multiplexer 63 means that the required information is supplied to the circuit 10, the MA generates on the output 69 of the ROM 69, at the outputs 51, - 53, 44 of the code that clears the signal that opens the AND 105 elements of the exchange unit 46 of the communication unit 2 and the appearance at the output of the decoder 73 of the block 46 of the exchange unit 2 of the signal communication opening the AND elements 104, as well as the appearance of the output of the decoder 74 of the block 46 of the exchange of the communication unit 1 of the signal opening the elements AND 93 and through the OR 91 element writing to the data register U9 of the block 46 of the exchange unit 1 communication information coming from the input Dov-10 O unit 2 through communication unit 104 and the elements of the exchange block 46 two communication inputs on block 30 1 bond. Further, the MA completes the execution of the Input operation in the same way as the completion of the Output operation. Simultaneously with the operation of the MA, information from the computer 1 can be recorded in the counter and registers of the exchange unit 46 of the communication unit 2 in the same way as described.

The computer 2 turns to computer 1 in a unidirectional mode after reading the command register, while on the computer main line 10 there is either the contents of the command register 100 of the communication block 1 of the communication unit 1, which is zero (when control signals come from the code generation unit 4 operations to communication unit 1), or Zanto bit from the output of the AND 80 element (when control signals are received from the operation code generation unit 4 to the communication unit 2). Bit Zan then comes from the output of the register 100 commands through the outputs 15 of the communication unit 1, through the inputs 16 and the AND element 103 of the exchange unit 46 of the communication unit 2.

The presence of a bit on the trunk determines the availability of information in the registers and the counter of communication unit 1 (busy). The presence of a null code on the trunk determines the ability to access the computer 1.

Claims (2)

1. A device for interfacing electronic computer numerical machines, containing two communication units and two operation code generation units, each communication unit containing a micron unit five 0 five program control, exchange unit, comparison unit and the first element OR, each exchange unit. contains two decoders, command register, data register, eleven groups of AND elements, three OR-NOT elements, and outputs of AND elements of the first, second and third groups and the first inputs of elements of the fourth, fifth and sixth groups of the exchange unit form respectively a group of outputs of the data address and a group of inputs of the address of the data of the exchange block, outputs of the elements of the fourth group and the first inputs of the elements And of the first group of the exchange block constitute Actually, the first group of information outputs and the first group of information inputs of the exchange unit, the outputs of the elements of the seventh, eighth and ninth groups and the first inputs of the elements of the tenth and eleventh groups of the exchange block form the second group of information outputs and the second group of information inputs of the exchange block, respectively. command registers are connected respectively to the first inputs of elements And the ninth group of the exchange unit and form the output group of the operation code of the exchange unit, the input group of the first and second decoder in the exchange unit, a group of code inputs and a third group of information inputs of the exchange unit are respectively formed; the synchronous input of the command register of the exchange unit is connected to the output of the first element OR of the exchange unit, and in each exchange unit the first input of the element OR of the exchange unit is connected to the first the output of the first decoder, the second inputs of the elements of the tenth group are connected to the first input of the second element OR NOT and to the second output of the first decoder, the third the output of which is connected to the second inputs of the elements of the eleventh group and the first input of the third element OR NOT, the output of which is connected to the synchronous input of the data register of the exchange unit, the information inputs of which are connected to the corresponding outputs of the elements of the sixth and eleventh groups of the ob0 block five 0 Namely, the second input of the third element OR is NOT connected to the first output of the second decoder, the first inputs of the elements AND the second group of the exchange unit are connected to the first inputs of the corresponding elements AND the eighth group, the second inputs of which are connected to the fourth output of the first decoder, the fifth output is connected to the first inputs of the elements And the seventh group of the exchange unit, the second inputs of which are connected to the corresponding outputs of the data register and the first inputs of the elements AND of the third group of the exchange unit, the second output of the second decrypt The rator is connected to the second inputs of the elements of the fourth group of the exchange unit, the sixth output of the front decoder is connected to the second inputs of the elements of the ninth group of the exchange unit, in which the command input / output of the microprogram control unit is respectively the command input-output of the block zi, the group of inputs for the data address and the group of outputs for the address of the data of the exchange unit are connected respectively to the first group of information outputs and the first group of information inputs of the communication unit, the first group of information The x inputs / outputs of the exchange unit are connected to the first group of inputs of the comparison unit and are respectively the second group of information inputs / outputs of the communication unit; the second group of inputs of the comparison unit is the group of information inputs of the communication unit, the first control input of which is connected to the first input the first OR element of the communication unit, the second input of which is connected to the first control output of the firmware control unit, the interface outputs, the outputs and inputs of which are respectively the outputs of the interface, the output a, the input of the communication unit, the output of the equality sign of which is the equality output of the comparison unit, the output of the first OR element of the communication unit is connected to the first reading input of the exchange unit, the second group of information inputs-outputs of which is the third group of information inputs-outputs of the block the second control input of which is the first control input of the exchange unit, the second control input of which is the third control input of the communication unit, the output group of the operation code of the connection exchange unit on with a group of inputs of the operation code of the microprogram control unit0 five 0 five The group of code outputs of which are connected to the group of code inputs of the exchange unit, wherein the command input-output of the first and second communication blocks form, respectively, the first and second groups of control inputs-outputs of the device, respectively, the information input groups of the first and second communication blocks The first and second address inputs of the device, respectively, the first groups of information inputs-outputs of the first and second communication blocks, respectively, form the first and second groups of address inputs-outputs device respectively, the third outputs of the first and second operation code generation unit are the first and second outputs of the device clock signals, respectively, the second groups of information inputs / outputs of the first communication unit are connected to the group of information inputs of the first formation unit of the operation code, to the fourth group of information inputs and the third group of information outputs of the second communication unit, the second groups of information inputs / outputs of which are connected to the group of information inputs of the second unit The operation code, with the third group of information input-outputs, the first communication unit, the equality outputs, the output-input interfaces, and the interface of the first and second communication blocks, are connected respectively to the information inputs of the output, input, and interface of the first and second operation code generation units, respectively, the first the control input of the first communication unit is connected to the second output of the first operation code generation unit and the read input of the second communication unit, the first control input of which is connected to the second output of the second power unit The code of the operation code and the read input of the first communication unit, the first write input of which is connected to the first output of the second operation code generation unit, the first write input of the second communication unit is connected to the first output of the first operation code generation unit, characterized in that increase device speed by eliminating addressing I 0 0 five 0 five and combining the operation of communication units, the device contains an element AND and an element NOT, each communication unit contains an element AND and a second element OR, each exchange unit contains an address counter, from the twelfth to the sixteenth group of elements AND, two elements NOT, nine elements SH and ten elements AND, and in the exchange unit the output groups of the elements And the fifteenth and sixteenth groups form the output group of the operation code of the exchange unit, the first group of inputs of the elements AND the sixteenth group are the group of balance inputs of the exchange unit, the first group moves the AND fifteen groups connected to the first group of input elements fourteenth group and the group of exchange outputs command block register is output decoupling group code Commands of the exchange unit, the information inputs of the command register are connected to the outputs of the corresponding elements of the 11th and thirteenth groups, the first inputs of which are connected from the output of elements of the fourteenth group to the inputs of elements of the sixth group, the first inputs of the elements of the twelfth group are connected to the first inputs and corresponding elements of the eleventh group, The first read input of the exchange unit is the first input of the third OR element of the exchange unit, the second input of which is connected to the first input of the first decoder of the exchange unit. , the output of the third element OR of the exchange unit is connected to the first input of the second decoder of the exchange unit, the third output of which is connected to the first input of the first element OR of the exchange unit, the second input of which is connected to the seventh output of the first decoder of the exchange unit, the eighth output of which is connected to the second inputs of the AND elements p of the group of the exchange unit and with the second input of the second element OR — NOT the exchange unit, the output of which is connected to the synchronization input of the counter address of the exchange unit, whose information inputs are connected to the outputs The appropriate elements of the group and n and the AND tenth group exchange unit, into- input unit increments exchange, a complementing input L exchange address counter unit, the outputs koto- ,, cerned connected to the first input five 0 five 0 five 0 five 0 five of the corresponding elements AND of the second group of the exchange unit, the second inputs of which are connected to the output of the second element OR of the exchange unit, the first input of which is connected to the fourth output of the second decoder of the exchange unit, the fifth output of which is connected to the first input of the fifth OR element of the exchange unit, the second input which is connected to the ninth output of the first decoder of the exchange unit, the tenth output of which is connected to the second input of the second element OR of the exchange unit, the output of the first element OR of the exchange unit is connected to the second inputs of the element ntov And the third group, the eleventh output of the first decoder of the exchange unit is connected to the third input of the third element OR NOT the exchange unit and the first input of the fourth OR element, the output of which is connected to the second inputs of the elements AND the sixth group of the exchange unit, the second input of the fourth element OR exchange unit connected to the first output of the second decoder of the exchange unit, the sixth output of which is connected to the first input of the third element And the exchange unit, the output of which is connected to one of the outputs in the output group of the data address of the exchange unit, the second input of the third element And the exchange unit is connected to one of the outputs of the output group of the operation code of the exchange unit, the second inputs of the elements And the fourteenth group of the exchange unit are connected to the twelfth output of the first decoder of the exchange unit, the thirteenth output of which is connected to the second inputs of the And elements of the twelfth group and the second input of the first element OR is NOT an exchange unit, the first input of which is connected to the second inputs of the elements of the thirteenth group, the second inputs of the elements of the first group are connected to the output of the tenth element nta AND of the exchange unit, the first input of which is connected to the sixth output of the second decoder of the exchange unit, the second input of the tenth element AND of the exchange unit is connected to the output of the second element of the NOT exchange unit, the input of which is connected to the seventh input of the first decoder of the exchange unit, the output of the fifth element OR the exchange unit is connected to the installation input in the instruction register register of the exchange unit whose output bits are the output group of the command code the exchange unit, the seventh output of the second decoder of the exchange unit is connected to the second inputs of the elements of the sixteenth group of the exchange unit and to the input of the first element of the exchange unit whose output is connected to the second inputs of elements of the fifteenth group, the second input of the first decoder of the exchange unit is connected to the output of - an OR element of the exchange unit, the first and second inputs of which are connected respectively to the outputs of the first and second elements AND, the first input of the last is the second input of the exchange unit, the third input of the cat The first one is the first input of the AND element, the second input of which is the second control input of the exchange unit and connected to the first inputs of the fifth, seventh and ninth AND elements of the exchange unit, the second input of the second element AND is the first control input exchange unit and connected to the first inputs of the fourth, sixth and eighth elements of the exchange unit, the first input of the exchange unit is the second input of the fourth element AND of the exchange unit, the output of which is connected to the first input of the seventh element OR, the output of which inen with the third input of the first decoder of the exchange unit, the fourth input of which is connected to the output of the eighth element OR, the first and second input of which is connected respectively to the outputs of the sixth and seventh elements of the exchange unit, the second input of which is the first control input of the second address the exchange unit, the second control input of the second address of which is the second input of the sixth element AND, the second input of the seventh element OR is connected to the output of the p - that element AND, the second input of which is the second input of the recording block exchange, the first control input of the first address of which is the second input of the eighth element AND of the exchange unit, the output of which is connected to the first input of the ninth element OR of the exchange unit, the second input of which is connected to the output of the ninth element of the exchange unit, the second input of which is the second control input of the first address of the exchange unit, the output of the ninth element OR of the exchange unit is connected to the fifth input of the first decoder of the exchange unit, and in each communication unit the output of the increment code of the exchange unit is connected to the first input element This AND communication unit, the second input of which is connected to the output of the second element OR communication unit, the first input of which is connected to the output of the increment of the microprogram control unit and is the output of the increment of the communication unit, the input of the increment of which is the second input of the second element OR of The output of the AND unit of the communication unit is connected to the increment input of the exchange unit, the first control input of the second address of which is the first control input of the second address of the communication unit, the second control input of the first address of which The second control input of the first address of the exchange unit, the third and second read inputs of which are connected to the first inputs of the first and second elements of the exchange unit, the second control input of the second address of the exchange unit is the second control input of the second address of the communication unit, the first control input of the first whose address is the first control input of the first address of the exchange unit, the first and second recording inputs of which are the first and second recording inputs of the communication unit, the second control input of which is the first a control input of the exchange unit, the second control input of which is the third control input of the communication unit whose inhibit input is the input of the inhibit of the microprogrammed control unit, the input I / o outputs, the interface and the mode of which are the input and output outputs interface and communication unit mode, the group of outputs of the control code of which is the group of outputs of the control code of the microprogram control unit, the second group of information inputs of the communication unit is the third group of information moves exchange unit, a first group of information inputs of which is a first group of information inputs to the communication unit, wherein the device outputs the first mode and the second communication units, respectively connected to first and second inputs of an AND device, whose output is connected to the input ele10 IS 20 271580385 NOT the device and with the second control inputs of the first and second communication units, the output of the second address of the first operation code generation unit is connected to the first control input of the second address of the first communication unit and the second control input of the second address of the second communication unit, first control input the first address of which is connected to the output of the first address of the first operation code generation unit and with the second control input of the first address of the first communication unit, the first recording entry of which is connected to the second recording input second communication unit, the first recording input of which is connected to the second recording input of the first communication unit, the first control input of the first address of which is connected to the output of the first address of the second generation unit of the operation code and the second control input of the first address of the second communication unit whose read input is connected with the second output of the second operation code generation unit and with the first control input of the first communication unit, the third control input of which is connected to the output of the element NOT and the third control input of the second Eu block, the inhibit input is co-connected to the inhibit output of the first communication unit, the inhibit input of which is connected to the inhibit output of the second communication unit, the input code group of the operation code of which is connected to the output group of the operation code of the first communication unit, the group of inputs of the operation code of which is connected to ". a group of outputs of the operation code of the second communication unit, the group of inputs of the control code of which is connected to the group of outputs of the control code of the first communication unit, the group of inputs of the control code of which is connected to the group of outputs of the control code of the second 25 thirty 35 40 45 S 0 85 five 0 five 0 five 28 the communication unit whose increment input is connected to the increment output of the first communication unit, the increment input of which is connected to the increment output of the second communication unit. 2. The device according to claim 1, wherein the operation code generation unit contains a control register, a delay element, an OR element, two AND elements and a bus driver, the first information input of the control register being the information input of the formation unit the operation code, the output of the first element AND is connected to the first input of the OR element and is the first output of the operation code generation block, the output of the second AND element is connected to the second input of the OR element and is the second output of the opera code generation block The first inputs of the first and second elements I are the output and input inputs of the operation code generation block, the output of the delay element is connected to the synchronous input of the control register, the installation input to O of which is connected to the input of the delay element and is the interface input of the code generation unit operation, the group of information inputs of the control register is a group of information inputs of the operation code generation unit, the output of the second address and the output of the first address of which are respectively the first and the second outputs of the control register, the third output of which is connected to the second inputs of the first and second elements AND of the operation code generation unit, the output of the OR element is connected to the input of the bus driver, the output of which is the third output of the operation code generation unit. 2№) 21 (22) 2 19 (20) ЪМ 37 (38) Fig.Z aw; "" garden Th / d5