SU1319042A1 - Device for controlling and exchanging data - Google Patents

Abstract

The invention relates to computing and can be used as a computational input-output system CHCTCbibi with distributed processing and distributed input-output data. The aim of the invention is to increase the reliability of the device due to the operative redistribution of input / output units. The device contains a firmware control block, a synchronization block, a matching block, a trunk block, a decoder, two multiplexers, a group of I / O blocks, two groups of switches, a group of external device address registers, an obmet control register, an initial register, two groups of K elements, element K. with 8 ill. 00 Mk o iCa N3

Description

113

The invention relates to computing and can be used as an input-output system for a computing system with distributed processing and distributed input-output data.

The purpose of the invention is to increase the reliability of the device due to the operative redistribution of I / O units in the process of data exchange.

The essence of the invention is to increase the reliability of the device by providing an operative redistribution of I / O units for WU and reducing the total amount of equipment. The volume of equipment is reduced by the amount of C (M – K) x X C (where Cgg is the volume of equipment of the I / O unit), i.e. the number of I / O blocks K in the device is less than the number of external devices M.

Figure 1 shows the functional diagram of the device; Fig. 2 is a functional block diagram of a firmware control unit; FIG. 3 is a functional diagram of a matching unit; figure 4 is a functional diagram of the block I / o; in FIG. 3 — the functional txe-ma of the synchronization unit; figure 6 is a flowchart of the algorithm for selecting and configuring an input / output unit; Fig. 7 is a block diagram of the service algorithm of the input-output unit; 8 is a timing diagram of the operation of the microprocessor processor unit.

The functional block diagram of matching and I / O blocks is shown when exchanging sixteen bit data words.

The device contains (Fig. 1) microprogram control unit (BMU) block 1, matching unit 2, a group of blocks 3.1-3. To I / O, block 4 synchronization, a group of registers 5.1-5. To addresses of external devices, register 6 controlling exchange, register 7 of the beginning of the exchange, the decoder 8, the first multiplexer 9, the second 10.1 - 10.K and the first 11.1 - 11.M switch groups, block 12 of the main elements, the first group of elements And 13.1 - 13.K, the second multiplexer 14, element And 15 , the second group of elements And 16.1- 16.K, outputs 17.1 - 17.K of the second group of elements And, the bus 18 data of the central percent row (CPU), an internal bus 19 data outputs of the first group vhodov- device 20, first 21.1

42 2

the second 21.2, the third 21.3 and the fourth 22 inputs of the device, the fifth input 23 of the device, a group of inputs 24 of the device, the second group of inputs-outputs

25 devices, the first, second and third outputs 26 of the device, the third group of outputs 27.1 to 27.M devices, the second group of outputs 28 of the device, the first group of outputs 29 of the device, output 30 of the block of main elements, the second group of inputs 31.1 to 31. To logical conditions BMU, the third group of outputs 32 BMU, the third group of information inputs and outputs

33 matching blocks, the fourth 34, fifth 35, sixth 36 groups of outputs of the BMU, the first 37.1 and the second 37.2 groups of information inputs and outputs of the matching block, the first 38.1, the second

38.2, the third 38.3 outputs of the synchronization unit, the second inputs 39.1 - 39. To the first group of elements And, the first inputs 40.1 - 40. To the second group of elements And, the group of outputs 41.1-41. To the decoder, the group of outputs 42.1 - 42. To the register of the beginning exchange, group of outputs 43.1–43. To the control register of the exchange, installation outputs 44.1–44. To the group's input-output unit, second information outputs 45.1–45. K, first information outputs 46.1–46. K, outputs 47.1–47, K service request, outputs

48.1- 48. To the direction of the exchange of blocks in the water-output group, the fifth input

49 logical conditions of the BMU, group of outputs 50 of the first multiplexer, output 51 of the element I.

At the same time, the inputs of the exchange requirement 21.1, the control word tag

21.2 and enabling direct access 21.3 of the group of inputs 21 for controlling the CPU of the device are connected respectively to the first, second, and third inputs of the logical conditions of the BMU 1.

BMU 1 (FIG. 2) contains an address generation unit 52, a multiplexer 53, an address counter 54, a register 55

microinstructions, fixed memory 56 (PP), elements And 57 and 58, outputs 59-63 of the address forming unit, outputs 64 - 68 G1.

The matching unit 2 (FIG. 3) contains the first 69.1 - 69.16, the second 70.1 - 70.16, the third 71.7 - 71.16 and the fourth 72.1 - 72.16 groups of trunk elements, the inputs and outputs 73 - 76 of the trunk elements.

The input-output unit 3 contains (FIG. 4) the control register 77, the register 78, the meter 79, the mode trigger 80, the trigger 81, the exchange direction (sign) trigger 82, the control trigger 83, the third element And 84, the eighth element And 85 , the sixth element And 86, the fourth element And 87, the fifth element And 88, the seventh element And 89, the element And 90 the tenth element And 91, the second element And 92, the first element And 93, the second element OR 94, the first element OR 95 , element NOT 96. In addition, unit 3 has the first 97.1, second 97.2, third 97.3 synchronization inputs of unit 3, first 98.1, second 98.2, third 98.3, fourth 98.4 inputs The group of control inputs of block 3, the first to sixteenth inputs 99.1–99.16 of the group of information inputs of block 3, the first to sixteenth outputs 100.1– 100.16 of the first information output of block 3, the output 101 of the register 77, the outputs 102.1, and 102.2 counter 79, first 103.1, second 103.2 outputs of the second information output 45 of block 3, output 104 of the element OR 94.

The synchronization unit 4 (FIG. 5) contains a trigger 105, a generator 106, and element 107 .. In addition, the first 108.1, the second 108.2, and the third 108.3 outputs of the generator 106 are indicated in the diagram (FIG. 5).

Consider the purpose of the elements, blocks and device connections.

EMU 1 (FIG. 2) is intended to control the operation of the device and generate micro-operation signals for interacting with the central processor and implementing the microprograms of information processing performed by the operation unit. Inputs 21.1, 21.2 and 21.3 of block 1 are used to receive signals, respectively: Exchange Requirement, Control Word Sign (CCP) and Direct Access Authorization (RID). The input 49 of block 1 is designed dp receiving the signal of the direction of exchange (sign) from the blocks

input-output (BVV). Inputs 31.1 - 31.К are designed to receive service request signals from blocks 3.1 - З.К, respectively. At the output 32 of the unit 1, micro-operations are formed which control the unit 2 of the matching. At the output 29 of the block, micro-operations are formed to control the RAM and the operating unit based on microprocessor sections, for example, the K1804BS1 set. At output 34, a BVB number code is issued. At the output 35, microoperations are formed that control the operation of multiplexer 9. At the output 36 of unit 1, microoperations are formed that control the operation of synchronization unit 4, blocks 3.1 - 3K, multiplexer 14. At output 28 of unit 1, microoperations are generated to interact with the CPU : Allow exchange, End of exchange, Preggs.

The address generation unit 52 (Fig. 2) is a combinational discrete device, the law of operation of which is uniquely determined by Table 1 of the correspondence. Table 1 defines the states of the inputs and outputs of the address generation unit 52 (where is the indifferent state of the corresponding device input. Tr. Vol. - signal Exchange request generated at the input 21.1 of unit 1. AC. Signal is a sign of the control input, arriving at input 21.2 of block 1. Routing. ND - sig nal Direct access enable generated at input 21.3 of block 1. R Z - logical condition signal Result symptom (Z) formed by the operating unit (microprocessor sections, for example, set K 804BC1 ), PP - three-digit micro-operatives uu signs transition kody.i names of which are given - us in Table 2, to MP - start address firmware service BU generated by requests from the input-output units.

And trans. - address transition formed at the output 67 PP 56.

- “000 O

 a- 000 1 t 000 about

As follows from Table 1, the address generation unit 52 operates as follows. When the micro-operation unit Microscope 52 has an impact on the end of the microprogram (code 000), zero signals are generated at the outputs of block 52.

If the exchange request signal arrives at the input of block 52, then at its control outputs 60–63, block 52 generates respectively 1,0,0,1, for which the code of the initial address of the exchange firmware from the input 30 of block 1 through the multiplexer 53 is recorded in the counter 54 .

If the inputs 31.1-31. To the block 52 receive a request from BVV.That at its output 59 the block 52 forms the code of the initial address of the service firmware i-ro WU, where, M, which is recorded into the counter 54 in the corresponding control signals. Signal exchange request has a higher priority. If the service request signal from the slave arrives at the moment the firmware is executed, this signal is not reproducible 1

is accepted before the end of the firmware.

When the CCP signal 52 arrives at the input of block 52, a single signal is generated at the output 62 of block 52, allowing the generation of the microcommand's execution address by increasing

the contents of the counter 54 per unit of clock pulse.

When the RID signal arrives at the input of the block 52, a single signal is generated at the output 62 of the block 52, allowing the generation of the execution address by increasing the content of the counter 54 by one.

Upon arrival at the inputs of the micro-operation unit 52 Analysis of the sign and the single signal at the input 49, the block 52 generates control signals at its outputs by which the transition address from the output 68 of the PI 56 through the multiplexer 53 is recorded into the counter 54. If the zero signal arrives at the input 49, then block 52 generates control signals that form the executive address

microinstructions by increasing the content of counter 54 by one.

When a microoperation unit 52 arrives at the inputs, a result and a single signal at input 22, block 52 generates control signals at its outputs for which the transition address A, ep from output 68 PP 56 through multiplexer 53 is written to counter 54. If the signal is zero to input 22, then block 52 generates control signals at the outputs that form the microcommand's executive address by incrementing the contents of counter 54 by one.

As a combinational device, the conditions of operation of which are unambiguously described by Table 1, the block 52 of the formation of the address can be most simply implemented on a programmable logic array.

Table 2

Microoperation

Code

Sign of the result

(Z) 100

Mark Analysis 011

End of firmware000

The multiplexer 53 (FIG. 2) is intended for switching the addresses of microinstructions from the input 30 of block 1, from the output 59 of the block 52 forming the address, and the output 68 of software 56. The multiplexer 53 realizes the logical function

 60 b1 61

where a 11 is the address at the output of multiplexer 53;

 - the address coming from the bus 18 CPU;

AJ is the address formed by block 53;

- the address coming from the output 68 PP 56; BV 61 control signals generated at outputs 60 and 61 of block 52, respectively.

The counter 54 (FIG. 2) is intended for storing, incrementing and issuing the address of the next microcommand. It has an input D parallel record of the address code, the counting input

B8

(+) and synchronization input C The address code received at input D is recorded in the counter, if a clock pulse is received at its synchronization input. The contents of the counter increase if the pulse arrives at its counting input (+1). The counter 54 operates in two modes. If the next address is formed by increasing

O per unit of the current address, the zero input signal comes from the output of the element And 58, and the next clock pulse from the output of the element to the counter's input 54 arrives at the synchronization input.

5 and 57. If the next address is formed by parallel writing the address code from input D, then a zero signal arrives at the counting input of counter 54; from the output of the element And 57, and the input |

0 synchronization - a clock pulse from the output of the element And 58.

The micro-command register 55 (FIG. 2) is intended for recording and temporary storage of micro-instructions readable from

 PP 56. At the output 55.1 of the register 55, micro-operations are formed that control the multiplexer 9. At the output 55.2 of the register 55, micro-operation signals are formed, intended for

0 control device operation. Output 55.3 produces the End of Exchange, Enable Exchange and Interrupt signals, designed to interact with the central process35.

The permanent memory is designed to store the firmware implemented by the device. At the input of the PCB 56, the micro address of the micro-co-operative address from the counter 54 output is given.

PP 56 is a static type memory block. At the output 64 of the PCB 56, micro-operations are formed, which are controlled by the block 2 of coordination. On

5, output 65 is provided by microoperations that control the operation of the operation unit on microprocessor sections, for example, the K1704BC1 series, the initial address counter, and the operational storage device (addresses of the RAM cells, circulation and recording signals).

At output 34 of block 1, an external device number code is generated. Signals 56 of the micro-operations are formed at the output 66 of the PCB 56; at the output of the 67 PCB 56 there are signals of the micro-operations of the transition signs, the codes and names of which are given in Table 2. At exit 68

91

PP 56 formed the addresses of the transitions when checking the logical conditions of the indication of the result (input 22 of block 1) and the direction of exchange (input 49 of block 1)

Consider the operation of the BMU 1. In the initial state, the counter 54 and the register 55 of the unit are in the zero state. From the output 67 of the PCB 56 to the input of the block 52 a micro-operation is received. The end of the microprogram, on the control outputs 60-63 of the block 52 there are zero signals. The operation of unit 1 begins with the arrival at its inputs 38.1 and 38.2. synchronization signals., respectively, T, and T (Fig.8). The clock pulse T ,, arriving at the inputs of the elements And 57 and 58, does not pass through the elements And, since the second inputs of the elements And receive zero signals. With the arrival at input 21.1 of block 1 of a signal. The exchange request at outputs 60–63 of block 52, respectively, generates single, zero and unit signals that allow the starting address of the exchange program from input 30 of block 1 to pass through multiplexer 53 and then write to counter 54 via a clock pulse. T. According to the clock pulse T in the register 55, the record is recorded in the first micro-command (1 MK) of the exchange microprogram (MP). At output 28 of block 1, a CPU signal is issued. Allowing the exchange of CPU causes the CCP signal to input 21.2, according to which a single signal is generated at output 62 of block 52, allowing passage of a clock pulse T, to the counter input of counter 54. The executive address of the second micro-command (2 MK) forms 1 by increasing the contents of counter 54 by one (+1). Microoperations are formed at the output 64 Ш1 56, allowing the passage of the data word from the input 20 of the device through the matching unit 2 to the input-output 25 of the device for subsequent writing to the RAM. In addition, at the output 65 of the PCB 56, the address, access and write signals of the RAM are formed. With the entry into the counter 54 of the address of the third micro-command (ZMK), at the output 67 of the PCB 56, a micro-operation Firmware End (MMP) is formed, and at the output 55.3 of the register 55 - the End of Exchange signal. With the arrival at input 31.1 of block 1 of the request from the first external device during the implementation of mik210

Exchange programs do not perceive this signal. After the formation of the microoperation of the CMP and the presence of the request at the outputs 60–63 of the block 52, the zero, single and single signals are formed, respectively, allowing the initial service microprogram address of the first slave (MO) to pass through the multiplexer 53 and then write to the counter 54 by a clock pulse T. Subsequent addresses of microinstructions of the service unit firmware are generated by increasing the content of the counter 54 by

unit (+1). The operation of the block ends after the termination of the arrival of the synchronization signals at the inputs 38.1 and 38.2 of block 1.

The matching unit 2 (FIG. 3) is intended for matching the operation of the device with the CPU when writing (reading) data to the operational memory of the CPU.

The first 69.1 - 69.16 and the second 70.1- 70.16 groups of trunk elements

serve to form an even data word when transmitting information from the CPU to the CPU, respectively. The third 71.1 - 71.16 and the fourth 72.1 - 72.16 groups of trunk elements are designed to form an odd data word when transmitting information from the CPU and to the CPU, respectively. The format of the danns CPU word is equal to two word data word formats.

At the input 32 of the matching unit 2 (Fig. 3), micro-operations are formed (at inputs 76.1 - 76.4) that control the passage of the data words. When transmitting an even data word from the CPU

the external device has a single signal at the input 76.1, and zero signals at the inputs 76.2 - 76.4. Controlling the transmission of data words through other groups of trunk elements is carried out in a similar manner.

Block 3 input / output (figure 4) is designed to control the remote and

receiving data words from external devices.

Control register 77 is designed to form the rate of exchange of bits of data words when receiving (transmitting) them from the slave. Registers 78 and 77 can operate in write and shift mode. If the control input of the registers receives a single signal, then

111

registers operate in write mode, otherwise - in shift mode.

I / O register 78 is designed to record data words that arrive in parallel code at input 19 of unit 3 from the CPU and issue them to WU with a serial code from output 100.16 of register 78. In addition, register 78 at input B records data words in serial code from the slave and output from the output of 46 CPUs in the parallel code.

The counter 79 (figure 4) is designed to record the code of the number of transmitted bits of the word when issuing and receiving it from the subscriber. The width of the counter 79 is determined by the output n togjN + l, where N is the number of register bits 78.

The mode trigger 80 is designed to control the operation of the trigger 81 and the register 77.

The mode trigger 81 is designed to control the mode of operation (write and shift) of the I / O register 78. The trigger 82 of the mark is designed for storing information about the direction of data exchange between the central processor and the slave. A control trigger 83 serves to control the output of bits of data words of a slave. Elements 84-93 are designed to generate signals that control the operation of the block. Element OR 94 serves to generate synchronization signals of register 78. Element OR 95 generates a signal to set to the initial (zero) state of counter 79. Element HE 96 is designed to generate a single signal, necessary dp autonomous formation of the rate of exchange of bits of data words.

The exchange control unit 6 operates in the mode of reading the data word of the TU and the mode of receiving information from the TU.

Mode vschachi Slovd data VU. In the initial state, the registers, triggers and the counter are in the initial (zero) state (the initial state setting chain is not shown in the functional diagram). The operation of block 3 begins with the arrival at input 41 of block 3 (Fig. 4) of the control signal from the output 41.1 of the decoder 8 (Fig. 1). At the same time, the groups of inputs 38 and 36 of block 3 receive the signals of synchronization and micro-operations that control

212

operation of block 3. Before issuing or receiving data words, the control unit always reads a control word (AC) containing information about the direction of data transmission. The DC enters the inputs 99.1–99.16 of the register 78 and is written into it on the falling edge of the pulse pulse T1. Information about the direction of data transmission (zero or

unit) from the input 99.16 of the register 78 is recorded by the clock pulse T 5. The resolution signals for the passage of the clock pulse T through the elements 85 and 91 are microoperations coming from the inputs 98.3 and 98.2, respectively.

After that, the clock pulse T, to the input 17 of block 3 receives a single signal, which sets

the triggers 80 and 83 to single states, as well as passage through the element of the rysh 95, confirm the initial (zero) state of the counter 79. A single signal from the output of the trigger 80 transfers the trigger 81 to the single state and sets the register 78 in the shift mode previously recorded by CSS.

By a clock pulse T, the register 77 is written to the head one unit from the output of the element NOT 96. The unit is transferred to the upper bits of the register 77 by the next clock pulse T after the trigger 80 is set to the initial (zero) state.

On the second clock pulse Tz. trigger 80 is reset to its original (zero) state.

When writing a unit to the high-order register of register 77, at the next clock pulse T2, a single signal from the output 101 of the register 77 arrives at the input of the element And 89 and at the next clock pulse T at the output 103.1.

In addition, a single signal from the output of the element And 89 through the element OR 94 is fed to the synchronization input of the register 78 and shifts the recorded US. Information signal with

output 100.16 of the register 78 through the element And 93 enters the output 103.2. A single signal from the output of the element And 89 also goes to the counting input of the counter 79, which carries out

count the number of transmitted data word bits.

A single signal from the output 101 of the register 77, the passage through the element

1313

and 88, according to the clock pulse T, arrives at the single input of the trigger 80, the latter being transferred to the single state. A single signal from the output of the trigger 80 allows the unit to be written to the low-order bit of the register 77 from the output of the HE 96 element. Block 3 is ready for the next bit of the data word. The output of the next bits from the output of 100.16 is similar.

When the last bit of the data word is output from register 78, a single signal 102 appears at the single output 102 of the counter 79, which arrives at the output 47 of block 3, signaling the end of the control word output to the subscriber. In addition, the unit signal from unit output 102 of the counter

79 according to the clock pulse T, passes through the element 87 and triggers the trigger 81 to the initial (zero) state, as well as through the element 92 of the control trigger 83.

The signal of the end of the exchange of the word to the output 47 of the block 3 signals that the data word is issued to the control unit and the block 3 is ready for recording and issuing the next word.

After the control word is transmitted, the data words, the so-called information words (IS), are transmitted. Recording and output of the IC has some special features. When writing an IC on a clock pulse Tj at the input 98.2, there is no micro-operation that controls the recording of the sign in the trigger 82.

According to the clock pulse T, at the input 98.1 there is a micro-operation, transferring through the element 84 and the trigger

80 in one state, as well as through the OR element 95, which sets the counter 79 to the initial state. Subsequently, the recording of the IC to the register 78 and the transfer of its CU occurs in the same way as the recording and the CU of the control word. After all the words have been transmitted, the micro-operation arrives at the input 98.4. The end of the group exchange, which passes through the element OR 95, sets the counter 79 to the initial (zero) condition.

The mode of receiving information from an external device. In this mode of operation, unit 3 enters after issuing the control word to the WU, which sets the WU to receive information on the output 43 of the exchange control unit 6.

214

A micro-operation is fed to the input 98.1, which, by a clock pulse T, sets the mode trigger 80 to one state. The signal from the output of the trigger 80 sets the trigger 81 to one state. Zero signal--: nal from the exit of the trigger 81 allows the recording of information (data word bits) received at the input of the register 78 s

input 43. The frequency (rate) of reception of bits is carried out by block 3 in the same way as the frequency of data word bits by shifting the unit in register 77. When a unit appears in (N-l) -M

the output of the register 77 is a single signal from this output on the contact pulse T, passes through the element 86 at the output 44 of the block 3.

By the next clock pulse

A T unit appears at the N-M output 101 of the register 77 and, via the clock pulse T, through the element And 89 enters output 103.1, synchronizing the arrival of the word bit from the VU to the input

43 block 3. At the same time a single signal from the output of the element And 89 is fed to the counting input of the counter 79 and through the element OR 94 to the synchronization input of the register 78. As a result

an information bit (zero or one) is written to the low-order bit of register 78 from input 43 of block 3.

Receiving the subsequent bits of the data word is similar. The bits of the word are sequentially written to the low-order bit of register 78 from input 43 of block 3, and the previously recorded bits are shifted to higher bits of register 78 until a single signal arrives at output 47 on the single output 102 of counter 79. block 3.

Receipt of the following ICs occurs in a similar way. When receiving the last IC in the array of information words, input 98.4 receives a microoperation of the end of group exchange, which, passing through the elements AND 90 and OR 95, sets the counter 79

to the initial (zero) state, preparing it for further work. The synchronization unit 4 (Fig. 5) is intended to form at its outputs 108.1 - 108.3 three sequences of clock pulses shifted relative to each other, which provide synchronization of the device operation.

The trigger 105 serves to control the operation of the synchronization unit 4. In the initial state, the trigger 105 is in the zero state. In this case, the zero signal from its output enters the control input of the generator 106.

The generator 106 at its outputs generates a sequence of pulses only if there is a single signal at its control input. Element AND 107 is used to form a signal at the zero input of the trigger 105 after the arrival of the control signal. End of operation from input 36.1 of block 4.

The synchronization unit 4 is triggered by the Start signal, which is fed to the input 23. It is applied to the single input of the trigger 105 and sets it to the single state. With a single signal at its output, the trigger 105 starts the generator 106, which begins the formation of sequences of clock signals, the formation of clock signals for transmitting (receiving) thirty-two times, continues for as long as the first data words. Bit 0-15 bus- element input 107 not received 18 data packs serve dp transmission

Equal Signal End of Work. After that, when the next pulse pulse from output 108.3 arrives at the second input element 107, a control signal is generated at the zero input of the trigger 105, which returns to its initial state and removes the control signal from the generator input 106. As a result, the generator 106 Stops sequence of clock pulses.

Register 5 of the address of the external device is intended for recording and temporary storage of the address of the slave with which the data is exchanged.

Control register 6 is designed to control the operation of the device when receiving information from external devices.

Register 7 of the beginning of the exchange is used to form the signals of the beginning of the exchange of data by an external device.

the initial addresses of the exchange programs. The bits 16–31 serve for

30 information is transmitted through block 2 of matching to the input-output 25 of the device for subsequent writing to RAM. The internal data bus 19 is designed to transmit sixteen35 bit data words.

The device works as follows.

In the initial state, all device registers are in the zero state.

40 nii. The operation of the device begins with the arrival of the start signal to the input 23 of the device. As a result, synchronization unit 4 begins to form at the output 38 three sequences of clock pulses shifted relative to each other.

With the arrival at device 21 (input 21.1) of signal 1, the exchange requirement from the CPU to output 28 of the descrambler 8 is designed to issue control signals at its outputs to write the addresses of the slave in registers 5.1-5. To the address of the slave and control the blocks of exchange control .

Multiplexer 9 is designed to control the passage of data words from exchange control blocks to the central processor.

Switch 10 is designed to - receive and switch information signals from the slave, depending on the address of the slave.

The switch 11 serves to switch and transmit the information of the slave depending on the address of the slave.

The block 12 of trunk elements is designed to form the initial address of the exchange microprogram, arriving t of the CPU bus 18.

Elements And 13.1 - 13.K serve dp forming the synchronization signals of registers 5.1 - 5.K, respectively.

The exchange direction multiplexer 14 is designed to select information from the exchange control units about the direction of data transmission between the CPU and the slave.

Elements 15-17 are intended to form control signals during the selection and adjustment of I / O blocks.

The data bus 18 of the CPU serves for the penal addresses of the exchange microprograms. The bits 16–31 serve for

30 information is transmitted through block 2 of matching to the input-output 25 of the device for subsequent writing to RAM. The internal data bus 19 is designed to transmit sixteen35 bit data words.

The device works as follows.

In the initial state, all the registers of the device are in the zero state. The operation of the device begins with the arrival of the start signal to the device input 23. As a result, synchronization unit 4 begins to form at the output 38 three sequences of clock pulses shifted relative to each other.

With the arrival from the device input 21 (input 21.1) of the signal 1 block The exchange request from the CPU to the output 28 of the device is given the exchange enable signal. Signal CPU Resolution

the exchange gives to the input 21 of the device (input 21.2) of block 1, the CCP signal, according to which at output 32 of the BMU 1 a micro-operation is formed, which enters the input of the matching block 2 and allows the information (the starting address of the RAM of the CPU) to pass through input 37.1 through block 2 matching, input-output 33 of unit 2 to input-output 25 of the device for subsequent recording into the buffer zone of the RAM. At the same time, at the output 29 of the device, microoperations are formed for recording information into the buffer zone of the RAM by a clock pulse T, for example, in cell A ,. In the next cycle of operation of the device, a clock pulse Tj at the device output 28 is formed. A microoperation is generated. The end of the exchange signaling the CPU that the data exchange is complete. Likewise, length information is passed from device input 20 to device input / output 25; an array of control words and constants 1 to the buffer zone of the RAM, for example, cells A, A, and A; respectively.

After the initial address (ON), array length (DM) and unit are written into the RAM buffer zone, the external device address is recorded in the A buffer zone of the RAM buffer zone, however, the formation of the KMP microoperation at the output 67 of the PC 56 of the firmware control unit 1 does not

L

proceeds, and the formation of micro-operations is performed at the output 29 of the device according to the implementation of the selection and setup microprogram of the I / O unit (Fig. 6). A microcooperative CML does not form at the same time as a microoperation. Microoperations are formed at the output 29 of the device, which carry out logical multiplication (Fig. 6, symbol 7) of the Ag cell contents onto the content of the A cell. At the same time, the signal of the logical condition value arrives at the device input 22 Sign of the result (zero or one). Units are recorded in the bits of cell A, if the corresponding I / O unit is occupied by servicing an external device. If the logical multiplication operation does not produce a signal of the result feature, the zero signal is received at the input 22 and the next microcommand shifts the unit to the higher bits of the busy sign cell of the I / O unit (Fig. 6, symbols 12, 13, 18, 19) . Thus, the selection of a certain value in the BWV 3.1 is performed via a clock I / O unit for the exchange of a pulse Te. By clock pulse

external

array of data words with external device, property. If all are busy

T l at the output 36.2 of block 1 is formed a microoperation, which, according to the tact with fO

f5

20

25

I / O blocks at the output 28 of the device, an interrupt signal is generated to the central processor, and at output 67 PP 56 (Fig. 2) is generated. - (microcooler KMP (Fig. 6, symbol 24). If a logical multiplication operation produces a single signal of the logical condition at input 22 of the device, the initial address of the array of data words of the RAM of the CPU and the array length counter from cells A and Aj of the buffer zone of the RAM into cells A {and A of the RAM of the i-ro I / O unit, where K ( 6, symbols 8, 14, 20.) After that, the clock pulse T is produced in The selected external device from the device input / output 23 to the registrar 5. Suppose that the first I / O unit is selected.According to the clock pulse T, the output 34 of the unit 1 generates the code of the external device number for which the output 41.1 of the decoder 8 This is a single signal that is input to an AND 1 3 element.

At the output 33 of block 1, micro-operations of address and addresses of the AJ cell are formed, according to which the address code

 external device enters the input-output 25 of the device. The clock pulse T, j at the output of the element And 13.1 generates a signal for register register synchronization 5.1, through which the recording of the address of the external device from input-output 25 of the device to register 5.1 proceeds. After that, at the device input 29, microoperations are formed that record the result of the logical multiplication of the contents of the cells Ag and A (Fig. 6, symbols 7, 13, 19), previously placed in the general purpose register (RON) of the operation unit, into the cell Ag of the buffer zone Ram

45 (FIG. 6, symbols 10, 16, 22).

Further, the control word is written from the RAM cell from the input-output 25 of the device to the BVV 3.1. For this purpose, micro-operations signals from output 36 of block 1, synchronization signals from output 38 of the synchronization block 4. and a control signal from output 41.1 of the decoder 8 are sent to the input of block 3.1. Recording of the control layer 40

At the output 36.2 of block 1, a microoperation is formed, which is formed by microoperations at the clock, checking the array length counter to zero. In the case of transferring all words to an external device, the microoperation is formed at the output 36 of block 1, transferring the input / output unit 3 to 7 (Fig.7,

19131904220

The main impulse T arrives through an elementary memory (SP) to an external device AND 15 and 16, at the single input of the woo (Fig. 7, symbols 3,4). At exit 29, register 7 start the exchange. At the output 42.1 of the register 7, a single signal is generated, which arrives at the input of the switch 11.1 and passes to the output 27.1 of the device, signaling the control unit that the exchange has started. The decoding signal dp for passing information through the switch 11.1 is a single signal symbol 5). After that, at the output of the output at the register 5.1, since 29 devices are formed by microopes, in the register 5.1 the code of the radio address is recorded, eliminating the first external device. By the sign of the employment of the BWV 3.1, by means of the to-do impulse Tz, the unit is crossed out from the corresponding register 7 to the initial (zero) 5th bit of the Ag cell. On the output state. Thus, the device is micro-paged to select and adjust the Interrupt unit, and to the I / O output. In the future, the I / O unit 67 W1 56 of the block 1 is a microcooperative microprocessor (KMP). 7, symbol 6). data words to the external device. At 20 output 67 of the PCB 56 of the block 1 (Fig. 2), a micro-operation KMP is formed. The device goes into standby mode for the next request from the CPU at the choice and tuning. If not all data words are transmitted to the VU, Micro-ops are formed at the output 29 of the device, recording the initial address of the data word array from the cell

next BVV to the autonomous output - 25 A, to the counter of the starting address and the data word form to the external arrangement of the Requirement signal for the rest. If it turns out that all BVV is of rare access. The device is on, then, at the output 28 of the device, the interrupt signal is centralized to the idle mode, allowing the direct access to the processor, and the output 67 of the PCB 56 30 pa from the CPU (Fig. 7, symbols 7-10). Block 1, a micro-optic CMP is formed (Fig. 6, symbol 24).

After issuing the data of the BVV 3.1-H.K data at the outputs 47.1–47. Single signals are generated that pass the data word from the TynajoT input to the inputs 31.1-20 of the device through block 2 according to 31. To the BMU 1. These signals occur asynchronously with respect to the CPU and each other. At the same time, several signals can be generated. BMU 1 sets the priority between requests from exchange control blocks such that at any one time only one service request is processed.

Upon receipt at the input 31.1 of the BMU 1 application from block 3.1, the implementation of the service firmware begins

first external device. Algo- (The operation of the device during the rhythm of servicing an external device for recording data from an external device is shown in Fig. 7. At output 36.3 in the CPU OP is performed as follows OBMAT I are formed by microoperations, in turn. The data word from the slave enters the signal is in the serial code to the input 24 ka (exchange direction) to the device input 49. The address code of the external unit is 1. If the input 49 of the unit 1 of the device (for example, the first slave) has a zero signal, then is sent to register 5 for the whole time pe- data corresponds to group communication, so the output soap has an array of data words from the register 5.1 is present operational unit

Upon the arrival of a signal. Direct access permission to input 21.3 of block 1 at output 32 of block 1 are formed by micro-operations, permitting data bus 19 to input of input 1.3 of I / O. At the output 41.1 of the decoder 8 and the output 34 of the block 1 for40, the microoperations are peacefully settled, and the data words and the launch of the block 3.1 for autonomous operation exist (Fig.7, symbol 11). Further, at the exit 29, micro-operations are formed,

45 carried out a modification of the array length counters, the starting address and their subsequent entry, respectively, into cells A and A, RAM.

the devices are formed by micro-operations that check the array length counter to zero. In the case of transferring all the words to an external device at the output 36 of block 1, a micro-operation is formed, translating the input-output unit 3 to the initial state (Fig.7,

memory (SP) to an external device (Fig. 7, symbols 3,4). Output 29 symbol 5). After that, at the output 29 of the device, micro oper- ations are formed, which eliminate the sign of the employment of the BWV 3.1 by deleting a unit from the corresponding discharge of the Ag cell. On the device output 28, a micro-operation is interrupted, and at the output 67 Ш1 56 of block 1 - a micro-operation KMP (Fig. 7, symbol 6).

memory (SP) to an external device (Fig. 7, symbols 3,4). Output 29 symbol 5). After that, at the output 29 of the device, micro oper- ations are formed, which eliminate the sign of the employment of the BWV 3.1 by deleting a unit from the corresponding discharge of the Ag cell. On the device output 28, a micro-operation is interrupted, and at the output 67 Ш1 56 of block 1 - a micro-operation KMP (Fig. 7, symbol 6).

If not all data words are transmitted by a VU, then micro-ops are formed at the output 29 of the device, recording the initial address of the array of data words from the cell

A, in the counter of the starting address and the formation of the signal Requirement of direct access. The device enters the signal standby mode. Direct access from the CPU (Fig. 7, symbols 7-10).

The passage of the data word from the input 20 of the device through block 2

When a signal arrives Allowing direct access to input 21.3 of block 1 at output 32 of block 1, micro-operations are formed that allow the passage of the data word from input 20 of the device through block 2 according to

vani, bus 19 data to the input unit 1.3 I / o. At the output 41.1 of the decoder 8 and the output 34 of the block 1, micro-operations form, about the data words that exist in the recording and the start of the block 3.1 for autonomous operation (FIG. 7, symbol 11). Further, at the exit 29, micro-operations are formed,

carried out a modification of the array length counters, the starting address and their subsequent recording, respectively, in cells A and A, RAM.

control signal that permits the passage of data word bits (zeros or ones) to a single setup input of register 6 (through a switch 10.1) and the subsequent passage of information to the input of a block 3.1. The autonomous reception of data word bits by block 3.1 is accompanied by the release of synchronization signals from output 45.1 through switch 11.1 to output 27.1 of the device. At the same time, before receiving the bits of the word from output 44.1 of block 3.1, a single control signal arrives at the zero setting input of register 6, preparing register 6 for receiving information.

Consider the operation of the device receiving the data word (Fig.7). Block 3.1 issues a request for service to input 31 of block 1. A single sign signal (data transfer direction) through multiplexer 14 is fed to input 49 of unit 1. A single signal at input 49 corresponds to a data record in the CPU CPU. After determining the direction of data transmission, the counter of the array of data words is checked (Fig. 7, symbol 1 IF not all data words are transferred from the slave), then the initial address of the array of data words from the cell OC is written to the counter of the initial address and the signal is generated. direct access. For this purpose, the corresponding microoperations are formed at the output 29. The device enters the standby mode of the REED signal (Fig. 7, symbols 14-17).

When the signal arrives at the input 21.3 of block 1 from the CPU, at the outputs 32 and 35 of block 1 micro-operations are formed that allow the passage of the data word from block 3.1 through multiplexer 9 and block 2 of matching to the output 20 of the device. In addition, at the output 36 of the block 1 of the forms, micro-operations are being carried out. Carrying out the launch of block 3.1 for the subsequent autonomous reception of the next data word from the control unit (Fig. 7, symbol 18). After starting block 3.1, microoperations are formed at the output 29 of the device, modifying the initial address and array length counters.

If all data words from WU are transmitted by the CPU, then the last word danns from block 3.1 is transmitted in the same way via multiplexer 9, matching unit 2 to the device output 20 and bringing the input unit back to its initial state (Fig.7, characters 20-23). After this, an exception is made to the sign of the occupation of the corresponding I / O block, micro-operations Interrupt and End of Microprogram are formed (Fig. 7, symbols 23,24).

The selection and configuration of other I / O units is done in a similar way.

The operation of the device stops with the arrival at the input of the micro-operation synchronization unit 4 from the output 36.1 of the BMU

Claims (1)

Invention Formula A device for controlling and exchanging data containing a firmware control block, a matching block, a trunk block, a synchronization block, a decoder, an exchange control register, two multiplexers, a group of I / O blocks, an And element, the first and second groups of information inputs and outputs of the block matching form a group of inputs and outputs of the device dp connection to the group of information inputs-outputs of the central processor of the computer, the third group of information inputs-outputs of the block matching connection en with groups of information inputs of input-output units of the group, with a group of information outputs of the first multiplexer and forms a group of inputs and outputs of the device for connecting to the RAM and computer, the first, second, third, fourth inputs of the logic conditions of the firmware control block are the inputs of the device to connect to the outputs of the exchange requirement, control-word sign, direct access permission and logical condition of the central computer processor, respectively, the first and second groups you The firmware control unit moves are the device output groups for connecting to the group of control inputs of the main memory of the computer and the group of control inputs of the central processor of the computer, respectively, the start input and the first, second, third outputs of the synchronization unit 231 are input and output devices for connecting to the start output and to the first, second, and third synchronous inputs of the central computer processor, while the third group of outputs of the firmware control block is connected to the group of enabling inputs of the matching block, the second group of information inputs / outputs of which connected to the group of information inputs of the block of trunk elements, the group of information-1CHONNYh outputs of which is connected to the first group of inputs of the logic conditions of the microprogram control unit, in An ora of a group of inputs of logical conditions of which are connected to service request codes of I / O blocks of a group whose outputs of the exchange direction are connected to a group of information inputs of a second multiplexer whose output is connected to the fifth input of a logical condition of a microprogrammed control unit, the fourth group of outputs of which is connected to a group of inputs the decoder, a group of outputs of which is connected to the inputs of a sample of blocks of input-output groups, the first, second and third synchronous inputs of which are connected to the first, W eye, the third output of the synchronization unit, respectively, the first output of which is connected to the first input of the element And and the first synchronous input of the microprogramming unit, the second synchronization input of which is connected to the second output of the synchronization unit. The first group of alignment inputs of the exchange control register is connected to the installation the outputs of the input-output units of the group, the first information outputs of which are connected to the group of information inputs of the first multiplexer, the group of control inputs of which are connected to a group of the microprogram control unit outputs a pole group which output is connected to the second input of the AND gate, a control input sync block, to the control input of the second multiplexer, with the input-output units enabling input group information inputs 904224 which are connected to the group of outputs of the exchange control register, permitting the input of the block of trunk elements is connected to the zero potential bus of the device, characterized in that, in order to increase reliability due to the operative redistribution of input-output blocks, a group of registers is entered into it 0 addresses of external devices, two groups of switches, register of the beginning of exchange, two groups of elements AND, and the information outputs of the switches of the first group form a group of device outputs for connection to the information inputs of external devices of the group, the information inputs of the switches of the second group form a group of device inputs for connecting to the information outputs of the external devices of the group, the information inputs of the external device address registers are connected to the input-output group of the device for connection to 5 main memory of the computer, while the group of outputs of the decoder is connected to the first inputs of the elements of the first and second groups, the second inputs of which are connected to the second outputs of the synchronization block 0 and the element And, respectively, the outputs of the elements of the first group are connected to the synchronous inputs of the external device address registers , groups of outputs of which are connected to control inputs of switches of the first and second groups, information outputs of switches of the second group are connected to the second group of installation inputs 0 of the exchange control register, the third output of the synchronization unit is connected to the first group of setup inputs of the exchange start register, the second group of setup inputs is connected to 5 outputs of elements of the second group and with the installation inputs of the group I / O units, the second information outputs of the group I / O units and the corresponding bits of the informational output group of the register of the beginning of the exchange are connected to the corresponding bits of the information | the inputs of the switches of the first group. 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