SU1464157A1 - Device for unpacking commands - Google Patents

Abstract

The invention relates to computing and can be used to decompress command information in a high-speed computer processor. The purpose of the invention is to increase the speed by simultaneously processing several commands. The unpacking device contains buffer registers of 1-3 commands, register of 4 command numbers, block 5 of the sample start indicators, block 6 of memory, block 7 of multiplexers, AND 8, group of 9 elements OR, D-flip-flop 0, group of 11 elements I. 1 hp f ply, 1 tab.

Description

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kj

The invention relates to computing and can be used to unpack command information in a high-speed computer processor, in particular in a processor that allows parallel execution of several consecutive commands.

The purpose of the invention is to increase the speed of communication by simultaneously unpacking several commands.

Fig. 1 shows a block diagram of a device for unpacking commands (all functional block diagrams for a memory bus width equal to a double word, i.e. four half words) t in Fig. 2 is a functional block diagram of the sample start pointers; FIG. 3 shows a functional block multiplexer circuit (for one bit of each half-word); figure 4 is a functional diagram of a group of elements OR; fig.Z - functional diagram of the group of elements I.

The device for unpacking commands (FIG. 1) contains the first 1, second 2 and third 3 command buffer registers, command attribute register 4, block 5 of the sample start indicators, block 6 lam, block 7 multiplexers, element 8, group 9 elements U, D-flip-flop 10, group 11 elements I, input 12 high-order device code codes, input 13 reset device-to, input 14 numbers of device commands (command reception signals to processor processing devices) input 15 enable command commands va, input 16 device sync input 17 low order code device commands, cutting device unpacking input 18, device command code output 19, device command forging output 20, device command forging output 21, output 5 of block 5, outputs 22 and 23 of block 3, outputs 24-26 of block 2, output 27 of the And 8 elements, outputs 28-30 of memory block 6, output 31 of block 7, code 32 of block 9, output 33 of block 4, output 34 of block 11 and output 35 of D-flip-flop 10,

The block 5 of the indicators of the beginning of the sampling (FIG. 2) contains a register 36, an encoder 37 implemented on a group of 38 And elements containing AND 39-45 "elements from the first to seventh and an OR 46 element. Multiplexer block 7 (Fig.З) contains elements AND-OR 47-

about

5 0 5

0 p -

five

52 and elements And 53-55. Group 9 of the elements OR (Fig.4) contains the elements OR 56.1-56.4. The group 11 of the elements And (figure 5) contains the elements And 57.1 57.4.

In the description of the operation of the device, the following designations are used: RR is a format of commands of one half word; RX, RS, SI, S and RRE - a format of commands of two half words in length; SS, SSE - a format of commands of three half words.

Commands in the memory must be located on the border of the half-word (or even byte), so when addressing the command, the value of the least significant (31st) bit of the command address is always zero, and this bit is not considered further. At the beginning of a new program branch (after a successful transition, change of processor state, or initial program load) 30, 29, ..., the 30th address bit indicate the number of the half-word from which the first command of the new program branch begins,

Two senior bits to each command (0th and 1st) define its format. So, if in the 0th and 1st bits of the co-. Manda contains code 00, the command consists of one half-word, with codes 01. or 10 - of two half-words, with code 11 - of three half-words.

If the information bus width is equal to n half words, it can contain from n / 3 to n commands, while in the junior half word or the younger two half words (and at the beginning of the program branch, when the address indicates these half words) not the full commands, but only the beginning of the next command, but the continuation of this command comes with a new reading from the memory,

The unpacking of commands is organized in such a way that from the command information 1 received in the second buffer register of 2 commands, only all full commands are always entered in the first buffer register 1 of commands, regardless of their formats, and the lower two half words are mc in the third buffer .register 3 teams. They will participate in unpacking the next block of information received from the memory (if there is an incomplete command in the previous block, i.e., a remnant). The first buffer register 1 command contains Zp-3

half words (where n is the size of the information memory bus in half words), which are distributed by command as follows; the first n - 2 teams contain three half words each, n - 1 command contains two half words, and π command contains one half word. In this case, regardless of the format of the -i command, three consecutive half-words are written in place of the first n - 2 commands, and in the place of the first command, two consecutive half words are used. However, the processing devices use only the number of bits defined by the opcode, which is always written to the place of the high byte of the high half-word. The second buffer register of 2 commands contains n half words and corresponds to the size of the information memory bus. The third buffer register of 3 commands contains two half-words and corresponds to the maximum possible remainder in the previous unpacking.

Block 5 of the sample start pointers generates features indicating from which half-word the command information begins in a given device operation cycle. If the sign of the beginning of a branch has been entered in the previous cycle, then the command information can start from 1, 2 ,, .., the n-th half-word from the second buffer register of 2 commands in accordance with the value of the least significant bits of the half-word address. If the sign of the beginning of a branch is not received in the previous clock cycle, then the command information may start from the first or second half word of the third buffer register 3 commands (remainder register) or from the first half word of the second buffer register 2 commands in accordance with the memory generated in the previous clock in block 6 address code

The signs generated by the block 5 of the sample start indicators, as well as the upper two bits from each half-word from the third 3 and second 2 buffer command registers (outputs 22 and 24), go to memory block 6, which is a programmable logic array and produces three control groups signals.

The group of control signals, coming from the output 29 to the block 7 of the multiplexers, indicates from which half-word each command begins and controls the recording of information half-words from buffer registers 2 and 3

0

five

0

five

0

five

0

five

0

five

teams in the corresponding half-word buffer register 1 teams. The address code is a sign of the remainder and enters from output 28 in block 5 of the sample start indicators. The control signal group coming from output 30 indicates the presence of 1,2 ,,,,, nth commands in this block of co-ordinated information and serves as information inputs for register triggers 4 command numbers when there is a high level at the first input of the group elements And (vrsod 35 D-flip-flop 10),

The operation of the device consider the example of fetching command information when processing a certain sequence of commands.

Suppose that the information bus width is equal to four half words (64 bits), then the first buffer register 1 of the commands must contain nine half words (three half words for the first and second commands, two half words for the third command and one half word for the fourth command ), the register of 4 numbers of commands must contain four triggers, the group of 9 HTOd elements must consist of four elements OR, the group of 11 elements And must consist of four elements AND, the element 8 must be six input, and the input 17 of block 5 must go The 30th and 29th bits of the address. Let a new program branch be processed containing commands of the formats RR, RX, SS, RS, RR, SS, RR, RR, RR, ,,., With the 29th and 30th bits being in the O and 1 state, respectively. The location of the command information is presented in the table, I

Immediately after determining the need to move to a new branch of the program, processor processing devices generate a Reset signal, according to which D-flip-flop 10 has valid information in the buffer registers 2 and 3 of the commands set to O, and all signs of pre-unpacked are reset in register 4 teams. Thus, at the And 8 element, the formation of a permitting pulse at the output 27 is prepared for receiving the command information block of the new program branch into the buffer register 2, and the zero output state of 35 V-flip-flop.a 10 prohibits the transfer of 4 numbers of unpacked commands to the register through the 11 elements AND,

The first double word of the command information of the new branch arrives at the information input of the buffer register 2 commands and is followed by the unit state of inputs 18 and 15, as well as code 01 at inputs 17, and G / (figure 2).

A clock pulse 16 at the output of the element And 8 forms an enabling pulse, according to which the first double word of the command information is written into the buffer register 2 of commands, the previous value of the two lower half words from output 26 is written into the buffer register 3 commands, the D-flip-flop 10 is set to 1 (Fig. 0). In register 4 of command numbers, information remains unchanged (all triggers are in state O), since the pre-zero level at output 35 of trigger 10 generates zero levels at information inputs 34 of all triggers. ra 4 (through a group of 11 elements I),

At the outputs of blocks 5, 3 and 2, input signals for memory block 6 are formed, and at the outputs of block 6, active lines are written in accordance with the coding table. In accordance with the input effects on the elements of AND 39-45 and the element OR 46 (Fig. 2). At the output 21.4 of the block 5 of the start indicators, the signal becomes active. This means that the high two bits of the first and second half words from register 3, as well as the high two bits of the first half word from register 2 are ignored (the command information starts from the second half word in re: history 2). The first RR command and the second RX command correspond to codes 00 at outputs 24 and 24;) and codes 01 at codes 24j and 24. At the output of memory block 6, the outputs will be active:

28, (the remainder is zero), 29, 29 (the second command begins with the second half-word, the third command starts with the third half-word of register 2) and 30,

30j (indications of presence: second and third teams). Sigkala with outputs 29 and 29 are received in block 7 multiplexers (fig.Z). The signal from output 294 allows the transmission of the second, third and fourth half words of register 2 (outputs 25j, 26f and 262), respectively, to the place of the first, second and third half words of the second command (outputs

31

f

31,

five

0

five

0

five

0

five

ij., 31, block 7 multiplexers), active output 29 allows the transfer of the third and fourth half words of register 2 (lines 26 and 26g), respectively, to the place of the first and second half words of the third command (outputs 31. and 31g of multiplexer block 7),

According to the next clock pulse, in the presence of a single level. input device 1-5, information prepared at output 31 of block 7 multiplexers (first two commands), is written into the buffer register 1 of commands, command numbers prepared at output 30 of block 6 of memory through a group of 11 elements And are recorded into register 4 ( since the transfer is resolved by the single state of output 35 of the D-flip-flop 10, which is set to the state O only after the arrival of the next signal Reset and later we assume that the transmission of command numbers through the group of elements And is resolved), the second double word of the command info the value is written into the buffer register 2 commands, and the meaning of the lower two half words of the first double word from the buffer register 2 commands is memorized; in the buffer register 3 is com-1, In accordance with the input effects on the element I.39-45 and the element OR 46 (Fig. 2) to the output signal 21, 1 of block 5 becomes active (the command information starts with the first half-word in register 2),

The third SS format command and the fourth RS format command correspond to codes 11 at outputs 24,

24,

and 10 at outputs 24 and 24g. At the output of block 6, the outputs will be active: 28 (the remainder is equal to one half-word),

50 3 (the first command starts with the first half-word of register 2), 30 (sign of the presence of the first command). The active signal from output 29, j enters into multiplexer block 7.

sg (fig.Z) and allows the transfer of primary ee

second, second half words of register 2 (outputs 25, 5 25, and 25 in FIG. 3), respectively, to the place of the first, second and third half words

the first command (outputs 31., 31, and 31 blocks of 7 multiplexers).

Thus, at the moment at the output 20 of the device there are the first (RR format) and the second (RX format) commands in place of the second and third commands of the buffer register 1, respectively, and at the output 19 of the device numbers of the second and third commands. At the same time, the information inputs for buffer register 1 and register 4 for command numbers provide information for the next command in SS format. After the first and second commands have been received by the processing units and (depending on the specific implementation of the processor, this can occur either in one or in two different cycles), an indication is received — 1 “w of reception at inputs 14.2 and 14.3 of command numbers devices that through the elements OR 56 and 56 (Fig, 4) reset the corresponding triggers of the register 4 numbers of commands. The inverse outputs of the 33 triggers register 4 prepare on the element And 8 reception of the next double word command information.

By analogy with the above, and if the corresponding conditions for the next TaxroBONry pulse are fulfilled, a third unpacked SS format command is written to the buffer register 1 in place of the first command, in register 4 the number of the first command, in register 2 the third double word of the command information, in register 3 the third and fourth half-words of the second double word of the command information,

Since the fourth RS format command occupies the lower half word of the second double word and the older half word of the third double word, it did not participate in the previous unpacking and only the third SS command entered the processing units. At the moment, the beginning of the fourth command is in the second half of the buffer register 3, In accordance with the input effects on elements AND 39-45 and element OR 46 (FIG. 2), the signal at output 21.2 of block 5 becomes active (the command information starts from the second half-word in reg3), the fourth coma de RS format, the fifth RR format command codes correspond to 10 vskhodah 22z and 22 codes 00 on lines 24 and 24z.

and codes 11 on outputs 24j. and 24, On, the output of block 6, the outputs will be active: 282 (the remainder is equal to two half words),

29,

 2,

29 (the first command begins with the second half-word of register 3, the second command begins with the second half-word of register 2), 30 ,, 30. (signs of the presence of the first and second

mand), the active signals of the outputs 29, and 294 enter the multiplexer block 7 (FIG. 3) and allow the transmission of the second half-word of the register 3 (line 232 of the first and second half-word

register 2 (lines 25, and 25) respectively to the place of the first, second and third half words of the first command (outputs 31, 31 and 31j of block 7 multiplexers).

After the third SS command is received by the processor processing blocks and when the corresponding conditions are fulfilled, the next RS clock command is written into register 1, the fourth RS command is replaced with the first command and the RR command is replaced with the second command, register 4 is the first and second teams, in register 2 - even

the true double word of the command information is Main-iH; in register 3, the third and fourth half-words of the third double word of the command information.

A sixth SS format command occupies two half words of the third double word and the senior half word of the fourth double word. This is indicated by code 001, recorded in register 36, and code 11 on lines 22 and 22; the seventh, eighth and ninth commands of the RR formats are indicated by codes

five

0

five

00 00 00 on line x 24 ,, 24., 24

3

t.

.

24, 24 and 24g. Listed codes

as well as the active signal 21, which is generated by the block 5 in accordance with the information recorded in the register 36, is transferred to the block 6 of the memory. The output of block 6 will be active outputs 28

29, 29,

29

R

(the remainder is zero), y, q, 29 (the first command starts with the first half-word of register 3, the second command starts with the second half-word of register 2, the third starts with the third half-word of register 2, and the fourth from the fourth half-word of register 2), 30, 30 , ZOZ, 30 (signs of the presence of the first, second, third and fourth commands), Active signals from the outputs 29, 29, 297- and 29 enter the block

7 multiplexers (FIG. 3) and permit the transfer of the first and second half words of register 3 (outputs 32J and 23i) and the first half word of register 2 (round 25j) respectively to the place of the first, second and third half of the first command (outputs 31, H,

mand.

about tl and h

10 a y u u

e e so

that, in order to increase the speed of 1 VIEW due to the simultaneous unpacking of several commands, it contains the third buffer command register, the AND group of elements, the OR group of elements, the D flip-flop and the start pointers block

3), the second, third and fourth samples, with the input of the resolution of the half-words of register 2 (outputs 25 th

The device's command is connected to the information input of the D-flip-flop and the first input of the And element, the second input of which is the synchronization input of the device, the output of the And element is connected to the synchronization inputs of the F-flip-flop, the first, second and third buffer command registers, the block of sample start indicators and the register of the company numbers, the device reset input is connected to the F-trigger reset input and to the first inputs of the OR elements, the second inputs of which are connected to the corresponding bits of the input of the device command numbers, the outputs OR groups are connected to the corresponding reset inputs of the command number register, the information input of the third buffer command register is connected to the second output of the second buffer command register, the first output of the third buffer register is connected to the third information input of the multiplexer unit, and the second output of the third buffer command register connected to the second address input of the memory unit, the third address input of which is connected to the output of the block of pointers of the beginning of the sample, the first input of which signs connect with the input of the device instruction code bits, the device unpacking mode setting input is connected to the second input of the block of sample start indicators, the third sign input of which is connected to the output of the memory block address code, the direct output of the D flip-flop is connected to the first inputs of the AND elements the group, the second output of the micro-operation code of the memory block is connected to the corresponding second inputs of the AND elements of the group, the outputs of the AND elements of the group are connected to the corresponding information inputs of the trigger triggers of the command number register, direct to The outputs of which are the outputs of the device command number code, the inverse outputs of the register of the command number are connected to the remaining inputs of the element I.

25z and 25) respectively to the place of the first, second and third half words of the second team (exits 31, 315- and 31); the third and fourth half words of register 2 (outputs 25 ,, and 254), respectively, to the place of the first and second half words of the third team (outputs 31 and 31g); the fourth half-word registrar 2 to the place of the first (and only) half-word of the fourth team (exit 31d).

After the fourth and fifth commands are received, the processing blocks are sent to the buffer by the next clock pulse: the sixth register, the eighth, the ninth command, the first, second, third, and fourth commands are written to register 4, the second, third, third, and fourth commands are written to register 4; the next double word of the command information, in register 3 is the matched two half words of the previous double word from register 2,

The process continues until the next pulse Q6poc is received,. indicates the need to move to a new branch of the program.

F

formula of invention

1. A device for unpacking commands containing the first and second command registers, a memory block, a multiplexer unit, a register of command numbers and I, and the output of the unpacked device commands is connected to the output of the first buffer command register, whose information input is connected to the output the multiplexer unit, the first and second information inputs of which are, respectively, the first and second, the output of the second buffer command register, the third output of which is connected to the first address input of the memory unit, the first output of the mic code ooperatsy which is connected to a control input yuschi multipl1gksorov block MSB input instruction code unit is connected to the data input of the second buffer register to

about tl and h

10 a y u u

e e so

that, in order to increase the speed of 1 VIEW due to the simultaneous unpacking of several commands, it contains the third buffer command register, the AND group of elements, the OR group of elements, the D flip-flop and the start pointers block

 samples and the input resolution is

five

0

five

0

five

0

five

0

55

The device's command is connected to the information input of the D-flip-flop and the first input of the And element, the second input of which is the synchronization input of the device, the output of the And element is connected to the synchronization inputs of the F-flip-flop, the first, second and third buffer command registers, the block of sample start indicators and the register of the company numbers, the device reset input is connected to the F-trigger reset input and to the first inputs of the OR elements, the second inputs of which are connected to the corresponding bits of the input of device command numbers, the outputs OR groups are connected to the corresponding reset inputs of the command number register, the information input of the third buffer command register is connected to the second output of the second buffer command register, the first output of the third buffer register is connected to the third information input of the multiplexer unit, and the second output of the third buffer command register is connected to the second address input of the memory block, the third address input of which is connected to the output of the block of pointers of the beginning of the sample, the first input of which signs are connected n with the input of the device command code bits, the device unpacking mode setting input is connected to the second input of the block of sample start indicators, the third sign input of which is connected to the output of the memory block address code, the direct output of the D flip-flop is connected to the first inputs of the elements Both the groups, the second output of the micro-operation code of the memory block are connected to the corresponding second inputs of the elements of the AND group, the outputs of the elements AND of the group are connected to the corresponding information inputs of the trigger numbers of the register of command numbers, forward e outputs which are output code devices command number, inverse outputs command numbers register connected with the other input member I.

P) ig.5

Compiled by V. Krivoruchko. Editor N. Yatsola Tehred M. Morgantal Corrector S. Shekmar

Order 1390

Circulation 669

VNYUSHI of the State Committee for Inventions and Discoveries at the State Committee on Science and Technology of the USSR (tOOSI), Moscow, Zh-35, Raushsk nab., 4/5

Subscription

Claims (2)

mand, factory registers of commands, the unit of multiplexers, the register of command numbers and the element And, the output of the unpacked device commands is connected to the output of the first buffer register of commands, the information input of which is connected to the output of the unit of multiplexers, the first and second information inputs of which are connected to the first and the second, outputs of the second buffer register of commands, the third output of which is connected to the first address input of the memory block, the first output of the microoperation code of which is connected to the control input of the unit as multiplexers, the input of the most significant bits of the device command code is connected to the information input of the second buffer register 1464157 Umand, characterized in that, in order to increase the speed of ¹ VIA by simultaneously unpacking several commands, it contains a third buffer register of commands, a group of AND elements, a group of OR elements, ₍ D-trigger and a block of indexes of the beginning of the selection, and the input permission to receive device commands is connected to the information input of the D-trigger and the first input of the And element, the second input of which is the synchronization input of the device, the output of the And element is connected to the synchronization inputs of the г-trigger, the first, second and third buffer register of commands, a block of pointers to the beginning of the selection and register .. command numbers, the reset input of the device is connected to the reset input of the P-trigger and to the input inputs of OR elements of the group, the second inputs of which are connected to the corresponding bits of the input of the device command numbers, the outputs of the OR elements are connected with corresponding inputs for resetting the register of command numbers, the information input of the third buffer register of commands is connected to the second output of the second buffer register of commands, the first output of the third buffer register of commands is connected to an information input of the multiplexer block, and the second register the address address path of the block of pointers to the start of sampling, the first input of signs of which is connected to the input of the least significant bits of the device command code, the input of the job of the unpacking mode of the device is connected to the second input of signs. connected to the output of the address code of the memory block, the direct output of the D-trigger is connected to the first inputs of the elements AND groups, the second output of the microoperation code of the memory block is connected to uyuschimi second inputs of the AND group elements and outputs connected to respective groups of information inputs instruction register numbers triggers direct outputs which are the outputs of the code device command number, inverse outputs command numbers register connected with the other input member I. the output of the third buffer command is connected to the second input of the memory block, the third input of which is connected to 12 II 1464157 2. The device according to claim 1, characterized in that the block of indicators of the beginning of the sample contains a register and an encoder, and the synchronization input of the block of indicators of the beginning of the sample is connected to the synchronization input of the register, the first, second and third groups of information inputs of which are connected respectively to the first, second and the third inputs of the signs of the block; pointers to the beginning of the sample, the output of which is connected to the output of the encoder, the input of which is connected to the direct and inverse outputs of the register.