RU2112272C1 - Unit of microcontroller network - Google Patents

Abstract

FIELD: automation and computer engineering, in particular, design of efficient controlling equipment. SUBSTANCE: device has microprogram memory unit, registers for address and microinstructions, multiplexer for logical conditions, constant generator, starting flip-flop, first comparison circuit, first clock oscillator, first buffer memory unit, address commutator, first output commutator, first, second and third AND gates, first to fourth OR gates, first delay gate, first univibrator, register for event counting, second buffer memory unit, second clock oscillator, second output commutator, second comparison circuit, flip-flops for channel switching, synchronization control and lock conditions, NOR gate, flip-flop, fourth to fourteenth AND gates, fifth to seventh OR gates, second and third univibrators, four delay gates. EFFECT: increased efficiency. 5 dwg

Description

 The invention relates to automation and digital computer technology and can find application in the construction of control and computing systems of high performance, including systems with mass parallelism, as well as discrete control subsystems of multi-level intelligent automated control systems (ACS) of technological and robotic complexes where accurate coordination of the moments of initialization and completion of asynchronous processes.

 A microprogram control device comprising a read-only memory block, a micro-command address generating unit, a next micro-command address register, a micro-operation register, a micro-command format register, a micro-program start register, a state register of parallel sections, a control trigger, a pulse generator, an OR element, an OR block, the first and the second elements And, the first and second blocks of elements And, the group of elements And, one-shot, the first, second and third elements of the delay (A. S. USSR N 1647566, CL G 06 F 9/22, publ. 07.05.91, BI N 17 )

 The disadvantage of this device is the significant number of external outputs used to organize interaction with other similar devices (receiving and issuing control transfer addresses), and, as a result, the sharply limited scalability of the control systems formed on its basis and, accordingly, the narrow scope of the device.

 Closest to the proposed device in technical essence is a microprogram device for controlling the exchange of control information in a distributed system, including a microprogram memory block, address registers, microcommands and receivers, a buffer storage unit, a register block, address switches, output and microcommands, a constant generator, a circuit comparisons, logic condition multiplexer, clock generator, trigger, delay element, first to third elements AND, first and second blocks of elements s and the first through fourth elements and OR monostable multivibrator (USSR AS, N 1325477 cl. G 06 F 9/22, publ. 07.23.87, BI N 27).

 The disadvantage of this device is a narrow scope due to the lack of synchronization means for completing parallel branches (sections) of microprograms assigned to various modules of control systems formed on its basis. The inability to synchronize the completion of parallel sections can lead to incorrect operating modes, for example, to the simultaneous (parallel) execution of incompatible operations when implementing parallel control algorithms.

 An object of the invention is to expand the scope of the device based on the organization of the ability to synchronize the completion of arbitrary groups of parallel sections of microprograms.

 The technical problem is solved by the fact that the microcontroller network module containing the microprogram memory block, address and micro-instruction registers, logical condition multiplexer, constant generator, trigger trigger, the first comparison circuit, the first clock pulse generator, the first buffer storage unit, the address switch, the first output switch , from the first to the third elements AND, from the first to the fourth elements OR, the first delay element and the first one-shot, and the input of the constant generator is the input settings of the module, and the output connected to the first input of the first comparison circuit, the output of the first output switch is connected to the output of the module synchronization control, the output of the first OR element is connected to the first input of the first AND element, the output of the second OR element is connected to the installation trigger input, the direct output of which is connected to the input of the first generator clock pulses, the first output of which is connected to the synchronization input of the address register, and the second output is connected to the synchronization input of the micro-command register, outputs of the logical condition code, and m a differentiable digit of the address of which is connected to the address and first information inputs of the logical condition multiplexer, respectively, the second information input of which is the input of the logical conditions of the module, the output of the logical conditions multiplexer in combination with the output of the unmodifiable part of the micro register register address is connected to the first information input of the address switch, whose output is connected to the information input of the address register, the output of which is connected to the address input of the microprogram memory block the output of which is connected to the information input of the micro-command register, the output of the end-of-operation label of which is connected to the first and second control inputs of the address switch, further includes a second buffer storage unit, a second clock pulse generator, a second comparison circuit, an event counter-register, a second output switch, triggers for channel switching, synchronization and blocking control, trigger, fourth to fourteenth AND elements, fifth to seventh OR elements, OR-NOT element, second and third one vibrators, from the second to the fifth delay elements, the output of the synchronization control mark of the micro-register register being connected to the first inputs of the second and third AND elements and to the first input of the third OR element, the output of which is connected to the first input of the fourth AND element, the output of which is connected to the trigger reset input start, the output label of the end of the section of the register of microcommands is connected to the first inputs of the fifth and sixth AND elements, with the third and fourth control inputs of the address switch, with the second input of the third OR element, with the input of the installation of the locking trigger, as well as with the first input of the fourth OR element, the output of which is connected to the fifth control input of the address switch, the second information input of which is the input of the operation code of the module, the output of the microcontrol register control transfer mark is connected to the third input of the third OR element, with the first input of the seventh AND element and with the first control input of the second output switch, the output of which, in combination with the output of the fifth OR element, forms the control transmission output of the module, you the progress of the control information of the micro-command register includes the output of the number of the synchronization point number and the output of the number of expected events and is connected to the first information inputs of the first and second output switches, the output of the number of the synchronization point of the micro-command register is connected to the first input of the second comparison circuit, the output of which is connected to the second input of the sixth AND element and to the second input of the third AND element, the third input of which is connected to the output of the OR-NOT element, the output of the third AND element is connected to the first (inverse) octagon input AND element with the first input of the ninth AND element, the output of which is connected to the first input of the second OR element, the second input of which is connected to the output of the first one-shot, the output of the mark of the end of the micro-register register operation is connected to the output of the module operation end, with the fourth input of the third OR element, with the second input of the fourth OR element and with the second input of the fifth AND element, the third input of which is the module start input, the output of the fifth AND element is connected to the third input of the second OR element, the second output of the first generator of industrial pulses is connected to the input of the second one-shot, the output of which is connected to the second input of the fourth element And and to the second input of the second element And, the output of which is connected to the installation input of the trigger synchronization control, the direct output of which is connected to the first control input of the first output switch, to the first input of the tenth element And to the first input of the eleventh element And, the output of which is connected to the input of the installation of the trigger, the counting input of which is connected to the inverse output of the trigger control sync onization, the direct output of the trigger is connected to the first input of the twelfth element And, the output of which is connected to the reset input of the synchronization control trigger, the first output of the second clock pulse generator is connected to the second input of the seventh element And, to the second input of the eleventh element And, to the installation input of the channel switching trigger and to the second input of the tenth AND element, the output of which is connected to the first input of the sixth OR element, the output of which is connected to the output of the module synchronization control, the second output of the second a clock pulse generator is connected to the first input of the thirteenth AND element, to the second input of the twelfth AND element, to the reset input of the channel switching trigger and to the second input of the first AND element, the output of which is connected to the second input of the sixth OR element and to the input of the first delay element, the output of which connected to the inputs of the shift synchronization and shift resolution of the first buffer storage unit, the output of which is connected to the second information input of the first output switch and to the inputs of the first OR element, the output which is connected to the second control input of the first output switch, the third and fourth control inputs of which are connected to the inverse and direct outputs of the channel trigger, respectively, the module synchronization control input is formed by the input of the synchronization point number, the input of the number of expected events and the synchronization line, the input of the module synchronization point number connected to the second input of the second comparison circuit and, in combination with the output of the register-event counter, connected to the information input of the first a buffer storage unit, the recording synchronization input of which is connected to the output of the eighth AND element, the input of the number of expected events of the module is connected to the inputs of the OR-NOT element and to the information input of the event-counter register, the synchronization line of the module synchronization control input is connected to the input of the second delay element, output which is connected to the synchronization input of the register-event counter, to the second input of the ninth AND element and to the input of the third one-shot, the output of which is connected to the second (direct) input of the first element And and with the third input of the sixth element And, the fourth input of which is connected to the direct output of the lock trigger, the output of the sixth element And is connected to the counting inputs of the lock trigger and the register-counter of events, the direct and inverse outputs of the channel switching trigger are connected respectively to the second and third control inputs of the second output switch, the input of the control reception module is formed by the input of the module number, the input of the control reception address and the synchronization line, the input of the control reception address of the module n with the third information input of the address switch and in combination with the input of the device module number is connected to the information input of the second buffer storage unit, the output of which is connected to the second information input of the second output switch and to the inputs of the seventh OR element, the output of which is connected to the fourth control input of the second output switch and with the second input of the thirteenth AND element, the output of which is connected to the first input of the fifth OR element and to the input of the third delay element, the output of which connected to the inputs of the shift synchronization and shift resolution of the second buffer storage unit, the recording synchronization input of which is connected to the output of the fourteenth element And, the first (direct) input of which is connected to the output of the fourth delay element, the input of which is connected to the synchronization line of the module control reception input, the input number the device module is connected to the second input of the first comparison circuit, the output of which is connected to the second (inverse) input of the fourteenth And element, with the input of the first one-shot, as well as with fifth control input of switch addresses, the output of the seventh AND gate connected to the second input of the fifth OR gate and to the input of the fifth delay element whose output is connected to a fourth input of the second OR gate, the output micro microinstruction register is the output of the module micro-operations.

 The essence of the invention is as follows.

 The proposed device, together with other identical devices (modules), is combined into a ring structure called a microcontroller network (MCS) and designed to control complex objects (complexes of interconnected objects) that involve parallel and asynchronous flow of many processes in time (for example, groups of processor elements in multiprocessor computing systems).

 Each ISS module is implemented in the form of VLSI with an internal reprogrammable memory of microprograms and provides the following capabilities: control of a sequential process, initialization of processes in other similar devices, as well as synchronization of their completion by transmitting special control microcommands (messages). To identify the various modules of the ISS, they are assigned logical numbers 1,2, ..., N. The type (number) of the operation to be performed is determined by the operation code (CPC), which is the address of the first microcommand of the initial section of the corresponding microprogram and is generated by the top-level control device (UUVU), for example, by the central processor.

 When controlling parallel or sequential processes, the ISS modules generate sequences of microcommands, the order of which is determined by the values of the signals of logical conditions coming from the control object (taken from the corresponding sensors or generated by special features for generating features). During the implementation of the firmware sections, the network modules can initiate the execution of the firmware sections by other modules by transmitting the corresponding starting addresses to these modules.

 Initialization of parallel or sequential sections of firmware (control transfer) is carried out as follows.

,

, одному из перечисленных модулей присваивается статус ведущего (например, ведущим считается модуль

, остальные рассматриваются как ведомые. В качестве ключевой информации при синхронизации параллельных участков используется номер точки (вершины) слияния (синхронизации) этих участков T_r, а также число участков Wr₀ (количество ожидаемых событий), завершающихся в точке T_r.The module M _i forms a control micro-command S, which includes the number of the initialized module k and the corresponding starting address (initialization address) A _pu . The micro-command S is transmitted to the module M _{i + 1} , where it is analyzed, which consists in comparing the number of the receiver of the message k with the number of this module (i + 1). If the numbers indicated coincide, then the module M _{i + 1} starts the execution of the firmware section from the received address A _ny otherwise microinstruction S transmitted to the output module M _{i + 1} and transferred to the next module ISS M _{i + 2,} where again subjected to analysis. Similarly, the micro-command S is transmitted to the next module in the ring structure of the network and is relayed until the number k coincides with the number of one of the ISS modules,
To implement the synchronization mode of completion of the group P of parallel sections of microprograms assigned to the modules

,

, one of the listed modules is assigned the status of the leader (for example, the module is considered the leader

, the rest are treated as slaves. As the key information when synchronizing parallel sections, we use the number of the point (top) of the merger (synchronization) of these sections T _r , as well as the number of sections Wr ₀ (the number of expected events) ending at the point T _r .

The master module M _q , completing the execution of the corresponding section of the firmware, switches to the synchronization control mode, and the remaining (slave) modules enter the active standby state. In the synchronization control mode, the module M _q generates a control micro-command Z _r containing the merge point number T _r and the number of expected events W _r = Wr ₀ -1 (the parallel section executed by the module M _q is not taken into account). This microcommand is sequentially transmitted to the modules M _{q + 1} , M _{q + 2} , ..., M _j , ... and as it passes through each of these modules it is analyzed and, possibly, modified. If the next ISS module M _j executes a certain part of the microprogram (and, accordingly, is not in the standby state) or has completed the implementation of the parallel section at the merge point T _f ≠ T _r , then the micro command Z _r is transmitted without changes to the next module (M _{j + 1} ) otherwise, before issuing the micro-command to the module M _{j + 1, the} number of expected events W _r decreases by one. Similarly, the microcommand under consideration passes through all the network modules and, since the ISS has a ring structure, appears at the input of the master module M _q .

Module M _q analyzes the microcommands arriving at its input, and upon detection of the microcommand Z _r (returning to its input along the ring), it polls the state of the field of the number of expected events W _r . If for the received microcommand Z _r , W _r > 0, i.e. among the controlled parallel sections there are incomplete ones, the module M _q continues to operate in the synchronization control mode and relays the micro-command Z _r to the output for the implementation of repeated polling. If for the received microcommand W _r = 0, i.e. Since all parallel sections converging to the merge point Т _r are completed, the module M _q leaves the synchronization control mode and resumes the execution of the microprogram section assigned to it. The slave modules subsequently exit the standby state as they receive control micro-commands of control transfer S.

 To ensure acceptable performance of the ISS, the transfer of control micro-commands of type S (control transfer) and type Z (synchronization control) is carried out through various - independent and simultaneously functioning - channels.

 The essence of the invention is illustrated by drawings, where in FIG. 1 is a functional diagram of a microcontroller network module; FIG. 2 is a functional diagram of a buffer storage unit, in FIG. 3 is a structural diagram of a ring microcontroller network; FIG. 4 - formats of microcommands implemented by the device, and in FIG. Figure 5 gives an example of the implementation of a parallel control algorithm for a microcontroller network consisting of five devices of the same type.

 The microcontroller network module (Fig. 1) contains a microprogram memory block 1, microcommand register 2, address register 3, logical condition multiplexer 4, a first buffer storage unit 5, a constant generator 7, a first comparison circuit 8, a trigger 11, a first clock generator 12 pulses, address switch 14, first output switch 19, second 24, third 25 and first 33 elements AND, third 36, second 37, fourth 38 and first 39 elements OR, the first one-shot 46 and the first delay element 48, and the input of the generator 7 constants is input 21 module, and the output is connected to the first input of the comparison circuit 8, the output of the switch 19 is connected to the output of the module synchronization control 58, the output of the OR element 39 is connected to the first input of the And 33 element, the output of the OR element 37 is connected to the installation input of the trigger 11 trigger, direct output which is connected to the input of the generator 12 clock pulses, the first output of which is connected to the synchronization input of the register 3 addresses, and the second output is connected to the synchronization input of the register 2 microcommands, outputs 2.1 of the logical condition code (LU) and 2.2 modifiable the address block (Am) of which are connected to the address and first information inputs of the multiplexer 4 logical conditions, respectively, the second information input of which is the input 52 of the logical conditions of the module, the output of the multiplexer 4 logical conditions in combination with the output 2,3 of the unmodifiable part of the address (An) register 2 microcommands connected to the first information input of the address switch 14, the output of which is connected to the information input of the address register 3, the output of which is connected to the address input of the microprogram memory unit 1 amm, the output of which is connected to the information input of the register of 2 microcommands, the output of 2.9 of the end of operation label of which is connected to the first and second control inputs of the address switch 14, as well as the additional included second buffer storage unit 6, the second comparison circuit 9, register counter 10 events, the second generator 13 clock pulses, triggers 15 lock and 16 channel switching, trigger 17, trigger 18 synchronization control, the second output switch 20, the element OR NOT 22, fifth 23, ninth 26, sixth 27, eleventh 28, twelve seventh 29, fourteenth 30, eighth 31, tenth 32, thirteenth 34, seventh 35 and fourth 45 elements AND, sixth 40, seventh 41 and fifth 42 elements OR, second 44 and third 47 single vibrators, second 43, third 49, fourth 50 and the fifth 51 delay elements, and the output 2.5 of the synchronization control label of the register of 2 microcommands is connected to the first inputs of the AND 24, 25 elements and to the first input of the OR element 36, the output of which is connected to the first input of the AND element 45, the output of which is connected to the reset input of the trigger 11 , output 2.6 marks the end of the section of the register 2 microcommands inen with the first inputs of the AND 23, 27 elements, with the third and fourth control inputs of the address switch 14, with the second input of the OR element 36, with the installation input of the trigger 15 of the lock, and also with the first input of the OR element 38, the output of which is connected to the fifth control input the address switch 14, the second information input of which is the input of the module operation code 54, the output 2.7 of the control transfer label of the microcontrol register 2 is connected to the third input of the OR element 36, to the first input of the AND element 35 and to the first control input of the switch 20, the output for which, in combination with the output of the OR element 42, the output 59 of the control transmission of the module is formed, the output 2.8 of the control information of the register of 2 microcommands includes the output 2.10 of the synchronization point number and the output of the number of expected events and is connected to the first information inputs of the output switches 19, 20, the output of the point number 2.10 synchronization register 2 microcommands connected to the first input of the comparison circuit 9, the output of which is connected to the second input of the element And 27 and to the second input of the element And 25, the third input of which is connected to the output of the element OR-N E 22, the output of the And 25 element is connected to the first (inverse) input of the And 31 element and to the first input of the And 26 element, the output of which is connected to the first input of the OR element 37, the second input of which is connected to the output of the one-shot 46, the output is 2.9 end mark operation register 2 microcommands connected to the output 60 of the end of the operation of the module, with the fourth input of the OR element 36, with the second input of the OR element 38 and with the second input of the AND element 23, the third input of which is the input 53 of the start module, the output of the And element 23 is connected to the third input element OR 37, the second output of the generator 1 2 clock pulses are connected to the input of a single-shot 44, the output of which is connected to the second input of the And 45 element and to the second input of the And 24 element, the output of which is connected to the installation input of the trigger synchronization control 18, the direct output of which is connected to the first control input of the switch 19, to the first the input of the And 32 element and to the first input of the And 28 element, the output of which is connected to the installation input of the trigger 17, the counting input of which is connected to the inverse output of the trigger 18 of the synchronization control, the direct output of the trigger 17 is connected to the first m the input of the element And 29, the output of which is connected to the reset input of the trigger 18 of the synchronization control, the first output of the clock generator 13 is connected to the second input of the element And 35, to the second input of the element And 28, to the installation input of the trigger 16 channel switching and to the second input of the element And 32, the output of which is connected to the first input of the OR element 40, the output of which is connected to the output 58 of the module synchronization control, the second output of the clock generator 13 is connected to the first input of the And 34 element, with the second input of the And 29 element, with the input throwing the trigger 16 channel switching and with the second input of the AND element 33, the output of which is connected to the second input of the OR element 40 and to the input of the delay element 48, the output of which is connected to the inputs of the shift synchronization (S) and shift resolution (SE) of the buffer storage unit 5, the output of which is connected to the second information input of the switch 19 and to the inputs of the OR element 39, the output of which is connected to the second control input of the switch 19, the third and fourth control inputs of which are connected to the inverse and direct outputs of the trigger 16 is switched of channels, respectively, the module synchronization control input 55 is formed by the input 55.1 of the synchronization point number, the input 55.2 of the number of expected events and the synchronization line 55.3, the input 55.1 of the module synchronization point number is connected to the second input of the comparison circuit 9 and connected to the output of the register-counter 10 events to the information input of the buffer storage unit 5, the write synchronization input (W) of which is connected to the output of the And 31 element, the input 55.2 of the number of expected events of the module is connected to the inputs of the OR-NOT 22 element and with the information input of the register-counter 10 events, the synchronization line 55.3 of the input 55 of the synchronization control module is connected to the input of the delay element 43, the output of which is connected to the synchronization input of the register-counter 10 events, to the second input of the element 26 and to the input of the one-shot 47, the output of which is connected with the second (direct) input of the And 31 element and with the third input of the And 27 element, the fourth input of which is connected to the direct output of the lock trigger 15, the output of the And 27 element is connected to the counting inputs of the lock trigger 15 and the register counter 10 s events, direct and inverse outputs of the trigger 16 channel switching connected respectively to the second and third control inputs of the switch 20, the input 56 of the control module reception is formed by the input 56.1 of the module number, the input 56.2 of the control reception address and the synchronization line 56.3, the input 56.2 of the module control reception address the third information input of the address switch 14 and in combination with the input 56.1 of the device module number is connected to the information input of the buffer storage unit 6, the output of which is connected to the second information the ion input of the switch 20 and to the inputs of the OR element 41, the output of which is connected to the fourth control input of the switch 20 and the second input of the AND element 34, the output of which is connected to the first input of the OR element 42 and to the input of the delay element 49, the output of which is connected to the synchronization inputs shift (S) and shift resolution (SE) of the buffer storage unit 6, the write synchronization input (W) of which is connected to the output of the AND element 30, the first (direct) input of which is connected to the output of the delay element 50, the input of which is connected to the synchronization line 56.3 in a path 56 for receiving control of the module, input 56.1 of the device module number is connected to the second input of the comparison circuit 8, the output of which is connected to the second (inverse) input of the And 30 element, with the input of the one-shot 46, and also with the sixth control input of the address switch 14, the output of the And element 35 is connected to the second input of the OR element 42 and to the input of the delay element 51, the output of which is connected to the fourth input of the OR element 37, the output 2.4 of microoperations (MO) of the register 2 of microcommands is the output of 57 microoperations of the module.

 The buffer storage unit 5 (6) (Fig. 2) is designed to receive, temporarily store and issue control messages (microcommands) of type Z (S) in the order of receipt and contains a group of registers 61.1-61.L (where L is the maximum length of the message queue in the block), a group of switches 62.1-62.L-1, a decoder 63, a group of elements AND 64.1-64.L, a group of elements OR 65.1-65.L, an element OR 66, a trigger 67 and a delay element 68, the shift synchronization input being (S) of the unit is connected to the input of the delay element 68, the output of which is connected to the reset input of the trigger 67, the shift synchronization input Lok connected to the first input of the OR gate 66, whose second input is connected to the input synchronization recording (W) unit, an output of OR 66 is connected to inputs of a synchronization 61.1-61.L registers inverted outputs are connected to inputs of AND gates 64.1-64. L, respectively, the outputs of which are connected to the input of the decoder 63, the outputs from the first to the Lth of which are connected to the first inputs of the elements OR 65.1-65.L, respectively, whose outputs are connected to the resolution inputs (V-inputs) of the registers 61.1-61. L respectively, the direct outputs of the registers 61.2-61.L are connected to the first information inputs of the switches 62.1-62. L-1, respectively, and the direct output of register 61.1 is the output of the block, the shift enable (SE) input of which is connected to the installation input of trigger 67, the direct output of which is connected to the first control inputs of switches 62.1-62.L-1 and to the second inputs of OR elements 65.1-65.L, the inverse output of the trigger 67 is connected to the second control inputs of the switches 62.1-62. L-1, the second information inputs of which and the information input of the register 61.L are connected to the information input (D) of the unit, the outputs of the switches 62.1-62.L-1 are connected to the information inputs of the registers 61.1-61.L-1, respectively.

 The microprogram memory unit 1 is intended for permanent storage and delivery of microcommands included in various sections of microprograms assigned to the current module.

 Register 2 microcommands for receiving and fixing microcommands read from block 1 of the microprogram memory at the time of their processing, and register 3 addresses for fixing the executive address of the next microcommand of the implemented section of the microprogram, the next operation code, or the address of control reception.

 The logical conditions multiplexer 4 is designed to interrogate the values of logical conditions generated at the input 52 of the logical conditions of the module and modify the value of the least significant bit of the address of the next microcommand at the branch points of the microprograms.

 The generator 7 constants is designed to generate the code of the logical number (identifier) of the module.

 The comparison circuit 8 is used to compare the code of the logical number of the current module with the codes of the receivers of the control micro-commands of type S and generate a receive / relay signal that determines either the micro-command is received by the current module or the transit of the micro-command to the output 59 of the control transmission of the module.

 The comparison circuit 9 is intended for comparing the code of the number of the synchronization point number corresponding to the executed firmware section with the codes of the numbers of synchronization points of type Z microcommands supplied to the module synchronization control input 55 and is used both when the module is operating in the slave mode and when operating in the master mode .

 The register-counter 10 events is intended for temporary storage and modification of codes for the number of expected events of the micro-commands for synchronization control Z when the module is in slave mode.

The clock generator 12 is used to form two disjoint in time pulse sequences t ₁ and t ₂ synchronizing the process of reading microcommands.

The clock generator 13 is used to form two shifted relative sequences of pulses P ₁ and P ₂ , synchronizing the processes of issuing and receiving control microcommands S and Z (to ensure stable operation of the device and to prevent the repeated issuance of microcommands of type S of the repetition rate of clock pulses F ₁ and F ₂ generated respectively by the generator 12 and the generator 13 must satisfy the relation F ₁ > F ₂ .

 The address switch 14 is designed to transmit the address code of the next microcommand to the information input of address register 3 from one of three possible directions: from the output 2.3 of the register of 2 microcommands and the output of the multiplexer 4 of logical conditions, from the input 54 of the operation code or from the input 56 of the control module reception.

 The trigger 11 trigger is designed to control the operation of the generator 12.

 The trigger 15 lock is used to block the process of modifying the codes of the number of expected events during repeated passage of the same control microcommands of type Z.

 The switch 19 provides the transfer of the micro-command synchronization Z generated by the current module, and the micro-command Z received at the input 55 of the module, to a single output 58 of the control module synchronization.

 The switch 20 provides the transmission of type S microcommands generated by the current module and type S microcommands coming from the module control reception input 56 and fixed in the buffer storage unit 6 to a single module control transmission output 59.

 The trigger 16 channel switching is used to control the switches 19 and 20 (provides alternate activation of the first and second information inputs of the switches 19 and 20).

 Triggers 17 and 18 in combination with elements I 24, 28, 29 and one-shot 44 are designed to control the process of issuing control micro-commands of type Z to the output 58 of the module.

 The OR-NOT 22 element is used to generate a signal that determines the state of the field of the number of expected events of microcommands Z received at input 55 when the module is in the master mode.

 Element I 23, single-vibrator 46, element I 35 and element I 26 serve to generate module start signals, respectively, when the module is initialized from the SIA, when control is transferred from another similar module, at the end of the process of issuing type S control microcommands, and when parallel sections of the firmware and together with the OR element 37 are designed to control the start of the generator 12 (switching to the single state of the trigger 11 start).

Element And 25 serves to generate a signal confirming the end of the required parallel sections of the firmware,
Element And 27 serves to control the passage of pulses of modification of codes of the number of expected events generated by a single-shot 47 to the counting input of the register-counter 10 events and control the switching of the trigger 15 of the lock.

 Elements And 30 and 31 are designed to block recording of control microcommands S and Z, respectively, coming from the inputs 56 and 55 of the module, in the buffer storage blocks 6 and 5, respectively.

Groups, the first of which is formed by the elements And 32, 33 and the element OR 40, and the second - by the elements And 34, 35 and the element OR 42, are used to control the issuance of synchronization pulses for receiving control microcommands Z and S, respectively,
The OR element 36 together with the And element 45 and the one-shot 44 is used to generate a shutdown signal of the clock generator 12 (reset trigger 11 trigger).

 The OR element 38 serves to generate a control signal of the switch 14 addresses when the transmission module is waiting for control from another similar device.

 The OR elements 39 and 41 are used to generate signals characterizing the state of the buffer storage units 5 and 6, respectively, and the delay elements 48 and 49 are used to delay the arrival of shift pulses of the queues of the buffer storage units 5 and 6, respectively, when messages are received while messages are received by the next ISS module .

 Delay elements 50 and 43 are introduced to coordinate the timing of the occurrence of synchronization pulses for receiving control microcommands S and Z with the moments of establishment of microcommands at the module inputs 56 and 55, respectively, and the delay element 51 is introduced to delay the receipt of the module start pulse (after issuing the control transfer micro command S) to trigger input 11 for the duration of the presence of a single signal level at its reset input.

 The operation of the proposed device is an example of the operation of a ring microcontroller network (Fig. 3) when implementing a parallel control algorithm.

Given the identity of the modules forming the ISS, we will consider the operation of the network using the example of the functioning of one of the modules, for example, the module M _i .

Initially, registers 61.1-61. L and triggers 67 of the buffer storage blocks 5 and 6 (Fig. 2), trigger 11 of the trigger (Fig. 1), triggers 17 and 18 are in a state of logical zero, trigger 15 is in a state of a logical unit, state register 3 addresses, register- the event counter 10 and trigger 16 are not defined (randomly), and all bits of the register 2 microcommands, except bit 2.9 marks the end of the operation (M _ko ), which is set to a single state, are in a state of logical zero, therefore, the clock generator 12 is turned off, element And 23 is open, address switch 14 is configured to receive information from the input 54 of the operation code of the module, and at the outputs of the OR elements 39, 41 there are logical zero signals indicating the absence of control messages in the buffer storage units 5 and 6, respectively. The clock generator 13 does not have a special control input and therefore constantly generates two time-distributed sequences of clock pulses P ₁ and P ₂ ; at the output of the generator 7 constants there is a code of the logical number of the module (the chain of bringing the elements of the device to its original state in Fig. 1 and 2 are not shown conventionally for simplicity),
The functioning of the ISS begins from the moment of input to the input 54 of one of its modules of the code of the operation being performed. The operation code is generated by the UUVU and fed to the input 54 of the module, which is assigned the initial sequential section of the corresponding microprogram, for example, module M _i . At the same time, the start pulse is applied to the input 53 of the module. The operation code arrives at the second information input of the address switch 14 and, since its second and fourth control inputs have enable signals (respectively “1” and “O”), it passes to the information input of register 3 of the micro command address. The start pulse passes to the output of the AND 23 element, through the OR 37 element it is transmitted to the installation input of the trigger 11 and switches it to a single state. A single signal from the direct output of the trigger 11 is supplied to the input of the generator 12 and allows the formation of pulse sequences t ₁ and t ₂ at its outputs.

On the leading edge of the first clock pulse t ₁ from the first output of the generator 12, the operation code is fixed in register 3 and fed to the address input of the microprogram memory block 1, the output of which after a while the first microcommand of the microprogram being executed appears. On the leading edge of the pulse t ₂ received at the synchronization input of register 2 from the second output of the generator 12, the read micro-command is entered in the register 2 of the micro-commands and appears at its output, and the trailing edge of the pulse t ₂ excites the pulse at the output of the one-shot 44. The further operation of the device is determined the format of the read micro command (Fig. 4).

 Case 1. If the read microcommand has the format A, then the outputs 2.5-2.7 and 2.9 of register 2 of the microcommands set the signal level to zero, the state of the output 2.8 becomes undefined and, accordingly, a zero signal is generated at the output of the OR 36 element, and the address switch 14 is configured to receiving information from its first information input. The zero signal from the output of the OR element 36 blocks the AND element 45, thereby prohibiting the reset of the trigger 11 trigger; a zero signal from the output of 2.5 register 2 blocks the elements And 24, 25; the zero signal from the output 2.6 of register 2 confirms the initial (single) state of the trigger 15 and generates a zero signal level at the output of the And 27 element, and the zero signal from the output of 2.7 register 2 blocks the And 35 element and the first information input of the switch 20. The operational part of the microcommand with output 2.4 of the register 2 microcommands is transmitted to the output 57 of the module to initiate the required micro-operations.

 At the same time, the executive address of the next micro-command is formed.

 The logical condition code from output 2.1 and the modifiable bit of the address from output 2.2 of register 2 of the microcommands are received respectively at the address and first information inputs of the multiplexer 4 of the logical conditions. If the code of the interrogated logical condition is not zero, then the signal from the corresponding bit of the input 52 of the logical conditions of the module is transmitted to the output of multiplexer 4, otherwise (i.e., if the code of the logical condition is zero) the initial value of the least significant bit of the address from the output 2.2 of register 2. Thus, at the output of the multiplexer 4, a modified value of the least significant bit of the address is formed, which in combination with the unmodifiable (high) part of the address from the output 2.3 of register 2 is defined yaet executive address of the next microinstruction. The generated executive address is supplied to the first information input of the address switch 14.

Since the first and third control inputs of the switch 14 there are zero signals coming from the outputs 2.9 and 2.6 of register 2, respectively, the executive address of the next microcommand is transmitted to the information input of register 3 of the address. When the next clock pulse t ₁ appears at the synchronization input of register 3, the address of the next microcommand is entered in register 3 and addresses the microprogram memory block 1, ensuring the reading of the next microcommand. Next, the module starts executing the read micro-command and functions similarly to the previously considered,
Case 2. If the read micro-command has the format B (Fig. 4), the module switches to the control transfer mode to another similar module of the ISS or to initializing a parallel section of the firmware. At the outputs 2.4-2.6 and 2.9 of the register 2 microcommands, the signal level is set to zero, and at the output 2.7 a single signal is formed - the control transfer mark (M _pu ). The number of the module to which control (p) is transferred, and the control transfer address (A _pu ) from the output 2.8 of the control information of the register of 2 microcommands (control micro-command of type S) are sent to the first information input of the switch 20, and the control transfer mark is fed to the third input of the OR element 36 and the first input of the And element 35, as well as the first control input of the switch 20.

 A single signal generated at the output of the OR element 36 opens the And element 45 and the pulse generated by the single-shot 44 passes through the And 45 element to the reset input of the trigger 11 of the launch. The trigger 11 switches to the zero state, and the zero signal from its direct output prohibits the operation of the generator 12: the module temporarily enters the standby state.

The next pulse P ₁ from the first output of the generator 13 switches the trigger 16 to a single state and a single signal from the direct output of the trigger 16 is fed to the second control input of the switch 20, providing a control micro-command S of the control transmission to the output 59 of the control transmission of the module, while the zero signal the inverse output of the trigger 16 blocks the second information input of the switch 20. At the same time, the pulse P ₁ through the open element And 35 and the element OR 42 is fed to the output 59 of the module and provides synchronization of receiving of the micro-command S to be used by the following similar module of the ISS, The same pulse from the output of the And 35 element through the delay element 51 and the OR 37 element is fed to the installation input of the trigger 11 and returns to the unit state (it is necessary to lock the generator 12 for the duration of the issuing of the micro-S commands due to the possibility change of information at the output of 2.8 register 2 until the next impulse P ₁ appears, since F ₁ > F ₂ ).

 The code of the interrogated logical condition from output 2.1 and the modifiable digit of the address from output 2.2 of register 2 are received respectively at the address and first information inputs of multiplexer 4 and form a new value of the least significant bit of the address at its output. The value from the output of the multiplexer 4 in combination with non-modifiable bits of the address from the output 2.3 of register 2 forms the executive address of the next micro-command. This address is transmitted through the switch 14 to the information input of the register 3. A single signal from the direct output of the trigger 11 turns on the generator 12 and the current module resumes the firmware from the address generated on the information input of the register 3.

Case 3. If the read micro-command has format B (Fig. 4), then the module M _i receives the status of the master and switches to the synchronization control mode of completion of the group of parallel sections assigned to other modules. At the outputs 2.4, 2.6, 2.7, and 2.9 of register 2 of microcommands, the signal level is set to zero, a single signal appears at the output 2.5 - a synchronization control label (M _usd ), and at the output 2.8 of the control information, a synchronization point number (NTS) code T _q and a code are generated the corresponding number of expected events (CBS) (completed parallel sections) W _q , forming a micro command synchronization Z _q .

The STC code from the output 2.8 (2.10) of register 2 is supplied to the first input of the comparison circuit 9 and, in addition, together with the CBS code, it is supplied to the first information input of the switch 19. A single label M _us from the output 2.5 of register 2 is supplied to the first inputs of the And 24 element , AND 25 element (at the second input of which there is a zero (inhibitory) mismatch signal from the output of the comparison circuit 9) and OR 36. Similarly to the previously considered, a single signal generated at the output of OR 36 opens the And 45 element and the pulse generated by the single-shot 44 through eleme NT 45 passes to the reset input of trigger 11. Trigger 11 switches to the zero state and thereby inhibits the operation of generator 12: the module goes into standby state.

At the same time, the pulse from the output of the one-shot 44 through the open element And 24 passes to the input of the installation of the trigger 18 of the synchronization control and puts it in a single state. A single signal from the direct output of the trigger 18 goes to the first control input of the switch 19, opens the element And 32 and, in addition, is fed to the first input of the element And 28. The next pulse P ₁ from the first output of the generator 13 switches the trigger 16 to a single state and simultaneously with a single signal generated at its direct output and arriving at the fourth control input of the switch 19 is fed to the second input of the And 32 element. The appearance of single signals at the first and fourth control inputs of the switch 19 while blocking Application of its third control input signal to zero inverse output of the trigger 16 causes the transmission of control microinstruction Z _q to the first data input switch 19 to the synchronization control module 58 output. In turn, the pulse P ₁ passes through the element And 32, the element OR 40, is fed to the output of the module 58 and provides reception of the generated microcommands Z _q module M _{i + 1} .

At the same time, the pulse P ₁ through the open element And 28 passes to the input of the installation of the trigger 17 and translates it into a single state. A single signal from the direct output of the trigger 17 is supplied to the first input of the And 29 element. The pulse P ₂ from the second output of the generator 13 through the open And 29 element is transmitted to the reset input of the trigger 18 and returns it to the state of logical zero. The zero signal from the direct output of the trigger 18 blocks the elements And 32 and 28 and, acting also on the first control input of the switch 19, disconnects the output 2.8 of the control information of the register 2 microcommands from the output 58 of the control module synchronization. At the same time, a positive signal level difference occurring at the inverted output of trigger 18 switches the trigger 17 to its initial (zero) state and the zero signal from the direct output of trigger 17 blocks element 29. The arrival of pulses P ₁ and P ₂ to the inputs of triggers 17 and 18 stops.

The synchronization control micro-commands generated in a similar way by other ISS modules are input to the module 55 and placed in the buffer storage unit 5 (the processing of micro-commands Z before being placed in unit 5 is discussed in detail below). The first of the received microcommands from the output of block 5 is fed to the second information input of the switch 19 and, in addition, generates a single signal at the output of the OR 39 element. The next pulse P ₂ from the second output of the generator 13 returns the trigger 16 to zero state. The zero signal from the direct output of the trigger 16 blocks the first, and a single signal from the inverse output opens the second information input of the switch 19. A single signal from the output of the OR element 39 is fed to the second control input of the switch 19, and the control micro command from the output of block 5 through the switch 19 is relayed to 58 module output. At the same time, the same signal is supplied to the first input of the And 33 element. The P ₂ pulse through the open And 33 element, the OR element 40 is fed to the output of the module 58 and ensures the reception of the relayed micro-command by the next network module.

At the same time, the pulse P ₂ from the output of the And 33 element through the delay element 48 is fed to the shift and shift enable inputs of block 5 and trails the existing microcontrol command queue (the operation of block 5 is described in detail on the example of the operation of identical block 6 and is given below),
Case 4. If the read micro-command has the format G (Fig. 4), then the module M _i completes the execution of the corresponding parallel or sequential section of the microprogram and switches to the active standby state. At outputs 2.4, 2.5, 2.7, and 2.9 of register 2 of microcommands, a zero signal level is formed, at output 2.6, a single signal is set - the label of the end of the parallel / serial section (M _kpu ), the state of outputs 2.1-2.3 becomes undefined, and at output 2.8 (2.10) In register 2, the code of the synchronization point number T _q appears, completing the completed firmware section, for parallel and zero code, for the sequential section. A single signal M _kpu from the output 2.6 of register 2 through the OR 36 element is supplied to the first input of the And 45 element. The pulse from the output of the single-shot 44 through the And 45 element is fed to the reset input of the trigger 11, puts it into zero state and thereby turns off the generator 12. At the same time, the label M _kpu from the output 2.6 of register 2 is fed to the first input of the And 27 element, allows the trigger 15 to be switched, blocks the And 23 element, and also arriving at the third, fourth and fifth control inputs of the address switch 14, it is configured to receive information (addresses at per control over the given module) from the input 56 of the control module reception.

The next micro-command synchronization control Z _t (generated by the module M _k ) accompanied by a synchronization pulse appears at the input 55 of the module; the CBS code W _{t is} supplied to the information input of the register-counter 10 and the inputs of the OR-NOT 22 element, and the HTC T _t code is fed to the second input of the comparison circuit 9 and compared with the code T _q received from the output 2.10 of register 2. The synchronization pulse accompanying the micro-command Z _t , from the input (line) 55.3 of the module enters the input of the delay element 43 and appears at its output with a time shift. From the output of element 43, a synchronization pulse is supplied to the synchronization input of the register-counter 10 events and the leading edge captures the received code W _{t in it} .

If the codes HTC T _q and T _t match, a single signal appears at the output of circuit 9, which is fed to the second input of the And 27 element. Since there is a logic zero signal at the output of register 2 of the 2 microcommands, the zero signal from the output of the And 25 element blocks the And element 26, preventing the switching of the trigger 11 to a single state, and, in addition, opens the element And 31.

The pulse from the output of the delay element 43 is fed to the input of the single-vibrator 47 and, by the trailing edge, excites the pulse v at its output. The pulse v from the output of the single vibrator 47 is fed to the third input of the And element 27 and, since there is a single (enable) signal from the direct output of the trigger 15 at the fourth input of this element, it passes to its output. From the output of the element And 27, the pulse v enters the counting input of the register-counter 10 and initiates a countdown operation by the rising edge: the code W _t decreases by one. At the same time, a pulse v appears at the trigger synchronization input 15 of the trigger and switches it to the zero state by a trailing edge. The zero signal from the direct output of trigger 15 blocks the And element 27, preventing the passage of the next pulse v, and thus does not allow the module M _{i to} repeatedly modify the CBS field of the same micro command Z _t when it appears again at the input of the module 55 (this blocking is necessary, when, due to a significant discrepancy in the moments of the end of various parallel sections, the same control microcommands can be repeatedly broadcast on the ISS ring).

If the codes HTC T _q and T _{t do} not coincide, a prohibitory (zero) signal is generated at the second input of the And 27 element, the pulse v from the output of the one-shot 47 does not pass through the And 27 element, and thus, the code W _t located in the counter register 10, remains unchanged. Similarly, the code W _{t is} not modified if the current module continues to execute the firmware and a zero signal from the output 2.6 blocks the AND element 27.

The modified code W _t from the output of the register counter 10 in combination with the HTC T _t code from the input 55.1 of the module is supplied to the information input of the buffer storage unit 5. At the same time, the pulse v from the output of the one-shot 47 through the open element And 31 is fed to the W-input of block 5 and provides fixation of the micro command Z _t for transmission to the next module of the ISS.

Case 5. If the read microcommand has the D format (Fig. 4), then at outputs 2.4-2.7 of register 2 a zero signal level is formed, at output 2.9 a single signal appears - the mark of the end of the operation (M _ko ), and the state of the remaining outputs becomes undefined. The mark M _ko from the output 2.9 of register 2 through the OR element 36 passes to the first input of the element And 45. The pulse from the output of the one-shot 44 passes through the element And 45 and puts the trigger 11 to zero, thereby turning off the generator 12. At the same time, the mark M _k arrives at the first and second, as well as through the OR element 38, to the fifth control inputs of the switch 14 and configures the switch 14 either to receive the operation code from the input 54 of the module or to receive the address of the control transfer from the input 56.2 of the module. At the same time the mark M is output _{to the} 60 end of the module operation and informs UUVU on the completion of the current ISS and willingness to implement the next operation.

 Let us consider the operation of the module in the mode of reception and analysis of type S control transfer micro-commands

The control transfer micro-command S, developed by the module М _i , is sequentially transmitted along the ISS ring and at some moment it enters the input 56 of the control reception of the module M _{i + h} . The number of the control receiver p contained in the address part of the incoming microcommands is fed to the second input of the comparison circuit 8 and compared with the current module number M _{i + h} generated at the output of the constant generator 7, and the control transfer address A _pu is transmitted to the third information input of the switch 14 addresses. At the same time, the micro-command S is supplied to the information input of the buffer storage unit 6.

When the number p coincides with the number of the current module M _{i + h,} the output signal of the comparison circuit 8 is set to a single signal level. A single signal from the output of the comparison circuit 8 is transmitted to the sixth control input of the switch 14, to the input of the one-shot 46 and blocks the AND element 30. Since at least one of the inputs of the OR element 38 has a single signal (i.e., the considered module has completed some either part of the firmware or operation as a whole), which is a condition for the correct operation of the ISS and is ensured by the availability of synchronization means for completing parallel sections, a single signal is also present at the fifth control input of switch 14, therefore _PU via the switch 14 is supplied to the data input of the address register 3. At the same time, a positive difference in the signal level occurring at the input of the single-vibrator 46 excites a pulse at its output, which, through the OR element 37, enters the installation input of the trigger 11, switches it to the single state, and thus starts the generator 12. The first clock pulse t ₁ s the first output of the generator 12 is fed to the input of the synchronization register 3 and provides a fix received on its information input addresses And _PU . The module M _{i + h} starts the execution of the firmware from the address And _PU .

In the future, the operation of the device for the implementation of the firmware is no different from the functioning of the module M _i when performing the initial sequential portion of the firmware.

 At the same time, the synchronization pulse accompanying the received micro-command S from the synchronization line 56.3 is supplied to the input of the delay element 50, after a specified time appears at its output and goes to the first input of the And 30 element. Since the And 30 element is blocked by a single coincidence signal from the output of the circuit 8 comparison, the synchronization pulse does not pass to its output, and therefore, to the recording synchronization input W of the buffer storage unit 6. Thus, the recording of the received microcommands in block 6 for the purpose of further transmission is not performed is running out.

If the coincidence of the number p and the module number M _{i + h} does not occur, then at the output of the comparison circuit 8, the signal level is zero. The synchronization pulse from the module line 56.3 through the delay element 50 and the open element And 30 passes to the write synchronization input W of the buffer storage unit 6 and provides the received micro-command S for transmission to the next network module M _{i + h + 1} ; the state of the current module remains unchanged.

 The micro command (control message) S from the information input of the buffer storage unit 6 (Fig. 2) is transmitted to the information input of the register 61. L and to the second information inputs of the switches 62.1-62.L-1. Since the trigger 67 is in a state of logical zero, a single signal from its inverse output is fed to the second control inputs of the switches 62.1-62. L-1 and provides the transfer of the control microcommands to the information inputs of registers 61.1-61. L-1, while the zero signal from its direct output blocks the flow of information from the first information inputs to the outputs of switches 62.1-62. L-1. The signals from the inverse outputs of the registers 61.1-61.L arrive at the inputs of the And 64.1-64.L elements, respectively, and form a code on their outputs that characterizes the current state of the control microcommand queue in the block.

. Этот код поступает на вход дешифратора 63 и возбуждает единичный сигнал на его (k+1)-м выходе. Указанный сигнал через элемент ИЛИ 65.k+1 передается на V-вход регистра 61. k+1, разрешая тем самым прием информации в данный регистр.Suppose that previously received microcommands are recorded in registers 61.1-61.k (k <L), and the remaining registers are respectively in a state of logical zero. Since at the inverse outputs of each of the registers 61.1-61.k there is at least one zero signal, and at the inverse outputs of the registers 61. k + 1-61.L, single signals are installed at the outputs of the elements AND 64.1-64. L code is formed

. This code is fed to the input of the decoder 63 and excites a single signal at its (k + 1) -th output. The specified signal through the OR element 65.k + 1 is transmitted to the V-input of the register 61. k + 1, thereby allowing the reception of information in this register.

 The pulse from the synchronization input of the recording block through the OR element 66 is supplied to the synchronization inputs of the registers 61.1-61.L and the trailing edge fixes the control micro-command S in the register 61.k + 1. Since the V-inputs of the remaining registers are 61.1-61. k, 61.k + 2-61.L the inhibitory (zero) signal level is maintained, their state remains unchanged.

 After fixing the micro-command S in the register 61.k + 1, the output of the And 64. k + 1 element displays a zero signal, which, in combination with the signals from the outputs of the And 64.1-64.k, 64.k + 2-64.L elements, is fed to the input of the decoder 63 and excites a single signal at its next, i.e. (k + 2) -m, exit. Similarly, the next control micro-command S is recorded in the register 61.k + 2, etc.

 Reading control microcommands from the buffer storage unit 6 is carried out in the order they are received.

The micro-command S marked in register 61.1 appears at the output of the block and is transmitted (Fig. 1) to the inputs of the OR element 41 and the second information input of the switch 20. The single signal generated at the output of the OR element 41 is fed to the second input of the And element 34 and the fourth the control input of switch 20. The next pulse P ₂ to the second output of generator 15 toggles flip-flop 16 to the zero state and simultaneously with a single signal with its inverted output, a control input at the third input of the switch 20 is supplied to a first input of aND gate 34. Manage -governing microinstruction output unit 6 through the open switch 20 is held at the transmission output control unit 59 and is transmitted to the input 56 of the next module ISS and pulse _P2 passes through the open AND gate 34, OR gate 42 and synchronizes the reception microinstruction issued. Simultaneously with the output of the element And 34, the pulse P _{2 is} fed to the input of the delay element 49 and with a time shift is applied to the inputs of resolution and synchronization of the shift of the buffer storage unit 6.

 The pulse from the input of the resolution of the shift of block 6 (Fig. 2) is input to the installation of the trigger 67 and switches it to a single state. A single signal from the direct output of the trigger 67 is fed to the first control inputs of the switches 62.1-62.L-1 and ensures the transfer of information from the direct outputs of the registers 61.2-61.L to the information inputs of the registers 61.1-61.L-1, respectively. The same signal through the elements OR 65.1-65.L passes to the V-inputs of the registers 61.1-61. L and allows the recording of information in all specified registers. At the same time, the pulse from the input of the shift synchronization (S) of the block is supplied to the input of the delay element 68 and, in addition, is transmitted through the OR 66 element to the synchronization inputs of the registers 61.1-61.L. Since the V-inputs of the registers 61.1-61.L contain enable signals, the information from the registers 61 is located on the trailing edge of the pulse. L-61.2 is transferred to the 61.L-1-61.1 registers, and the zero code is entered in the 61.L register. The state of the register 61.k becomes zero, a single signal is generated at the output of the AND 64.k element, and the control micro-command S, previously located in the register 61.2, appears at the output of the block. The pulse from the output of the delay element 68 after a predetermined time (the shift time of the queue) is supplied to the reset input of the trigger 67 and returns to the zero state.

If after the shift of the queue the state of register 61.1 becomes zero, then the output of the OR element 41 (Fig. 1) sets the zero signal. This signal blocks the AND element 34 and prevents the propagation of the pulse P ₂ to the output 59 of the control transmission of the module and to the input of the delay element 49. The process of issuing control microcommands to the output 59 of the module is suspended. With the arrival of the next control micro-command in block 6, the transit transmission of micro-commands to the output 59 of the module is resumed.

Consider the operation of the master module M _i in the analysis mode of the micro-command synchronization control.

The synchronization control micro command Z _q generated by the module М _i is sequentially transmitted to the modules М _{i + 1} , М _{i + 2} , ..., М _{i + h} , which, as the parallel sections of the microprogram attached to them, either reduce the corresponding code W _q , or leave the incoming micro-command Z _q without modification (see case 4). The synchronization control micro-command sequentially passes through all the network modules and again enters the synchronization control input 55 of the master module M _i .

The STC code T _{q of the} emerging microcommand Z _q from input 55.1 goes to the second input of the comparison circuit 9 and is compared with the STC code generated at the output 2.10 of register 2. Since the latter is the STC code T _q (see case 3), the output of the circuit 9 comparison produces a single coincidence signal, which is transmitted to the second input of the element And 25, the first input of which receives a single label M _must from the output 2.5 of register 2. Simultaneously, the CBS code W _{q of the} received microcommands Z _q from the input 55.2 of the module is fed to the inputs of the element OR- NOT 22, but a sync pulse, s the forward micro-command, from the synchronization line 55.3, enters the input of the delay element 43 and, after a predetermined time, appears at its output.

If W _q > 0, i.e. among the polled parallel sections there are incomplete ones; a zero signal is generated at the output of the OR-NOT 22 element. The zero signal from the output of element 22 through the element And 25 passes to the first input of the element And 31, and also blocks the element And 26. On the leading edge of the pulse from the output of element 43, the code W _{q is} entered in the register-counter 10 events and in combination with the code NTS with the input 55.1 of the module is supplied to the information input of block 5, and the trailing edge of the pulse excites a pulse v of a similar shape at the output of a single-shot 47. At the same time, a pulse from the output of element 43 is fed to the second input of the element And 26, however, since the latter is blocked by a zero signal from the output of the element And 25 , the signal level is kept at its output, trigger 11 remains in the zero state and still blocks the operation of the generator 12. At the same time, the pulse v from the output of the one-shot 47 through the open element And 31 passes to the W-input of block 5 and provides the recording of the micro command Z _q to block 5 for re-issuing to the next module of the ISS and polling the status of the remaining sections of the firmware. Since the element And 27 is blocked by a zero signal from the output 2.6 of register 2, the pulse v does not pass to the output of the element 27 and, thus, the micro command Z _q (code W _q ) is transmitted to the input of block 5 without changes.

If W _q = 0, i.e. if all parallel sections converging to the point T _{q are} completed, then a single signal is generated at the output of the OR-NOT 22 element, which, through the open AND 25 element, is supplied to the first input of the And 26 element and, in addition, blocks the And 31 element. The synchronization pulse from the output of the element 43 through the open element And 26, as well as the element OR 37 passes to the input of the installation of the trigger 11, puts it into a single state and thereby starts the generator 12. At the same time, the pulse v generated by the single-vibrator 47 does not pass to the output of the element And 31, and therefore, to W-input b Loka 5; Thus, the entry of the received microcommands in block 5 is not performed. The first clock pulse t ₁ generated at the first output of the generator 12, fixes the previously generated address of the next microcommand in the register 3. The module M _i leaves the standby state and resumes the execution of the firmware from the address written in register 3.

 In the future, the operation of the module does not differ from its previously considered functioning in the implementation of the initial sequential section of the firmware.

Immediately after synchronization of the parallel sections at the point T _{q, the} module M _i can go into any of the possible operating modes, including the synchronization control mode of the next group of parallel sections.

, где Q_i - общее число параллельных и последовательных участков, закрепленных за модулем М_i,

. Штриховкой на фиг. 5 выделены параллельные участки, сопоставленные ведущим модулям, а стрелками показаны условные направления передачи микрокоманд типов S и Z.The operation of the microcontroller network, built on the basis of the proposed device, we explain on the example of the network, consisting of five modules, when implementing the control algorithm shown in Fig. 5, where the following notation is used: T ₁ , T ₂ , T ₃ , T ₄ are the synchronization points (vertices), and WO ₁ , WO ₂ , WO ₃ and WO ₄ are the numbers of expected events, i.e. parallel sections converging to points T ₁ , T ₂ , T ₃ and T _4, respectively. In the notation M $\genfrac{}{}{0ex}{}{\text{f}}{\text{i}}$ the subscript i defines the module number, and the superscript f corresponds to the parcel number assigned to the module M _i ,

where Q _i is the total number of parallel and sequential sections assigned to the module M _i ,

. The shading in FIG. 5, parallel sections are mapped to the leading modules, and the arrows indicate the conditional directions of the transmission of microcommands of types S and Z.

Initially, the module M ₁ (after receipt of the CPC from the UUVU) implements a serial section M $\genfrac{}{}{0ex}{}{\text{1}}{\text{1}}$ , and then proceeds to the execution of the parallel section M $\genfrac{}{}{0ex}{}{\text{2}}{\text{1}}$ and at the same time generates a micro-command transfer control S, which initiates the execution of the module M ₂ plot M $\genfrac{}{}{0ex}{}{\text{1}}{\text{2}}$ . Module M ₂ , in turn, also generates a microcontrol command transfer, which is transmitted and initiates the start of module M ₃ . Similarly, the initialization of the modules M ₄ and M _{5 is} carried out.

Module M ₂ , completing the implementation of the parallel section M $\genfrac{}{}{0ex}{}{\text{1}}{\text{2}}$ and, being the leader for the synchronization point T ₁ , switches to the synchronization control mode and generates a micro command Z _{1 of the} format T ₁ = 1: W ₁ = 1 (where ":" is the concatenation symbol). Module M ₁ , being slave to the synchronization point T ₁ , completes the execution of the parallel section M $\genfrac{}{}{0ex}{}{\text{2}}{\text{1}}$ and modifies the micro-command Z ₁ arriving at its input (assumes W ₁ = W ₁ -1 and brings it to the form 1: 0). As soon as the micro-command Z ₁ appears at the input of the module M ₂ , this module proceeds to interrogate the CBS field. If the received micro command has the form 1: 0, M ₂ exits the synchronization control mode, proceeds to the execution of the parallel section M $\genfrac{}{}{0ex}{}{\text{2}}{\text{2}}$ while launching section M $\genfrac{}{}{0ex}{}{\text{3}}{\text{1}}$ otherwise M ₂ relays the micro-command Z ₁ to the output and expects it to reappear at the input.

Similarly, execution and synchronization of the completion of other sections of the firmware are performed. The operation of the ISS ceases when the module M ₁ completes the execution of the last sequential section M $\genfrac{}{}{0ex}{}{\text{4}}{\text{1}}$ .

Thus, the proposed device provides the ability to build on its basis systems with wider functionality than systems implemented on the basis of the prototype, which significantly expands the scope of the device. The presence and use of synchronization means for terminating arbitrary groups of parallelly executed sections excludes the possibility of simultaneous implementation of incompatible operations (microcommands), for example, sections M $\genfrac{}{}{0ex}{}{\text{2}}{\text{1}}$ and M $\genfrac{}{}{0ex}{}{\text{2}}{\text{2}}$ included in the algorithm shown in FIG. 5, provided that the execution of section M $\genfrac{}{}{0ex}{}{\text{1}}{\text{2}}$ ends before the execution of section M $\genfrac{}{}{0ex}{}{\text{2}}{\text{1}}$ . The introduced tools make it possible to use the device in the construction of discrete control subsystems of industrial industrial control systems for general purposes, as well as in high-performance computing and control systems that implement complex information processing algorithms that require the parallel development of many interacting processes over time.

The maximum number of synchronized parallel sections converging to a single point of confluence T _m is determined by the width n of the register-counter 10 events (Fig. 1) and the corresponding field in the format of control microcommands and is equal to D _max = 2 ⁿ -1. For most of the possible applications of the device, n = 6-8 (63-255 parallel sections) are sufficient.

Claims (1)

 A microcontroller network module containing a microprogram memory block, address and micro instruction registers, logical condition multiplexer, constant generator, trigger, first comparison circuit, first clock, first buffer memory, address switch, first output switch, from the first to third elements And, from the first to the fourth OR elements, the first delay element and the first one-shot, and the input of the constant generator is the module settings input, and the output is connected to the first input of the first circuit Comparison, the output of the first output switch is connected to the output of the module synchronization control, the output of the first OR element is connected to the first input of the first AND element, the output of the second OR element is connected to the installation input of the trigger, the direct output of which is connected to the input of the first clock generator, the first output which is connected to the synchronization input of the address register, and the second output is connected to the synchronization input of the micro-command register, the outputs of the logical condition code and the modifiable bit of the address connected to the address and first information inputs of the logical condition multiplexer, respectively, the second information input of which is the input of the logical conditions of the module, the output of the logical conditions multiplexer in combination with the output of the unmodifiable part of the micro register register address is connected to the first information input of the address switch, the output of which is connected to the information input address register, the output of which is connected to the address input of the microprogram memory block, the output of which is connected to the information a micro-command register input, the output of the end-of-operation label of which is connected to the first and second control inputs of the address switch, characterized in that a second buffer memory unit, a second clock pulse generator, a second comparison circuit, an event-counter-register, and a second output switch are additionally introduced into it , triggers for channel switching, synchronization and blocking control, trigger, fourth to fourteenth AND elements, fifth to seventh OR elements, OR element - NOT, second and third one-shot s, from the second to the fifth delay elements, and the output of the micro-command register synchronization control label is connected to the first inputs of the second and third AND elements and to the first input of the third OR element, the output of which is connected to the first input of the fourth AND element, the output of which is connected to the trigger reset input start, the output label of the end of the micro-register register section is connected to the first inputs of the fifth and sixth AND elements, with the third and fourth control inputs of the address switch, with the second input of the third OR element, with the input setting the trigger lock, as well as with the first input of the fourth OR element, the output of which is connected to the fifth control input of the address switch, the second information input of which is the input of the module operation code, the output of the microcontrol register control transfer mark is connected to the third input of the third OR element, with the first input of the seventh AND element and with the first control input of the second output switch, the output of which, combined in the output of the fifth OR element, form the output of the module's control transmission, the control output The information of the micro-command register includes the output of the number of the synchronization point number and the output of the number of expected events and is connected to the first information inputs of the first and second output switches, the output of the number of the synchronization point of the micro-command register is connected to the first input of the second comparison circuit, the output of which is connected to the second input of the sixth element And and to the second input of the third AND element, the third input of which is connected to the output of the OR element - NOT, the output of the third AND element is connected to the first (inverse) input of the eighth element that And with the first input of the ninth AND element, the output of which is connected to the first input of the second OR element, the second input of which is connected to the output of the first one-shot, the output of the mark of the operation end of the micro-register register is connected to the output of the end of the operation of the module, with the fourth input of the third OR element, with the second input of the fourth OR element and with the second input of the fifth AND element, the third input of which is the module start input, the output of the fifth AND element is connected to the third input of the second OR element, the second output of the first clock generator and pulse is connected to the input of the second one-shot, the output of which is connected to the second input of the fourth element And to the second input of the second element And, the output of which is connected to the installation input of the trigger synchronization control, the direct output of which is connected to the first control input of the first output switch, to the first input of the tenth element And to the first input of the eleventh element And, the output of which is connected to the installation input of the trigger, the counting input of which is connected to the inverse output of the trigger control synchronization her, the direct output of the trigger is connected to the first input of the twelfth element And, the output of which is connected to the reset input of the synchronization control trigger, the first output of the second clock pulse generator is connected to the second input of the seventh element And, to the second input of the eleventh element And, to the installation input of the channel switching trigger and to the second input of the tenth AND element, the output of which is connected to the first input of the sixth OR element, the output of which is connected to the output of the module synchronization control, the second output of the second generator clock pulses is connected to the first input of the thirteenth AND element, with the second input of the twelfth AND element, with the reset input of the channel switching trigger and with the second input of the first AND element, the output of which is connected to the second input of the sixth OR element and to the input of the first delay element, the output of which is connected with shift synchronization and shift enable inputs of the first buffer storage unit, the output of which is connected to the second information input of the first output switch and with the inputs of the first OR element, the output of which о is connected to the second control input of the first output switch, the third and fourth control inputs of which are connected to the inverse and direct outputs of the channel trigger, respectively, the module synchronization control input is formed by the input of the synchronization point number, the input of the number of expected events and the synchronization line, the input of the module synchronization point number connected to the second input of the second comparison circuit and, in combination with the output of the register-event counter, connected to the information input of the first buffer memory block, the recording synchronization input of which is connected to the output of the eighth AND element, the input of the number of expected events of the module is connected to the inputs of the OR-NOT element and to the information input of the event-counter register, the synchronization line of the module synchronization control input is connected to the input of the second delay element, output which is connected to the synchronization input of the register-event counter, to the second input of the ninth element And and to the input of the third one-shot, the output of which is connected to the second (direct) input of the eighth nta And with the third input of the sixth element And, the fourth input of which is connected to the direct output of the blocking trigger, the output of the sixth element And is connected to the counting inputs of the blocking trigger and register-counter of events, the direct and inverse outputs of the channel switching trigger are connected respectively to the second and third control the inputs of the second output switch, the input of the control reception of the module is formed by the input of the module number, the input of the control reception address and the synchronization line, the input of the control reception address of the module is connected to the third information input of the address switch and in combination with the input of the device module number is connected to the information input of the second buffer storage unit, the output of which is connected to the second information input of the second output switch and to the inputs of the seventh OR element, the output of which is connected to the fourth control input of the second output switch and with the second input of the thirteenth AND element, the output of which is connected to the first input of the fifth OR element and to the input of the third delay element, the output of which is connected is with the shift synchronization and shift enable inputs of the second buffer storage unit, the write synchronization input of which is connected to the output of the fourteenth AND element, the first (direct) input of which is connected to the output of the fourth delay element, the input of which is connected to the synchronization line of the module control reception input, the input of the number the device module is connected to the second input of the first comparison circuit, the output of which is connected to the second (inverse) input of the fourteenth element And, with the input of the first one-shot, as well as with the sixth unit with the input input of the address switch, the output of the seventh AND element is connected to the second input of the fifth OR element and to the input of the fifth delay element, the output of which is connected to the fourth input of the second OR element, the microoperation register of the micro-command register is the output of the microoperation of the module.

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