SU1282121A1 - Mulimicroprogram control device - Google Patents

Abstract

- The invention relates to the field of automation and computer technology and can be used in the development of computers and other digital systems with firmware. The aim of the invention is to increase speed. The device contains a microinstructions memory block, N address registers, N logic condition code registers, microinstruction register, operation end register, counter, control trigger, clock generator, N control object lock information analysis nodes, decoder, four multiplexers, demultiplexer, N switches , four groups of elements AND, three groups of elements OR, element AND, two elements IL, element NAND. The purpose of the invention is achieved through the implementation in the blocking device by some of the objects controlling the operation of other objects. 1 hp ff, 7 ill. (L

Description

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The invention relates to automation and digital computing and can be used in the design of multi-microprogramming systems for monitoring and controlling complex identical objects.

The purpose of the invention is to increase speed.

Figures 1 to 4 illustrate a functional diagram of a multi-microprogrammed control device; figure 5-7 - time diagrams of the device.

The multi-microprogram control unit (Figures 1-4) contains a block of 1 memory of micro-instructions, the first 2.1 is the N-th 2.N address registers, the first 3.1 -N-th 3.N registers of the logic conditions code, the register 4 micro-commands with fields 4 , 1 end of operation, 4.2 end of operation, 4.3 addresses of the next microcommand 4.4 micro-operations, 4.5 codes of logical conditions, register 5 of end of work, counter 6, control trigger 7, generator of 8 clock pulses, first 9.1 - N - and 9.N nodes of information blocking analysis, decoder 10, address multiplexer 11, multiplexer 12 codes of logical conditions, the first one tipleksor logic 13 conditions the second multiplexer logic 14 conditions the multiplexer 15 interlocks signals, the demultiplexer 16, first 17.1 - N-17 minutes, N switches, the first 18, second 19, third 20, fourth 21 and a group of elements, per- V5TO. 22, the second 23, the third 24 groups of elements OR, the element AND 25, the first element OR 26, the second element OR 27. element AND NOT 28, inputs 29.1 - 29.N

device command codes, device start-up input 30, logic inputs 31.1 31.N devices, outputs 32.1-32.N signals of device microoperations, first 33, second 34, third 35, fourth 36 outputs of generator 8, outputs 37.1 -37, N decoder 10,

Each node of analysis 9 of the blocking information contains the register 38 of the code of the blocked micro-operation, the register 39 of the mask code, the multiplexer 40, the switch 41, the first 42, the second 43 and the third 44 groups of elements I, inputs 45-50, output 51,

The multi-microprogram control device operates in the following modes: implementations of control of N objects in the presence of ready signals from objects of control of realization 45 of control of N objects in the presence of signals of control of objects of control J selective locks on the blocked microoperation,.

5Q Firmware control implementation mode in the presence of readiness signals from control objects, V. the initial state of the trigger 7 control, all registers and the counter are

Consider the operation of the node 9, When the status is zero (the setting chain of the last ten micro-blocking commands to the initial state is not shown). In the service cycle of the control unit-field 4..1 of the register 4 of the micro-commands of the filling of the 1st control object, the unit is entered. In block 1 of the memory of the microd 46 of node 9f, the lock-in code is received, the roo-commands are written microprograms, pack5

ABOUT

35

my microoperations, to inputs 47 - the mask code of blocked objects, to inputs 45 - the code from the output of the decoder 10. At the same time, at output 37; there is a single signal. Under the action of the signal from the output 37 into the register 38 it records with the code of the blocked micro-operation M; and in the register 39 - the mask code of the blocked control objects.

During the operation of the multi-microprogram control device, the control inputs of the switch 41 receive the unitary codes of control objects, which are maintained by the device. If the device g serves the blockable object j, then in JM register de register 39 a unit is recorded which, under the action of the control signal 37j, through the switch 41 enters the control inputs of the AND group elements AND 44. At the same time, the code of the blocked microoperation HI from the register 38 through the group of elements AND 44 is fed to the control inputs of the multiplexer 40. If in the operating section issued to the jth control object of the micro-command contains blocked — microoperation

0

five

35,

thirty

M;

then the unit signal of the corresponding input of the group of information inputs 49 through the multiplexer 40 is fed to the output 51 of the node 9j. Otherwise, a single signal at the output 51 of the node 9; missing.

With the blocking of micro-operation Mj at the input 48 of node 9; a single signal arrives, setting registers 38 and 39 to zero,

The multi-microprogram control device operates in the following modes: implementations of control of N objects in the presence of ready signals from objects of control of the implementation of control of N objects in the presence of signals of control of objects of control J selective locks on the blocked microoperation,.

The mode of implementation of firmware control in the presence of readiness signals from control objects, V. the initial state of the trigger 7 control, all registers and the counter are

3128

equal to the work from the first to the Nth control objects.

The operation of the device begins with a signal start to the input 30 of the device. At the same time, signals from the outputs of the OR elements 23.1-23.N corresponding to the operating objects (the corresponding inputs 29.1-29.N receive non-zero values of the command codes), pass through the elements AND 19.1-19.N and establish the corresponding triggers register 5 into one state. A single signal appears at the output of the NE-NE 28, and the generator 8 clock pulses is turned on. ,

The Start signal through the elements OR 22.1-22.N arrives at the synchronization inputs of the 2.1-2.N registers of the address and writes operation codes into these registers (the initial addresses of the microprograms that come from the switch outputs 17.1-17.N. The switches 17.1-17.N allow passing the command codes received respectively from the inputs 29.1-29.N of the device.When S.POLYA 4.1 registers 4 single-signal microcommands, the operation ends the command codes from the outputs of the 2.1-2.N registers of the address to the information inputs of the address multiplexer 11. Simultaneously from the output sch At the control input of multiplexer 11, a control signal (number of the first control object) is received, which allows the operation code (address A1-1) to pass from address register 2.1 to the output of address multiplexer 11. The command code from the outputs of multiplexer 11 is fed to inputs of microcommand memory 1. In this case, the first microinstruction (MC1-1) for the first control object is read from memory 1 and enters the information input of the register 4 microinstructions ..

On the next clock pulse T, from the output 33 of the generator 8, MK1-1 is recorded in the register of 4 micro-instructions, since the signal is on. element output OR 27 is absent. In the record of microcommand MK1-1 to register 4, at output 4.1 of register 4, a zero signal is generated, allowing the address A1-2 of the second microcommand (MK1-2) to pass from output 4.3 of register 4 through switch 17.1 to the information input of register 2.1 of address. Code of logical conditions from output 4.5 re14

gistra 4 microinstructions is fed to the information input of the register 3.1 code logical conditions.

The micro-operations signals from the output 4.4 of the register 4 arrive at the information input of the demultiplexer 16 simultaneously with the arrival at its control input of the code of the number of the first control object from counter 6. The signals of the micro-operations of the micro-command MK1-1 arrive at the output 32.1 of the device, i.e. management With the arrival of micro-operations signals, the first control object at input 31.1- / receives an occupancy signal h (the single readiness signal value) of the first control object that arrives at the corresponding information input of the multiplexer 15. The control input of the multiplexer 15 receives the object number code the output of counter 6, with the result that a single signal is generated at the output of multiplexer 15.

The signal from the output 34 of the generator 8 (pulse T) records the address A1-2 of the following microcommand into the register 2.1 of the address and the code of the logical condition being checked into the register 3.1. The code of the number of the first control object from the counter 6 enters the decoder 10 and excites its output bus 37.1.

When a pulse T is received at the output of an element And 18.1 of a group of elements 18. 1-18.N, a single signal appears. On the falling edge of this pulse, the address A1-2 of the next (second) microcommand (MC1-2) is written to the address register 2.1, and the code of the logical condition that is executed before its execution is written to the register 3.1.

The next microcommand address, which is input to the microcommand memory block 1, is formed by multiplexer 11 and the OR 26 element by modifying the least significant bit of the address with the value of the logical condition being checked. With a zero value of the logical condition, the least significant bit of the address is preserved, and with a single value, it is replaced with the value of a logical condition. The element LI 26 forms a modified address address of the next microcommand. Unmodified address bits from the outputs of multiplexer 11 directly go to the inputs of block 1 of micro-commands, and the low-order (modified) address bits from the output of multiplexer 11 are fed to the input of low-order addresses of block 1 of micro-commands memory through the OR 26 element.

From the outputs of the registers 3.1-3oN to the informational inputs of the multiplexer. 12 Logic condition codes are being received. The code of the control object number from counter 6 arriving at the control unit. The counter 6 then goes into the zero state, and the operation cycle of the device repeats.

At the end of the execution of the current firmware stored in memory block 1, from output 4.1 of register 4, the input of the corresponding 17.1-17.N commutator receives a single value of the signal. End of operation, which

The input of multiplexer 12 allows the fO to allow passage to the registers

5 21216

owls The counter 6 then goes to the zero state, and the cycle of operation of the device is repeated.

Upon completion of the execution of the current firmware stored in memory block 1, from output 4.1 of register 4 to the input of the corresponding switch 17.1-17.N, a single signal value is received. End of operation, which

O allows passage to the registers

passing the logical condition code from the register output 3.1 In this case, the logical condition code goes to the input of the multiplexer 13. Simultaneously, the multiplexer 14 allows the passage of the logical condition value from the device input 31.1 to the information input of the multiplexer 13 (since the control number of the object also goes to the control input of the multiplexer 14 control) of the first object (from counter 6). The value of the logical condition comes from multiplexer 13 to the element OR 26.

The pulse from the output 35 of the generator 8 (pulse T) resets the register 4 (the leading edge of the pulse) and increases the content of the counter 6 by one (the falling edge of the pulse), and the device proceeds to service the next (second) control object.

The pulse from the output 36 of the generator 8 (pulse T.), the trigger 7 goes into one state (if at the output of multiplexer 15 there is a single value of the occupation signal of the control object) or at zero. voy (otherwise).

On the second clock pulses T, -T, the operation of the proposed device is similar to the operation of the device on the first clock pulses. In register 4, the first micro-command MK2-1 of the second control object is written to the register 2.2 of the address (A2-2) - the next (second) micro-command MK2 -2 of the second control object, and in register 3.2 - the code of the logical condition being checked. In the (N4-1) -M cycle, the MK1-2 micro-command, etc., is recorded in register 4. (figure 2).

2.1-2.N of the next command code from inputs 29.1-29.N respectively.

Upon completion of the i-ro operation of the control object from output 4.2 of register 4

5 microinstructions a single signal is received. The end of the work, which, passing through the corresponding element And 21, sets to the zero state the corresponding bit 5, - of the register 5.

20 end of work.

Managing the operation of the multi-microprocessor control device using the end-of-operation register implementation 25 is as follows.

When the device is started up (at input 30, a single Start signal), the signals from the outputs of elements OR 23 of the group of elements SHIII 23. through the corresponding 30 elements AND of the group of elements AND 19.1-19.N are fed to the inputs of the installation in unit of register bits 5.

P: :) and these are the corresponding bits.

35 5 registers 5 are set to

a single state (in a single state, only bits corresponding to the operating control objects are set).

40

After executing the i-th control object of the current firmware at input 29 | enters the next command code. At the same time, at the output of element 45 OR 23 of the group of elements OR 23.1-23.N, a single signal appears, which by the first input opens the element AND 19.2 of the group of elements AND 19.1-19.N. Signal The end of operation 50 from the output 4.1 of the register of 4 micro-instructions comes through the element 20; groups 3jteMeHTOB 20.1-20.N, element ШШ 24 ;, element I 19, to the input of the installation in Resetting the counter 6 to the zero state - the unit of the register bit 5 of the end occurs on a signal of overflow - 55 Jobs. At the same time, it is either confirmed that the internal signal is the state of bits 5 of the counter 6. This signal is generated after the 6N clock pulse 1 arrives at the counting input of the counter.

 The i-th control object executes the microprogram, or bit 5 is set to one.

2.1-2.N of the next command code from inputs 29.1-29.N respectively.

Upon completion of the i-ro operation of the control object from output 4.2 of register 4

micro-commands a single signal is received. The end of the work, which, passing through the corresponding AND 21 element, sets to the zero state the corresponding bit 5, - of the register 5.

end of work.

The operation of the multi-microprogram control device using the end-of-operation register is performed as follows.

When starting the device (at input 30, a single Start signal), the signals from the outputs of elements OR 23 groups of elements SHS 23. through the corresponding elements AND groups of elements AND 19.1-19.N are fed to the inputs of the installation in unit of register bits 5.

P: :) and these are the corresponding bits.

5 registers 5 are set to

a single state (in a single state, only bits corresponding to the operating control objects are set).

After executing the i-th control object of the current firmware at input 29 | enters the next command code. At the same time, at the output of the element OR 23 of the group of the elements OR 23.1-23.N, a single signal appears, which opens the element And 19.2 of the group of elements AND 19.1-19.N on the first input. Signal The end of the operation from the output 4.1 of the register of 4 micro-instructions comes through the element 20; groups 3jteMeHTOB 20.1-20.N, element ШШ 24; element E 19, to the input of the installation in the unit of the register register 5 of the end of the Work. At the same time, either a single state of bits 5 is confirmed.

one

 The i-th control object executes the microprogram, or bit 5 is set to one.

12821218

; Thus, writing the address of the next microcommand to the register 2.2 does not occur and the following microcommand is read in the next cycle of operation of the device from memory block 1 as in the current cycle at the address stored in register 2.2 of the address and so on until those then until input 31.2 receives a zero value for the busy signal from the second control object.

At the output of the multiplexer 15, the signal is absent. Upon receipt of a T4 pulse from output 36 of the mode of implementation of microprogram | 5 rator 8 trigger 7 is set to

if the i-th control object is just starting.

When all bits of register 5 are set to the zero state (which corresponds to the end of work, the multi-microprocessor control unit), a zero signal appears at the output of the IS-NE 28 element. In this case, the generator 8 is turned off and stops the issuance of clock pulses T, -T and the multi-microprogrammed control device stops functioning.

control in the presence of signals from the control objects. The operation of the proposed device in this mode differs from that in that, provided that the i-object of the control object is closed (the control object did not have time to finish the previous microcommand), the next microcommand is recorded in the repetitive T pulse, the code 4 is recorded in the microcommand register 4 regular microinstructions. The clock pulse TI, the input through the element And 18.2 to the input of the synchronization register 3.2 and the element OR 22.2 to the input of the synchronization register 2.2,

gist 4, addresses of the next micro-25, {there is an entry in them of the verification code e. yda for a given object in register 2;

. and the code of the checked logical condition in register 3 i does not occur.

Let us consider the algorithm of functioning of the device under the assumption that 30 when issuing a microcommand to the second control object, this object is ok of a logical condition and the address code of the next microcommand, respectively. Further, the device operates similarly to the described algorithm.

- Thus, in the presence of busy signals from control objects, the recording of addresses of microcommands in registers

- Thus, in the presence of busy signals from control objects, the recording of addresses of microcommands in registers

salary busy i.e. At the input 31 of the signal address 2.1-2.N, the codes for the logical conditions of occupancy, there is a unit in the registers 3.1-3.N and a record of the busy signal. This 35 microcommand in register 4 mix signal passes to the output of multiplexer 15 and enters the information input of trigger 7. When trigger input 7 arrives, trigger commands are not produced until the control objects complete the previous microcommands. Selective lock mode

The output from the output 36 of the generator 8 is a pulse- "lockable micro-operations." In this mode, Td it is set in a single mode, the selection-state is realized. In this case, a single signal OR 27 appears at the output of the locking block, a single signal appears, the control of several objects is controlled by the transmission of the impulse T, c. cut element And 25 and pulse T. through 45 i element And 18.2 groups of elements And 18.1-18.N.

I

In this mode, the control unit begins to function if, when reading the next microcommand, the mask code of the blocked objects and the code of the blocked microoperation are read from the microcommand memory 1.

Thus, the signal to the input of the synV of this mode the control unit begins to function if, when reading the next microcommand from block 1 of the microcommand memory, the mask code of the blocked objects and the code of the blocked microoperation are read.

For example, when the i-ro control object is operating in this mode, the mask code of j

register 4 does not receive 50 and the next microcode MK2-i does not write to register 4. Similarly, the absence of a signal at the synchronization inputs of registers 2.2 and 2.2 under the action of a pulse Tj does not allow 55 control objects to write in them the address of the next micro Direction and the code of the blocked microopicomida (MK2- (i + 1)) and the code being checked - walkie talkies Mj. Subsequent servicing of the control unit is blocking the conditions before its execution by the control unit. My objects in node 9; analyzed

the zero state and the signal at the output of the element OR 27 disappears.

According to the clock pulse T, the code of the next microcommand is written to the register of 4 micro-instructions. The clock pulse TI, the input through the element And 18.2 to the input of the synchronization register 3.2 and the element OR 22.2 to the input of the synchronization register 2.2,

{there is an entry in them of the code of the checked logical condition and the address code of the next microcommand, respectively. Further, the device operates similarly to the described algorithm.

- Thus, in the presence of busy signals from control objects, the recording of addresses of microcommands in registers

addresses 2.1-2.N, codes of logical ordering commands are not made until control objects complete the execution of previous microcommands. Selective lock mode

lockable micro-operations. In this mode, the possibility of selective blocking of several control objects by one control object is realized.

lockable micro-operations. In this mode, the possibility of selective blocking of several control objects by one control object is realized. i

In this mode, the control unit begins to function if, when reading the next microcommand, the mask code of the blocked objects and the code of the blocked microoperation are read from the microcommand memory 1.

For example, when the i-ro control object is operating in this mode, the mask code of j

 the control object of the control objects and the code of the blocked microoperation Mj. During the subsequent maintenance by the control unit of the blocked objects in node 9; analyzed

912

microcommands that he has in the presence of micro-operations M ;. If this micro-operation takes place, then at the output of node 9 {there appears a single signal arriving at the element OR 27. At the same time, the device functions similarly to functioning in the second mode of operation: the next micro-command to register 4 of micro-commands, the addresses of the next micro-command to register 2. to and the code of the logical condition being checked is not recorded in the register of the return register (k is the number of the control object to be locked). At the same time, micro-operations signals do not arrive at the control center to the control object and it is idle.

The end of the lock mode is as follows. When reading the next microcommands for the blocking control object at the second output of block 1 of the microcommand memory, a single blocking signal i-M appears to be the control object of other control objects. In this case, the registers 38,39 knot 9; set to zero. Subsequently, when servicing the kth control object, a single signal at the output of node 9; is absent and the device works in the same way as in the first mode.

Figure 2 shows the timing diagram of the operation of the device when,

In the first cycle of operation, the MC1-1 is output to the first control object. In the second cycle of operation, the MC2 is output on the second control object. Since the first object to the third cycle does not have time to perform MK1-1 (a single signal at the input of 31.1 devices), it is idle in the third cycle. In the fourth cycle, the MC2-2 is assigned to the second object. In the fifth cycle, MC1-2 is output to the first object (there is no signal at input 31.1). In this case, the second object is blocked by the fourth micro-operation.

In the sixth cycle, MC2-3 appears on the second object (the signal at the output of node 9.1 is absent). In the seventh cycle, microcontrol MK1-3 is output to the first control object. In the eighth cycle, the second object MK2-4 is not output, since it contains the M4 microoperation (at the output of node 9.1 there is a single signal) about

In the ninth and tenth cycles, the device functions in the same way as in

five

five

0 5

0 5

2110

seventh and eighth cycles. In the eleventh cycle, MK1-5 is output to the first object and the second control object is released (the signal at the output of node 9.1 disappears). In the twelfth cycle, an MC2-4 is output to the second object.

Claims (2)

Invention Formula 1. Multi-microprogramming control unit containing a microinstructions memory block, from the first to the Nth address registers, from the first to the Nth registers of logic conditions codes, microinstructions register, end of operation register, control trigger, counter, clock generator, address multiplexer , logic conditions multiplexer, first and second logic conditions multiplexers, blocking signal multiplexer, demultiplexer, decoder, first to Nth switches, first AND group, OR group, OR elements, OR, NAND, and the device start input is connected to the first inputs of the OR elements of the first group, the outputs of which are connected to the synchronization inputs, from the first to the Nth address registers, respectively, the outputs from the first to the Nth address registers are connected to the informational ones the multiplexer inputs of the address, from the first to (t − 1) -th outputs of which (where ha is the number of bits of the address code . microinstructions) are connected to the unmodified address bits of the microinstruction memory block, and the tth output of the multiplexer address is connected to the first input of the first OR element, the output of which is connected to the microinstruction memory block’s input address, the microcommand microcommand code output connected to the information input of the register of micro-instructions, the output of the micro-operations of which is connected to the information input of the de-multiplexer; the output of the sign of the end of the operation of the register of micro-instructions is connected to the control inputs of the first to the Nth switch, the output of the address code of the next microcommand of the register of microcommands is connected to the first INFORMATION inputs from the first to the Nth switch, the output of the code to be checked -logical condition of the micro-command register is connected to the information inputs from the first to the N-th register of koi12 For logical conditions, the outputs from the first to the Nth registers of logical conditions codes are connected to the informational inputs of the multiplexer of logical conditions codes whose output is connected to the control input of the first logical conditions multiplexer; the output of the first logical conditions multiplexer is connected to the second input of the first element OR inputs the logical conditions of the first group of devices are connected to the information inputs of the second multiplexer logical conditions, the output of which is connected to the information input m of the first multiplexer of logic conditions, the inputs of the logical conditions of the second group of the device are connected to the information inputs of the multiplexer of the blocking signals, the first output of the clock generator is connected to the first input of the And element, the second output of the clock generator of the first group, the third output of the clock pulse generator is connected to the input of the installation of the microinstruction register to zero and to the counter input of the counter, the output of which is connected to the control inputs of the multiplex A pair of blocking signals, a demultiplexer, an address multiplexer, a second logical conditions multiplexer and a decoder information input, from the first to Nth outputs of the decoder, are connected to the second inputs of the same name elements of the first group, the outputs of which are connected to the second inputs of the OR elements of the first. groups, with synchronization inputs from the first to the N-th registers of logical conditions, respectively,; the inputs of the device command codes are connected to the second information inputs from the first to the Nth switch, differing in that, in order to increase its speed, the first to the Nth node of the information blocking information is entered into it, from the second to the fourth elements And, the second and third groups of elements OR, and the inputs of the command codes of the device are connected to the inputs of the elements OR of the second group, the outputs of which are connected to the first inputs of the elements AND of the second group, the outputs of the decoder are connected to the first groups of information inputs from the first to the Nth block of information analysis of blocking, with the first inputs. 21 12 elements of the third and fourth groups, the outputs of the elements of the third group are connected to the first inputs of the elements OR of the third group, the outputs of which are connected to the second inputs of the elements of the second group, the outputs of the elements AND of the second group are connected to the installation inputs of the corresponding bits of the register The inverse outputs of which are connected to the inputs of the NAND element, the output of the NAND element is connected to the trigger input of the pulse generator, the fourth output of which is connected by the synchronization input of the control trigger whose output is connected to the first input of the second element OR whose output is connected to the third inputs of the AND elements of the first group and to the second input of the AND element, the output of the AND element is connected to the synchronization input of the micro-register register, the output of the end of the micro-command register operation is connected to the second inputs of the AND third elements group, the output of the sign of the end of the register of micro-commands is connected to the second inputs of the elements of the fourth group, the outputs of which are connected to the inputs of the settings to zero of the corresponding bits of the register of the end p Work, the device start input is connected to the second inputs of the elements of the third group, the output of the blocking signal multiplexer is connected to the information input of the control trigger, the outputs of the micro-operation lock code, mask code and micro-command code of the micro-instructions memory block are connected to the second, third, fourth groups of information inputs from the first to the Nth block of information analysis of blocking, the outputs of the block of analysis of blocking information from the first to the Nth block are connected respectively to the second to N + 1th inputs of the second element ORT, the demultiplexer outputs are from the first to the Nth outputs of the device microoperations signals, the fourth output of the clock generator is connected to the synchronization inputs of the first to Nth blocking information analysis nodes, the reset inputs of which are connected to the output of the blocking release feature microinstructions memory block. 2. The device according to claim 1, wherein the blocking information block ANALYSIS node contains a mask register, a lockable micro-operation code register, a switch, a multiplexer, the first, second and third groups of AND elements, and the i-th (i et, N) information the input of the first group of the node is connected to the first inputs of the elements of the first and second groups, the N information inputs of the first group of the node are connected to the control inputs of the switch, the outputs of the elements of the first group are connected to the installation inputs of the corresponding block of the code block register my uop, straight outputs are connected to first inputs of AND gates of the third group, vkody elements and the third group are connected to yn ravl yuschimi multiplexer inputs, whose output is connected to the output kt la, .informatsionnye inputs of the second group 29. 23.1: g L 3D O1b J7. 23./V P1 11.1 37 ha yiM The node points are connected to the second inputs of the elements of the first group, the information inputs of the third group of the node are connected to the second inputs of the elements. 5 And the second group, the outputs of which are connected to the installation inputs to the unit of the corresponding bits of the mask code register, the direct outputs of which are connected to the information inputs of the commOutator, the outputs of which are connected to the second inputs of the AND elements of the third group, the reset input of the node is connected to the installation inputs register zero of the blocking micro-operation and register 15 of the mask code, the information inputs of the fourth node group are connected to the information inputs of the multiplexer, and the node synchronization input is connected to the third inputs of the AND elements of the first and second groups. 19.1 04 20.1 2.1 13JL. 20.f / lk.N 28 5M U2.2 (pu2.5 a 5 and t 17 Phi2. 25 five fff 52./ g " On 52.W J5 Ate 35 P 36 A1-i X A / -2 A2H Aeg) Lee 27 f МК2-1 V 46 2J (Ptf a5 one P P P P D2-2 A A2-3 AF2 HSC) A2-2XAf-Z UMK2- t 6