SU1161942A1 - Multiprogram control device - Google Patents

Abstract

MULTI-MICROPROTTAMIC DEVICE 71 EQUIPMENT, containing a microinstructions memory block, N address registers, microinstruction register, address multiplexer, first logical conditions multiplexer, demultiplexer, clock generator, first control trigger, -ShSh element and two elements And, and an input input, input, and. the output of the first control trigger is connected respectively to the start input of the device, the output of the first element I and the input of the clock generator, the output of which is connected to the first input of the second element And, the output of the microinstructions memory is connected to the information input of the register of microinstructions, the output of the field of microoperations of which is connected to the informational input of the demultiplexer, the i- and the output of the demultipexor

Description

The inputs of the first multiplexer of logical conditions are connected to the outputs of the logical conditions code and the second multihexor of logical conditions, respectively, the control input of which is connected to the output of the counter, the t-th information input of the second multiplexer of logical conditions is connected to the i-th input of the logical conditions of the device, the first and the second information inputs, the control input and the input of the i-ro switch are connected respectively to the 1st input of the operation code of the device, the output of the address and the output of the floor-end com IDs of the microinstructions register and the information input of the i-ro address register, the synchronous input of which is connected to the output of the 1st OR element of the group, the first and second inputs of which are connected respectively to the device start input and the i-th output of the second decoder, the information input and output of the first decoder are connected respectively, with the output of the end of the microinstructions register and the input of the end of the register, the output of which is connected to the input of the first element I, the synchronous input, the information input and the output of the 1st register of the code of logical conditions with Dineny respectively with the i-th output of the second decoder, the output of the logical conditions of the register of micro-, commands and the 1st information input multiplexer logic code conditions, the first information input of the multiplexer ready signals connected to the 1st input signal of the device, the multiplexer output ready signals are connected to the inverse input of the prohibition element and the first inputs of the NAND element and the third element AND, the second and third inputs and the output of which are connected respectively to the zero output of the lock trigger , the second output of the sync pulse generator and the installation input of the second control trigger, the first and second inputs and the output of the fourth element And are respectively connected to the single output of the unlock trigger, the second output of the sync pulse generator and the input of the delay element whose code is connected to the reset input of the unlock trigger, the second input and the output of the element is NOT connected, respectively, with a single output of the blocking trigger and the input of the second one-oscillator, the output of which is connected to the input of the trigger setup is unlocked irovki, straight input and output barring member connected respectively to the second output of the clock generator and the first input of the fifth AND gate, the second inputs of the second and fifth AND gates are connected to the zero output of the lock latch, the output of the fifth AND gate is connected to the clock register. micro-commands and blocking trigger, the reset input and information input of which are connected respectively to the output of the fourth element AND and the output of the blocking flag of the microcommand memory block, and the first and second inputs and code of the sixth element AND are connected respectively to the output of the second element AND, zero output of the second control trigger and the control input of the second decoder.

The invention relates to digital computing and can be used in the design of multi- microprogramming control systems with complex identical objects.

The purpose of the invention is to increase the speed of the device by using the natural temporal redundancy of the object to control it in parallel.

FIG. 1 shows a functional diagram of the proposed multi-micro control device in FIG. 2 - time diagrams of the device; in fig. 3 - the algorithm of the device.

The multi-microprogram control unit contains a block of 1 memory of micro-commands, the first one is the N-th register 2. 1-2. N addresses, first - N, and registers 3. 1-3. N code of logical conditions, register of 4 micro-commands with the end field of command B, end of operation 6, address 7, micro-operations 8, logical conditions 9, register 10 of end of operation, counter 11, multiplexer 12 addresses, first multiplexer 13 logical conditions, multiplexer 14 code logical conditions, the second multiplexer 15 logical conditions, the multiplexer 16 readiness signals, the demultiplexer 17, the first - N -and switch 18. 1-18. N, the second decoder 19,. the first decoder 20, the generator 21 clock pulses, the first 22 and second 23 control triggers, the lock trigger 24, the unlock trigger 25 a group of elements OR 26. 1-26 N, element OR 27, first 28, second 29, seventh 30 AND elements, prohibition element 31, sixth 32, fifth 33 and fourth 34 AND elements, AND-HE element 35, first one-shot 36, second one-shot 37, delay element 38 element NOT 39.  The device has the first - N - and inputs 40. 1-40. N opcodes, device input 41 start devices first - N -and input 42. 1-42.  The N values of the logical conditions of the device are the first —N — and inputs 43. 1-43. N signal readiness device, the first N-th outputs 44. 1-44. The first N controls are N th objects, respectively, the first 45. 1 and second 45. 2 generator outputs 21 clock pulses, the output 46 of the modifiable address bit of the address multiplexer 12, the output 47 of the element OR 27, the output 48 of the blocking indication of the block 1.  FIG.  2 shows the timing diagram of the device in three main modes.  To specify the time. The following basic data are taken from the device operation diagrams: the number of control objects. four; in the second cycle of operation of the device, the second control object is occupied; ; signal. readiness of the second control object comes asynchronously in the eighth cycle of the device; the mode of blocking the operation of the multimicroprogram control unit is realized by the third control object; the readiness signal of the third control object arrives asynchronously in the thirteenth cycle of the device operation. I 424 The multi-microprogram control unit contains three groups of hardware.  The means of storing and forming micro-commands include block 1, register 4 micro-commands, blocking trigger 24.  Unit 1 is designed to store the management firmware of the first N-M control objects.  Register 4 is designed to record microinstructions read from block 1.  The trigger 24 is designed to store a special label blocking the operation of the multimicroprogram control device for the execution time of the current microcommand by one of the N control objects.  The means of forming the address are registers 2. . f, registers 3. 1-3. N, multiplexers 12-15 and the element OR 27.  Registers 2. 1-2. N are intended for recording operation codes received at inputs 40. 1-40. N operation codes, or micro-instruction addresses, which will be read from block 1.  Registers 3. 1tZ. M are intended for recording the codes of logical conditions coming from the field 9 of register 4.  The multiplexer 12 is designed to switch the addresses of micro-instructions coming from the registers 2. 1-2. N addresses, depending on the number of the object of the poisoning coming from the counter 11.  Multiplexer 12 implements the following system of logical functions: N i. “, -. Ki -, i y, L P V where m is the value of the m-th address bit in the i-th address register; x  V-.  where I Kj - if in the corresponding discharge of the counter 1 1 recorded K; - if the corresponding discharge of the counter 11 is recorded O,. , - n - register width 2. 1-2. N; 5 M is the number of bits of the counter 11, with 2 H - N - 1; N is the number of control objects. The multiplexer 15 is intended for switching, depending on the number of the control object, of logical values. conditions coming on input 42. 1-42. N device.  The device readiness signal is one of the logic conditions supplied to the inputs 42. N device.  Multiplexer 15 implements the following system of logical functions: -v.  B, V.  ; . where t m is the bit level of the logic level at the input 42. i devices; KL K.  / m is the number of bits of logical conditions arriving at inputs 42.1-42. N devices Multiplexer14 is intended for switching the codes of logical conditions coming from registers 3. 1-3 devices.  The multiplexer 14 commutes passing the logical condition code of register 3. 1-3. N depending on the number of the object entering the input of the multiplexer from the counter 11.  Multiplexer 14 implements the following system of logic functions,. , ,, N. , K -.  four .    where is the value of the E-th bit of the logic conditions code in 3. i register of devices "P K. L K.    R - register width 5. 1-3. N.  42 6, the multiplexer 13 is designed to select one of the 6 values of the logical conditions supplied to the input of the multiplexer 13 from the output of the multiplexer 15.  The choice of the value of the logical condition occurs depending on the code Cp of the logical condition coming from the output of the multiplexer 14.  The multiplexer 15 implements the logical function V, if in the corresponding discharge of the code of logical conditions input to the multiplexer 15 is recorded if in the corresponding discharge of the code of logical conditions recorded O.  The control and synchronization means include register 10, counter 11, multiplexer 16, demultiplexer 1-7, switches 18. 1 -18.  N, decoder 19 and 20, generator 21, trigger 22, trigger 23, trigger 25, OR elements 26. 126. N, elements And 28-30, 32-34, prohibition element 31, AND-NO element 35, one-shot 36 and 37, delay element 38, element NO 39.  Register 10 is used to record the signals of the end of the firmware of the first - control object.  Counter 11 is intended to determine the number of the first -N-ro I object of control.  Counter 11 has a conversion factor of N, where N is the number of control objects.  The overflow signal is an internal counter signal.  After the number of pulses equal to N is entered at the C input of the counter 11, the counter returns to the initial state, and the cycle of the device is repeated.  The multiplexer 16 is designed for switching the signals of control objects.  It implements the logical function N. where is the i-ro occupancy signal of the control object; TO.  L K.  .  one . 1 Demultiplexer 17 is designed to detect micro-operations from the output of field 8. register 4 on.  one of the exits 44. 1-44. N control device.  The demultiplexer 17 implements the following system of logical functions L: Pv, 4, Pl. K, where t, N are numbers of control objects; L is the field size of the microscope of register 8; register 4; .  The device operates in the following modes: microprogram control in the presence of ready signals from objects; implementation of firmware control in the presence of signals of control objects; blocking multimicroprogram operation a lot of control device.  The mode of implementation of firmware control in the presence of readiness signals from objects.  In the initial state, all the triggers, registers, and the counter are in the zero state (input; E1Y reset registers 2.  and 3. ;, 10 counter 11 and the register setup input 4 in FIG.  1 not shown).  In field 5 of register 4: microinstructions recorded unit.  In block 1, the microprograms are recorded that impede the operation of the first N control objects.  The operation of the device begins with the filing of the start signal at the start input 41.  As a result, the trigger 22 is set to one and the generator 21 is started.  Start signal, passage through groups of elements OR, 26; 1-26. N and entering the inputs of registers 2. 1-2. N, records in these registers the operation codes (the initial addresses of the microprograms), which come from the outputs of the switches 18. 1-18. N. , Switches 18. 1-18. N allow the execution of operation codes from inputs 40. 1-40. N at receipt from floor 5 of register 4 of a single signal.  Koshl operations with the outputs of registers 2. 1-2. N addresses are sent to the information inputs of multiplexer 12.  At the same time, from the output of the counter 11, the control input of the multiplexer 12 receives a control signal (the number of the first control object), which allows the operation code to pass from register 2. 1 to the multiplexer output 12.  The operation code from the output of the multiplexer 12 is fed to the input of block 1.  As a result, from block 1, the first microcommand MK1-1 of the first control object is read out and fed to register 4.  Clock signal from output 45. 2 generator 21, the passage through the elements 31 and 32, writes it to the register 4.  The resolution signal for element 31 is the zero signal from the output of multiplexer 16,: for element 32, the single signal jC of the zero output of trigger 24.  In addition, the sync signal and the output of the element 2 is fed to the trigger input confirming the initial state of the trigger, since from the output 24 of the block 1 blocking sign to the D input of the trigger 24 a zero signal is received.  From the output of field 5 of the register of 4 micro-commands, the zero signal allows the passage of the address of the following micro-command MK2-G through the switches 18. 118. N at the input of registers 2. 1-2. N of the address received by the field 7 of the register address of 4 microinstructions.  The code of logical conditions from the output of the floor 9 of the register 4 micro-instructions is fed to the inputs of the registers 3. 1-3. N.  The micro-operations signals from the output of the field 8 of register 4 arrive at the information input of the demultipexor 17 at the same time as the signal (number of the first object) from the counter 11 arrives at its control input.  As a result, the signals of the microoperations of the G1-1 micro-command are fed to the input 44. 1, t. e.  on the first control object.  With the arrival of signals from the micro-operator to the first control object at the input 43. In Fig. 1, the control signal for the first control object appears at the input of the multiplex 16.  The control of the input of the multiplexer 16 receives a signal from the counter 1 1, as a result of the single busy signal of the first object, as indicated at the output of the multiplexer 16, prohibits the passage of a clock signal t through the element 31.  The busy signal arriving at the input of the element 35 from the output of the multiplexer 16 does not change the state of the one-shot 37, since the second input of the element 35 receives a zero signal from the output of the trigger 24.  In addition, the busy signal does not pass through element 34 due to the absence of a clock signal t at its input.  After passing to exit 44. 1 micro-output signals 45. 1 clock signal T2 is the clock signal Tj, which, passing through elements 29 and 30, is fed to the first input of the decoder 19, to the second input of which enters the number of the first control object from counter 11 (the counter is in zero, state).  From the output of the decoder 19, the signal enters through the element 26. 1 to register C-input 2. 1 addresses As a result, in the register 2. 1 records the address of the next (second) micro-command MK1-2 of the first control object.  Simultaneously sync.   the output of element 29 is fed to the input of counter 11 and to the input of element 39. On the falling edge of the inverted sync signal, which is fed to the input of the one-oscillator 36, the latter generates a signal to reset the register 4 to the R-input of register 4.  The reset signal also arrives at the R input of trigger 23, confirming its initial (zero) state.  On the trailing edge of the sync signal, one is recorded in the counter (the number of the second control object. . . ).  Simultaneously with the recording of the address of the micro-command MK1-2 in the register2. 1 the logical conditions code comes along on the leading edge of the synchronization signal 2, coming from the output of field 9 of register 4 to register 3. 1 code of logical conditions.  From the outputs of registers 3. 1 and 3. N on the information inputs of the multiplexer 14 receives the codes of logical conditions.  The number of the first control object from counter 11, coming in (to the control input of multiplexer 14), allows the logical condition code to pass from the output of register 3. one.  As a result, the logical condition code from the output of the multiplexer 14 is fed to the control input of the multiplexer 13.  At the same time, multiplexer 15 permits the passage of the logical condition value from input 42. 1 device, since the Hot-iep of the first object arrives at the control input of the multiplexer.  From the output of the multiplexer, 15 values of the logical conditions are fed to the information input of the multiplexer 13.  Thus, according to the first clock pulse G, the microcommand MK1-1 is written to register 4 and transmitted to the first control object; recording information in the trigger 24; the micro-operations performed by the first control object, the arrival of a single busy signal at the input of the multiplexer 16.  On the first clock pulse fj, the address of the microcommand MK1-2 and the code of logical conditions are written to registers 2. 1 and 3. 1, respectively; reset register 4 and confirm the initial state of the trigger 23 on the falling edge Tj; write the unit to counter 11, in which the number of the second control object is set on the falling edge LJ.  By the second clock pulses f and the operation of the multi-microprocessor control device is similar to the operation of the device by the first clock pulses ц In register 4, the first micro-command MK2-1 of the second control object is recorded and recorded in register 2. 2 addresses of the next (second) micro-command MC2-2 of the second control object.  The (W + 1) -M cycle in register 4 contains the micro-command MK1-2 and so on. d.  The counter 11 is reset to the zero state by an overflow signal occurring in the (N-I) -M cycle of operation of the multi-microprogrammed control device.  Upon completion of the execution of the firmware stored in block 1, from the output of field 5 of register 4 to the input of switch 18. i enters a single End command, which allows the passage to register 2, i of the address of the next opcode.  Upon completion of the i-ro operation of the control object, a single signal arrives from the output of field 6 of the register to the input of the decoder 20 End of operation.  The control input of the decoder 20 from the output of the counter 11 receives the i-ro number of the control object.  From the output of the decoder 20, the signal End of operation is recorded in the i-th trigger of register 10.  When writing to all the triggers of the register of 10 single signals, the operation horse at the inputs of the 2: 8 element has single signals that trigger the reset signal of the trigger 22 to the zero state.  A zero signal, arriving at the input of the generator 21, stops the generation of the clock signals by the generator c and 2 by this generator.  Thus, the device finishes its work.  The mode of implementation of the firmware control under the condition that the control object is occupied.  The operation of the multi-microprogram control device in this mode differs from that considered in that if the control object is occupied (the control object did not have time to finish the work on the previous micro command), the following microcodes of this object are not recorded in register 4.  Suppose that the (M + 2) th operation cycle of the device, the second control object was found to be z, t. e.  at the entrance 43. 2 signals g. . There is a single signal present at the input of the multiplexer 16.  From the output of the multiplexer 16, a single busy signal arriving at the inverse of the input element 31, prohibits the passage of a clock signal to the input of the register 4 and to the C input of the trigger 24 through the element 32.  As a result, the recording of information (micro-commands MK2-2) in register 4 and trigger 24 does not occur.  The clock pulse T, having passed through the element 34, sets the trigger 23 to one state.  A zero signal from its zero output prohibits the passage of a clock signal 2 through element 30.  The clock signal tc output element 30 to the input of the decoder 19 is not received, and therefore, it is prohibited to write the address of the following micro-command MK2-3 in register 2. 2 and the code of logical conditions in the register 3. 2 of register 4 (register 4 was zero on the previous clock signal).  On the trailing edge of the sync signal f, the number code of the third control object is written into the counter 11.  On the falling edge of the inverted sync signal D2, at the output of the one-shot 36, a signal is generated that confirms the initial (zero) state of the register 4 and sets the trigger 23 to the zero state.  In the following, (N + 3) -M, the operation cycle of the multimicroprogram control device, a zero signal is present at the output of the multiplexer 16.  Counter 11 records the number of the third control object.  Using the sync signal f to register 4, the microcomputer MKZ-2 is recorded and micro-operations are transmitted to the third control object, and the operation of the device is subsequently similar to the operation in the first mode.  If by the time of the (2N + 2) -ro cycle of operation the second control object completes the microoperations of the micro-command MK2-1, then at input 43.2 there is a zero readiness signal of the second control object that allows the micro-command MK2-2 to be written to register 4.  Thus, when the R-ro control object is occupied on the 1st cycle of the device operation, the MKR-i micro-command is not written to register 4.  In subsequent cycles, the operation of the device is similar to the operation in the first mode.  The mode of blocking the operation of the multimicroprogram control device.  The device enters this mode of operation when a single signal appears at the output 48 of block 1.  A single signal from the output 48 enters the D-input of the trigger 24.  With the arrival of the sync pulse f at the input of the trigger 24, the latter is transferred to the one state, Simultaneously, but into the p. Register 4 from block 1 is a regular microcommand.  From entrance 43. i a single occupation signal through the multiplexer 16 is fed to the inputs of the elements 31 and 35.  By entering the inversion input element 31, a single occupancy signal prohibits the passage of sync pulses f through element 31.  As a result of the arrival at the inputs of element 35 of a single occupancy signal and of a single signal from flip-flop 24, a zero signal is present at the top of element 35.  A zero signal from the output of the trigger 24 arriving at the input of the element 29, prohibits the passage of the clock pulses t2 through this element.  Thus, the device enters the blocking mode with recording the unit to the trigger 24 (the receipt of the clock pulses f2 is blocked) and with the arrival of the busy signal at the input 43. i control (blocking the passage of clock pulses)

The unlocking of the device is performed by the following technical means: one-shot 37, trigger 25, element 33 and delay element 38.

Unlocking the device occurs in the following way.

After completing the back; The control object sends to the control input 43.1 a zero readiness signal. The zero signal from the output of multiplexer 16 is fed to the input of element 35. As a result, a single signal is formed at the output of element 35. A single-oscillator 37, responding to a change in potential at the input from low to high, generates a single unlock signal at the output, which, arriving at the trigger 25, sets it to the unit state. A single signal from the output of the trigger 25 postztat to the input of the element 33 and, thereby.

permits the passage of a sync pulse to the f-input of the trigger 24. The sync pulse t, arriving at the R-input of the trigger 24, transfers it to the zero state. A single signal from the output of the trigger 24, arriving at the input of the element 29, allows the passage of clock pulses 2, as well as entering the input of the element 32, allows the passage of clock pulses f, from the output of the element 31, to the inverse input of which the zero ready signal from the output of the multiplexer 16 comes. The clock pulse t from the output of the element 33, which is delayed by the element 38 for the duration of its duration, arriving at the P input of the trigger 25, sets the latter to the zero state. The zero signal from the output of the trigger 25, is fed to the input of the element 33, prohibits

passage of clock pulses.

through

this item. After unlocking, the operation of the multi-microprogrammed control unit continues in the same way as in the first two modes of operation.

Thus, the invention allows to increase the speed due to the possibility of simultaneous execution and issuance of micro-commands to a group of parallel controlled objects. With MOTOR1, the natural temporal redundancy of control objects is used based on the combination of the phases of execution and the execution of micro-instructions in parallel to the implemented branching microprograms.

D JL 1. i.

ex r rO; five .

tf S csi ro e r rrj "si

51 jty

NJ

eu

&

r CNJ c

- 5 to 5 to "

1.Einish kooo5 oriepoi uu in p histo |

2 Vydchchch sherrDioi o5vvlp1) 1. (G1roR) yeni

Sopchgv oEreso

 3onucb-hot) o «peroscipher MIS 6 u, uu 8 register i register .i

 Ostanob

Mr. Jaiapo

g g

MK. i- Ml)

By / Ie S KGit

KG W 28

KSt

r HOfluj Sagna / "g on S 4 dfV3ii

s5ros mpueeeoo 2.1

(End of Yig.L

Claims (1)

MULTIMICRO PROGRAM CONTROL DEVICE containing a memory block of microcommands, N address registers, a register of microcommands, an address multiplexer, a first logic condition multiplexer, a demultiplexer, a clock generator, a first control trigger, an OR element, and two AND elements, with the installation input, reset input, and output. trigger control are connected respectively to the start input of the device, the output of the first AND element and the input of the clock generator, the output of which is connected to the first input of the second And element, microinstruction storage unit coupled to the data input of the register! microcommands, the microoperation field output of which is connected to the information input of the demultiplexer, the ith output of the demultiplexer (1 Ν) is connected to the ϊth output of the device, the output of the 1st address register is connected to the ϊth information input of the multiplexer ^! addresses, outputs of non-modifiable bits of the group of outputs of which are connected to the inputs of non-modifiable bits of the group. address inputs of the memory block of the microcommands, the first and second inputs and the output of the OR element are connected respectively to the output of the modifiable bit of the group of outputs of the address multiplexer, the output of the first logic condition multiplexer and the input of the modifiable discharge group of address inputs of the micro-memory memory block, characterized in that, in order to improve performance, it contains N logical condition code registers , end-of-operation register, counter, second logical condition multiplexer, logical condition code multiplexer, ready signal multiplexer, K switches, two decoders, second control trigger, lock trigger, unlock trigger, OR group of elements, third, fourth, fifth and sixth AND elements , element ·? · inhibit element, AND-NOT element, two one-shot elements, delay element and NOT element, the input and output of which are connected to the output of the second AND element and the input of the first one-shot, the output of which is connected to the input m reset the micro command register and the second control trigger, the counter counter input is connected to the output of the second AND element, and the counter output is connected to the control inputs of the first decoder, address multiplexer, logical condition code multiplexer, ready signal multiplexer, demultiplexer, and second decryption information input: the rotor, control and information inputs of the first logic condition multiplexer are connected to the outputs of the logic condition code multiplexer and the second logic multiplexer, respectively conditions, the control input of which is connected to the output of the counter, the j-th information input of the second logical condition multiplexer is connected to the i-th input of the values of the logical conditions of the device, the first and second information inputs, the control input and output of the i-ro switch are connected respectively to i- the input of the device operation code, the output of the address field and the output of the end field of the micro register command of which are connected respectively to the start input of the device and the ith output of the second decoder, the information input and the output of the first decoder are connected respectively to the output of the end-of-field field of the micro-command register and the input of the end-of-operation register, the output of which is connected to the input of the first element And, sync input, information input and the output of the ί-th register of the code of logical conditions is connected respectively with the i-th output of the second decoder, the output of the field of logical conditions of the register of micro-, commands and the i-th information input of the code multiplexer logical conditions, the 1st information input of the ready signals multiplexer is connected to the ί-th input of the device ready signal, the output of the ready signals multiplexer is connected to the inverse input of the inhibit element and the first inputs of the AND gate and the third AND element, the second and third inputs and output which are connected respectively to the zero output of the lock trigger, the second output of the clock generator and the installation input of the second control trigger, the first and second inputs and the output of the fourth element And are connected respectively with the single output of the trigger trigger, the second output of the clock generator and the input of the delay element, the output of which is connected to the reset input of the unlock trigger, the second input and the output of the AND gate are connected respectively to the single output of the trigger trigger and the input of the second one-shot, the output of which is connected to the unlock trigger installation input, the direct input and output of the inhibit element are connected respectively to the second output of the clock generator I and the first input of the fifth element And, the second inputs the second and fifth elements AND are connected to the zero output of the blocking trigger, the output of the fifth element And is connected to the sync inputs of the microcontrol register and the blocking trigger, the reset input and information input of which are connected respectively to the output of the fourth element And and the output of the blocking indicator of the micro memory block, and the first and second the inputs and output of the sixth element And are connected respectively to the output of the second element And, the zero output of the second control trigger and the control input of the second decoder.