SU1555705A1 - Device for shaping test actions - Google Patents

Abstract

The purpose of the invention is to improve the quality of tests by increasing the likelihood of detecting errors, as well as expanding the field of application by providing applicability to devices with a variety of formats and a wide range of commands. The device contains a clock pulse generator, random code generator, trigger trigger, AND element, test register, test code generation unit

The test code generation unit contains a decoder, a register, a control trigger, the first AND element and an OR element. Additionally, N blocks of word formation of the test set (where N is the number of layers in the format of a test command) are entered, and the I-th (I = 1 ... N) block forming the word of the test set contains a decoder, the AND element, the OR element, the register and the trigger .

Description

first to (M-1) -th sets are connected to the second inputs of the decoders of the second and N-th word formation blocks of the test set, respectively; direct trigger output of the N-th word formation block of the test set is connected to the first input of the element And, the output of which is connected to the synchronous input of the test register, as well as to the R inputs of the triggers of all blocks of forming the word of the test set, the group of outputs of the registers of all the blocks of forming the word of the test set is connected to groups of information inputs of the register of the test with the second o (N + l) -io, respectively, the second output of the clock generator is connected to the second input of the AND element, the second inputs of the AND elements of all the blocks of forming the word of the test set and the first input of the AND block of the test code forming unit, the output of the OR element of the test code forming block with the second input of the AND block of the formation of the test code, the output of the AND block of the formation of the test code is connected to the synchronous input of the register and the S-input of the trigger of the control unit of the formation of the test code, the inverse output of the trigger of the control block The formation of the test code is connected to the enable input of the decoder of the test code generation block.

The invention relates to computing and instrumentation technology and can be used to build systems, test and test devices for converting and processing information of modern computing systems.

For modern devices of information conversion and processing, for example, computer processors, a wide range of computer codes, differing in the number of operand fields, is typical. In addition, for each type of instruction, such as register-register, register memory, etc., there is a characteristic relationship between the operation code and the allowable range of changes in the values of the operands.

Therefore, if the specified features are not taken into account, then commands with a valid operation code (test), but with forbidden codes (values) of the operands of the word, predominate in the test sequence being formed. As a result, the emergency stop of the object under control increases sharply. This leads to the fact that the testing time increases and, in addition, the diagnostic abilities that significantly determine the quality of the test are reduced, since after each emergency stop it is necessary to set the object to its initial state.

Due to frequent interruptions of a sequence of commands, the probability of detecting errors that

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still occur on long sequences of test commands, and are therefore difficult to detect,

The purpose of the invention is to improve the quality of the test by increasing the likelihood of detecting errors, as well as expanding the scope of application by providing applicability in devices with different formats, and a large range of commands.

The introduction of the first and N-ro units of the formation of the word of the test set (where N is the number of words in the format of the test command) allows to form the required number of words (operands) in the format of the test command. In addition, the formation of words provided by the aggregate of the elements and nodes of each test word formation block is carried out taking into account the allowable set of their values, determined by the test code of the formed test command. The latter advantage is also achieved by connecting the outputs of the register of the test code generation block containing the test code of the generated test command to the first groups of information inputs of the registers of each word formation block. As a result, the number of interruptions in the test sequence of test commands is sharply reduced, as a result of which the quality of the test is improved by increasing the probability of detecting errors occurring on long sequences of test commands and increasing

There is a device application area in control systems for checking information processing and transformation devices, such as computer processors, which have a wide variety of formats and a wide range of commands.

The drawing shows a functional diagram of the proposed device.

The device contains a test code generation block 1, the first 2,1-N th 2.N blocks of word formation of a test set, test register 3, trigger 4, generator 5 random codes, generator 6 clock pulses, element 7.

In addition, block 1 contains a register 8, a control trigger 9, a decoder 10, an AND 11 element, and an OR 12 element.

The composition of each of blocks 2.1-2.N is identical to the composition of block 2.1, which contains the register 13.1, trigger 14.1, decoder 15.1, element AND 16.1 and element OR 17 „1.

In addition, the diagram denotes start 18 and stop 19, output group 20, - output group 21 of generator 5, output group 22 of register 8, inputs 23.1-23.N of decoders 15.1-15 "N blocks 2.1-2.N respectively, groups of outputs 24.1-24.N of registers 13. 1-13.Kblokov 2. 1-2.NCOOT- correspondingly, outputs 25.1 and 25.2 of the generator.

Block 1 is designed to form a test command test code in register 8, a decoder 10 - to select the allowed test code among the codes received at its input 21 from the generator 5 output. This decoder is triggered when there is a permit.

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signal at the V-input from the trigger output

9, which is removed after selection

valid test code.

The element OR 12 is used to generate a write enable signal to the register 8 when the output de

encoder 10, the corresponding permission of the 50 command. However, such a decision is attached to the operation code.

The trigger 9 is designed to enable (prohibit) the operation of the decoder 10 (15.1) when prohibiting (enabling) the operation of the decoder 15.1 (10).

Register 3 is intended to compose the format of a test command generated by the device. Write in it

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It would be possible to reduce the device performance (command generation frequency in register 3) by increasing the repetition period of valid codes in the bits of the output generation code. torus 5 corresponding to the specified command format fields.

Consecutive blocking

, Cove 1 and 2.1 is necessary due to the existence of 55705

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The words from outputs 22, 24.1-24.N of registers 8, 13.1-13.N are written after completion of the formation of the N-ro word of the test set, which identifies the appearance of the signal from single output 23 (N + 1) of trigger 14.N of block 2. N.

Oscillator 6 is designed to form on its outputs 25.1 and 25.2 of two sequences of clock pulses that are shifted relative to each other.

Random code generator 5 is a computing computing node. It can be performed, for example, on a shift register with a modulo-two sum element in feedback, which allows the formation of a pseudo-random sequence of codes.

Element I 7 is designed to form a zero-setting signal for triggers 9 and 14.1-14.N of blocks 1, 2.1-2.N, as well as a write signal to register 3 upon completion of the formation of the last (N-ro) word.

Block 2, i (i 6 1, N) is designed to form the code of the 1st word of the test set (command), register 13.1 - to store the code of the 1st word of the test set (command), triggers 14. -14. ( N-1) —for ensuring the sequential generation of the test instruction word codes.

With this functional diagram of a device with one generator 5, the output code of which is equal to the maximum width of the test code or words in the test, sequential formation of operand codes is necessary to prevent simultaneous operation of more than one block 2.1 and the formation of the same word codes as a result.

An alternative solution to this is to extend the code at the output of generator 5 to a value equal to the size of the full test format.

50 teams. However, such a decision is welcome.

It would be possible to reduce the device performance (command generation frequency in register 3) by increasing the repetition period of valid codes in the bits of the output generation code. torus 5 corresponding to the specified command format fields.

Consecutive blocking

, kov 1 and 2.1 is necessary due to the existence of a relationship between the valid test code and the set of corresponding word codes,

Decoders 15.1-15.N are designed to identify the allowed code received at input D 2, depending on the test code of the generated test command, which goes to output D 1. The decoders 15., N are triggered when there are permissive signals at the inputs V 1 and V 2 at the same time

The device works as follows.

The principle of operation of the device consists in sequential identification by the storage unit 1 of the first allowed operation code in a random sequence of codes generated by generator 5, in the identification of codes generated by generator 5, in identifying and fixing the allowed operand codes successively with blocks 2 1 1- 2.N. It is assumed that the command format contains V + 1 fields: a test code field and N word fields.

In the initial state, all the memory elements of the device are in the zero state (the circuit of the initial installation to the initial state is not shown).

When the start signal from input 18, the trigger 4 is set to one state and turns on a generator of 6 clock pulses, which starts issuing clock pulses at the outputs 25.1 and 25.2 alternately,

For each clock pulse from output 25.1, a generator of 5 random codes is triggered and, at the falling edge of this pulse, generates at the outputs 21 a regular random code, which goes to the corresponding information inputs of the decoders 10 and 15.1 - 15.N and registers 8 and 13.1- 13.N. At the beginning of the next test command generation stage, the decoder 10 (15.1-15.N is open (closed) by a signal from the zero (single) output of trigger 9 (flip-flops 9 and 14.1-14. (N-1). Therefore, when the first random number arrives to the inputs of the 21 decoder

10, corresponding to the allowed operation code, the OR 12 element is triggered, which opens the AND 11 element.

The second second clock pulse from the output 25.2 of generator 6 triggers element 11, the output signal of which allows the code from the outputs 21 of generator 5 to register 8 of the test code to be written, and also the flip-flop 9 sets the zero state on the trailing edge of the pulse, which closes opens the decoder 10 (15.1) signal from the zero (single) output 23.1, entering the input V (V 2) of the specified decoder.

After that, the formation of the words of the test command begins. Each regular random code arrives at the second input of the decoder 15.1, which is opened by enabling signals at the inputs VI and V 2.

Upon receipt of the word resolution code, the OR 17.1 element is triggered and the word code is recorded in the register 13.1 of the 2.1 block and the trigger 14.1 is set to one, which disables the decoder 15.1 and resolves the decoder 15.2 of the next test generation block 2.2,

In the following, the process of forming words in blocks 2.2-2. N is repeated as described. Moreover, after writing the code of the Nth word to the register 13, N of the block 2.N, the trigger 14. also sets to the one state, closes the decoder 15.N of the block 2, K and, in addition, opens with a signal from output 23, (NH ) the element And 7, which is triggered by the next clock pulse from the output 25.2 of the generator 6, and sets in the initial state the triggers 9 and 14.1-14.N.

In addition, the output signal of the element And 7 allows the recording of information from the outputs 22 and 24, .N into the register 3, thus completing the composition of the test action command

Further, on the next clock pulse from output 25.1, the device proceeds to the formation of the next test command, which occurs similarly to that considered.

Editor N. Tupitsa

Compiled by M. Greblov

Tehred A. Kravchuk Proofreader S. Cherni

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Claims (1)

A device for generating test actions, comprising a clock generator, a random code generator, a start trigger, an AND element, a test register, a test code generating unit, the test code generating unit comprising a decoder, a register, a control trigger, a first And element and an OR element, the group of outputs of the decoder is connected to the group of inputs of the OR element, the start and stop inputs of the device are connected to the inputs S and R of the start trigger, respectively, the output of the start trigger is connected to the start input of the clock pulse generator x, the first output of which is connected to the sync input of the random code generator, the group of outputs of the random code generator is connected to the groups of information inputs of the decoder and the register of the test code generation block, the output of the And element is connected to the input R of the control trigger of the test code generation block, which is different, which, with the aim of improving the quality of tests by increasing the probability of detecting errors, as well as expanding the scope by providing the possibility of use in devices with various formats and a large nomenclature of commands, the device contains N blocks for generating the word of the test set (where N is the number of words in the format of the test command), and the ith (i = 1 ,,, Ν) block for generating the words of the test set contains a decoder, element And, element OR, a register and a trigger, and in each i-th block of word formation of the test set, the group of outputs of the decoder is connected to the group of inputs. OR element, the output of which is connected to the first input of the AND element, the output of which is connected to the register clock and S — the trigger input, R — the input of which is connected to the first decoder enable input, the group of register outputs of the test code generation unit is connected to the first groups of information inputs of decoders of the corresponding N blocks for forming the word of the test set and with the first group of information inputs of the test register, the group of outputs of which is the group of outputs of the device, the group of outputs of the generator randomly x codes are connected to the second groups of information inputs of the decoder and groups of information inputs of the registers of all test word formation blocks of the test set, the direct output of the control trigger of the test code generation block is connected to the second resolution input of the decoder of the first test set word formation blocks, the direct outputs of the trigger of the test word formation blocks - 1555705 A1 of the first set from the first to (C-1) -th is connected to the second inputs of the resolution of the decoders of the blocks of the formation of the words of the test set from the second to the Nth $, respectively, the direct output of the trigger Ντο of the block of the formation of the words of the test set is connected to the first input of the element And, the output of which is connected to the sync input of the test register, ed, and also to the R-inputs of the triggers of all test word formation blocks of the test set, the group of register outputs of all test set word formation blocks is connected to the groups of information of the test register information 15 from the second to (Ν + 1) th, respectively, the second output of the clock generator is connected to the second input of the AND element, the second inputs of the AND elements of all test word formation blocks and the first input of the AND element of the test code generation unit, the output of the OR element of the code generation unit the test is connected to the second input of the AND element of the test code generation unit, the output of the And element of the test code generation unit is connected to the register input and the S-input of the control trigger of the test code generation unit, the inverse output of the control trigger a test code generating unit is connected to an enable input of a decoder of a test code generating unit.