SU1256007A1 - Information input device - Google Patents

Abstract

The invention relates to computing. The device is intended for address input of information from subscribers and can be used in high-speed computers operating in real time. The essence of the invention is to improve the device speed and reliability of recording-reading information, which is achieved by introducing a group of triggers, a second group of email, T; Tent AND, a third group of elements Hj of the group of OR elements, an OR element, a delay element, the first and second elements OR trigger and element And connected to each other and with other elements of the device by the appropriate links. As a result, an increase in the device speed and accuracy of information input is achieved due to the detection of all errors of repeated readings to registers for writing and reading information. 2 Il. from € ke SP O5 Oh about

Description

one

The invention relates to computing and can be used in high-speed computers operating in real time.

The purpose of the invention is to increase the speed and reliability of writing-reading information.

FIG. 1 is a block diagram of an information input device; in fig. 2 - timing charts of the proposed device.

The device for entering information contains the registers 1, the decoder 2, the element OR 3, the first group of elements AND 4, the group of triggers 5, the second group of elements AND 6, the third group of elements AND 7, the group of elements OR

8, first and second elements OR

9,10, delay element 11, trigger 12, element And 13, informational

and the address inputs 14 and 15 of the device are inputs 16 and 17 of the read and write permission; Devices, informational outputs 18 of the device, prohibiting the operation of device 19, output 20 of the device availability

The information input device operates as follows.

In the initial state, the registers 1, the triggers 5 and the trigger 12 are in the zero state and at the second input of all elements AND 4 there is a single level (the setting circuit is not shown in the zero state)

When recording information (Fig. 2a), the address of the record A3 (number v of the register 1 to which recording is made, 1 1,2, ..., p) is input to the inputs 15 of the device at the same time, the inputs 14 are the recordable information word of the IC, and to input 17 - the write pulse FROM. The write pulse arrives at the third input of all elements AND 4, and the same through, the first element OR to the input of the installation of the trigger 12 and sets the trigger 12 to the one state. After a period of time t after the arrival of A3 at the 1st output of the decoder 2 (the zero output of the decoder in the device is not used), a single signal is generated, which is fed to the first input of the i-th element 4. As a result, after the time t at the output of the t-oro element, a pulse is formed (PI), which is fed to the second input of the i-th register 1 and provides

12

fO

15

20

25

.

-, e

to 50 and ejj

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writing the IC into this register, acts on the input of the setup in the 1st i-th trigger 5 and sets this trigger to the one state j passes through the OR 3 elements and the second OR 10 element and sets the trigger 12 to the zero state. In addition, from the output of the element OR 3, this pulse arrives at the output 20 of the device’s readiness and is a response signal (from). The duration of the impulses OT and PI is equal to the trigger time 1

Thus, after receiving the information in the i-register 1, the i-th trigger 5 is set to a single state and remains there until the information from the i register is read.

If, as a result of an error, the i-th register is re-written (when information received in the register has not yet been read out of it), then the t -and trigger 5 prohibits the formation of a single signal at the output of the i-th element of the 4th signal. As a result, no OT signal is generated. After a time interval equal to the delay time t, + t, + -t, a pulse is generated at the output of the delay element 11, which passes through the element 13 and is outputted to the prohibiting output 19 of the device as an error signal. The same signal passes through the second element OR 10 to the zero input of trigger 12 and sets the trigger to the zero state.

When reading the information (Fig. 26), as well as when writing, the reading address (AF) enters the inputs 15, and the reading pulse (IFA) arrives at the input 6. As a result, single inputs act on all inputs of the i th element And 7 (i and trigger 5 are in the single state) and at its output an impulse PI is formed, which sets the i and trigger 6 to the zero state, is fed to the first input The i-th elements And 6 and provides reading the IC from the i-th register and all through the block of elements OR 8 to the information outputs of the device 8, goes through the element OR 3 to the output 20 of readiness and is a response signal.

If, as a result of an error, read access to information produces 30

35

40

45

c to the register from which the IC has already been read, then the trigger 5 corresponding to this register is in the zero state, the PI pulse is not generated at the output of the corresponding element And 7, the information is not read from the register, and the device prohibits the output 19, as in in the previously considered case, an OR signal is generated.

Thus, in the proposed device, the IC is written only to the register from which the previously received IC is already read, and the reading is only from the register in which the new IC is written. If, as a result of errors, appeals arise for re-writing (when the previously received IC is not yet read) or for re-reading (when the IC is already read, but the new one has not yet been received), then all such errors are detected, error signals are generated. and the treatment is not

are performed.

in the proposed device, the minimum duration of one write or read cycle (Tn) is (Fig. 2a, b)

 p-ash and or tg

To ensure high performance of the input / output device, the decoder 2 must be linear. (4). In this case, w-t. Assuming

H AR35

that t -1; t

or and -tg

,

From consideration of the work of the known device it is clear that in it the duration of one recording cycle is minimal.

(Fig. 2c)

T.

.

receiving A3;

time

T

,,,,,.

7 ng from or

where tg is the response time of the control unit yn-jo;

From the formation of a pulse-response and its duration, respectively.

55

Assuming i: t t

TO

from

and

16i.

j 10

- 15 20

)

Winning the speed of the proposed device compared with the known

) L 9 S - l. i, J.

 P

Thus, the proposed device for entering information on speed exceeds the known 2-2.5 times, and also has a higher accuracy of entering information due to the detection of all errors leading to repeated access to the same registers for writing-reading information, and the exclusion of such appeals.

15 20

25

thirty

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five

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five

Claims (1)

Invention Formula A device for entering information containing registers, a decoder, an OR element, the first group of elements AND, information inputs of the registers are information inputs of the device, the outputs of the decoder are connected respectively to the first inputs of the AND elements of the first group, the outputs of which are connected respectively to the inputs of the register. that, in order to increase the speed and reliability of information input, it contains a group of triggers, the second group of elements . And, the group of elements OR, the first and second elements OR, the delay element, the trigger and the element AND, the output of which is connected to the first input of the second element OR and is the inhibiting output of the device, the inputs of the decoder are the address inputs of the device, the outputs of the decoder are connected respectively to the first - by inputs of elements AND of the third group, the codes of which are connected to the first inputs of elements AND of the second group and the reset inputs of group triggers, the forward outputs of which are connected respectively to the second inputs of elements AND the third th group inverted outputs of flip-flops are respectively connected to groups of the second inputs of AND gates of the first group, whose third inputs and the first input of the first element ILs are input resolution recording device, the third inputs of AND gates of the third group and the second input of the first OR gate is S. 12 The read enable input of the device, the outputs of the elements AND of the first group are connected respectively to the inputs of the installation of the group triggers, the outputs of the registers are connected respectively to the second inputs of the elements AND of the second group, the outputs of which are connected to the corresponding second inputs of the OR elements, the outputs of which are information outputs - dami device outputs of the elements of the first group and the elements of the third "..  f i L, 1 the groups are connected to the inputs of the OR element, the output of which is the device ready output and connected to the second input of the second OR element, the output of which is connected to the reset input of the trigger, the output of the first OR element is connected to the input of the trigger installation and to the input of the emitting element whose output is connected to the first input element And, the second input of which is connected to the trigger output.  tMhiu t (-I / n / l P Editor P. Cossey Compiled by E. Kanaeva Tehred M. Khodanych  | j "j .l P Fie.2 Proofreader V. Booth ha Order 4823/47 Circulation 671 VNIIGSh of the USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk, Embankment, 4/5 Production and printing company, Uzhgorod, st. Project, 4 Subscription