SU1322316A1 - Device for averaging signals - Google Patents

Abstract

The invention relates to computing and can be used, in particular, in medicine. when processing signals electroencephalogram. The purpose of the invention is to improve the accuracy of the device. The operation of the device is based on lowering the resolution by scaling a portion of the image. The device contains analog-to-digital converter 1, adder 2, digital-analog converters 3, 9, oscilloscope 4, memory block 5, subtractor 6, synchronization block 10, counter 8, threshold element 7, register 11, multiplexers 12 , 13, 14, the frequency divider 15, the item ШШ 16, фо) - the worldizer 17 pulses, trigger 18, counter 19, the buffer register 20. 1 Il. (/: with

Description

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Fig. Geichr sp iositsn. niii-incjuigel; -... and his p hk and G; oh .. onk Oym. zopaio in systems of processing, off gigiala, where T1: ao-ats signal averaging about the ensemble realizatsh, and 4ficT U) C rn and

., at processing cnj iia.iiOF. electroencephalogram.

The purpose of the invention is populations when visually analyzing yciieri, a wipe signal according to iipei-ieHi; and dynamic range.

The drawing shows the functional, nan device diagram.

i cTpoiicTiuT contains an analog-diffonoi i transducer 1, c1; m, t.or 2, a digital-analogous signal, n reamers (L. AG) 3, reference data 110T 6, n.-v- m ti, H -; chi 1 a i spruce b, Hopoichm; mi: iaeG: .. 7, SChCH; 8, liA I Y, I)

(a1 ;; -: 1) it, iz11Ip, register 11, mulch L - ii icKcoyii 12 -. (, de: nttel 1 3 hours, j: iC: K iiT IJJU i 1 ij, form11} h at1. l. l 1 / im- 1; ult co}, Tpiirveii 18, sa1stchi 1S, bui; 4 piib i (register 20.

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The device works as sl :: - g, 1 - and 1 G 1 j 6 times.

In the mode Full image on Unrag1Lu: 11, inverse m; - l ;, I lHi.-iL KCC iio - 12-Ki I ;; 1: chi gel 15 h, 1 rd g:, 1 i);); i ; i li.-i lo1 ces1; and food din dd, 4Tii g / beats the end of the coefficient | - H | a / - j iiMn ii dessi- jojia h; 1st,) you, p. ; I;, 4ivt -jHiniellliP LH1.1DP).) NRP 1 ulY Andirjeivcopa 12:; ); oykh;) l; y - mentia: -; . sm-m t zzrmdom d1 :: MK;:, h, n G11:) and .ri; ii1 th oyijiepnoro register. i O, H Llkchlmchenie nkhoda z.lit 1nIgga MI 16 k; -, 1.:;с:du keru nose: a from rn; it is 1 ctr; t; :) u: read tel b (-. 1 1kp- (h ; 11 .lyrii / rinniCKTopa 13 and on: t; chu cha V U.ri, rachgllisch; ustopopek countechkl 19 pos-ga11; 1sr d, H1:) About 1soda label (cT ipine 8 bit). In ycTpoii- C; Accurate. Gic 1 by razr to counter 19 Rapno 8, A. Counter a 8 early 12. On

And 1 1mrmptsioiny) 1 counter flow 8 node-11 and.; Poo. p.c) 1 c) a move; a 10 slyschp1z; p1ii, and on information 1, choll1 -.P1 input counts L ka 19 those; e i ltulmsm, their period is 16 times . , G1od, s1nny output 18 la iix.o; J. counters, op1) unites 11a1 ratio1Ile accounts (direct, reverse). Pogic one) and 1 at the output, not a trigger means direct, but logical KHsi iiojn - reverse. 1 mpul1) Soms from us e) 10rmirovat-el 17 processcTBjjiieToi code entry, which is present 101CSTO for inor; The organization ;; h: i) d, am schst

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H1nsol. in this mode at the initial inputs of the installation of counters 8 and 19 there is a label code. The information reading cycle begins with the writing of the index codes into counters 8 and 19 by a pulse from the output of the driver 17. The pulse duration of the relay is T 8-10T, where T is the repetition period of the pulses from the output of the 6-unit sync of the eopisadium to the input of the address counter 8. Since at the moment of the presence of a pulse at the counter resolution recording input, the counting is forbidden, the oscillo-parplia beam stops for a time, and a voice tag appears on the screen, (x) standing in TpiD i epa 18 at this moment next to the opposite. The new condition of the rigger is unity, which means direct counting — 1 to 8 and 1 9. An oscilloscope, a deviation; according to the city's signal a signal 9, moves to;) T1) in the case to the right of ML: M-; n, a sample of information sampled according to an altram, a large code, and labels. On the port 1LP 3., ugr; 1in 10 | tsego vertical ochsloseliey ray, codes are given from the output of the senior bits of the buffer G e 11C 1 ra 20. Since the counter 19 counts 16 times slower than the counter 8, np) of the osdillograph of the candle 1shet - SL1 Toaj.iso for each Bfji6op tesc, there are only eight that are counted: 1 arrays ampp1- sampling rates. D.P. of the visual control of the full image of the Go image on the oscillo G 11af; 1 x of the number of samplings of the clock, TiiK Kai; with an 8-bit banknote PAK, it is obtained 256 levels GG along the vertical and 25G5 with 1 horizon.ch. At the moment when ;; and there is a full number of counts ;; 19, jni6o of counter 8, again, the shaper 17 and the player are flushed, from which output the starting codes are reset to the counters, and the trigger 18 does not return to the opposite state, i.e. a logical zero appears on its nhixoae, o1 | ;; sde-lu ts 1Y, counting down counts 1..h 8 and 19. The oscilloscope beam begins to d, flashing to the left of the mark, flashing up in the boxes tagged by addresses,; JHYLIim code. Its moment an error again triggers the relay II to switch triggers. repeats. The position of the mark on the curve is determined by the mark code, supplied by the pa inputs of counters 8 and 19.

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Subtracter 6, register 11 ii mule. - type 13 multiplexer designed to control the amplitude of the signal. The signal of the relay in register 11 records the ordinate code of the label, the abcissa code of which is fed to the input of the counter 8. The ordinate code is fed to the input of the counters 6. The second input of the subtractor 6 receives the ordinate code of the current sample. At the moment when the difference module of the ordinate code of the label and the ordinate code of the current sample exceeds the threshold value determined by the dimensions of the oscilloscope screen, the cycle resumes, as the input of the generator 17 and the trigger 18 will receive a pulse from the output of the SHSh 16 element. so that the oscilloscope beam does not go beyond the screen at a given resolution.

In the Segment mode, the control inputs of multiplexers 12-14 and divider 15 are given a logic zero signal, which ensures the setting of the frequency division factor 1, connecting the inputs of CM 3 using multiplexer 12 to B1 1 input of eight low bits of the buffer register 20, connecting the input the element ШШ 16 to the output of the threshold element 7, the input to the input of the counter 19 is the code of the center of the sweep, equal to 2, where n is the counter width. If yes, case 8. 8. In this case, the counters 8 and 19 work in parallel with the only difference, to her that the overflow of the counter 19 occurs 16 times faster than the counter 8, and, therefore, this mode provides a 1/16 view implementation, and this part occupies the entire screen of the oscilloscope. Connecting the D / L 3 inputs to the eight lower bits of the buffer register 20 also allows the vertical scale to be increased 16 times. Thus, by viewing the signal in segments, the high resolution of the storage device can be almost completely used, even with a low resolution oscilloscope - common ability.

The selection of the segment of interest is carried out visually, in the half-image mode by placing a mark in the center of the segment. When switching to segment mode, a pulse code from the output of shaper 17 is written to counter 8, and a 3 code

Chick 19 is the center scan code. Thus, the sample located in the memory block at the address determined by the tag code gets n to the center of the screen, and the screen shows 6y: ieT 2 samples to the right of the center and 2 samples to the left, where n is the counter size 19 .

it about invention

A device for averaging signals containing an analog-digital converter, a buffer register, a memory unit, two digital-to-analog converters, an oscilloscope, a first reversible counter, a synchronization unit, an information input of the analog-digital converter, the output of the analog-digital converter connected to the first information input of the adder, the second information input and output of which are connected respectively with the output of the memory unit and the information input of the buffer register A tra, the write enable input of which is connected to the first output of the synchronization unit, the second output of which is connected to the write permission of the memory unit, and the input is the device start input, the information output of the first reversible C4eTtniKa is connected via the first digital-analog converter to the horizontal reference input oscilloscope sweep, the input of the vertical sweep of which is connected to the output of the second digital-to-analogue converter, characterized in that, in order to improve the accuracy, tel, threshold element, register, three multiplexers, frequency divider, OR element, pulse shaper, trigger, second reversible counter, with the bit outputs of the buffer register connected to the first input of the subtractor, the outputs of the high bits and the outputs of the lower bits of the buffer register are connected respectively the first and second information inputs of the nepBo multiplexer, the output of which is connected to the input of the second digital-to-analog converter, the second input of the subtractor is connected to the output of the register, the information input of connected to the output of the memory unit, whose address input is connected to

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the information output of the second reversible counter, the information input of which is connected to the third output of the synchronization unit and the information input of the frequency divider, the input of the initial installation of the second reversible counter is connected to the first input of the second multiplexer and is the input of setting the device label code, input, enable recording the first reversible counter connected with the enable inputs of the recording of the second reversible counter and register and connected to the output of the pulse former, the input of which is connected to the This input of the trigger and the output of the OR element, the first, second and third inputs of which are connected respectively to the outputs of the recess

first and second reverse

Editor N. Rogulich Order 2867/47

Compiled by V. Orlov

Tehred L. Oliynyk Proofreader A. Zimokosov

Circulation 672 VNIIGSh of the USSR State Committee

for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5

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Production and printing company, Uzhgorod, st. Project, 4

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the counters and the output of the third multiplexer, whose information input is connected to the output of the threshold element, whose input is connected to the output of the subtractor, the output trigger and connected to the control inputs of the selection of the direction of counting of the first and second reversible counters, the information input and output of the initial installation of the first reversible counter, respectively, are connected to the outputs of the frequency divider and the second multiplexer, the second information input of which is the input of the device center setting, and the control the input is connected to the input of setting the division factor of the frequency divider, the same inputs of the first and third multiplexer, and is the input of the setting of the display type of the device.

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Claims (1)

Claim A device for averaging signals containing an analog-to-digital converter, a buffer register, a memory unit, two digital-to-analog converters, an oscilloscope, a first reversible counter, a synchronization unit, the information input of an analog-to-digital converter is the information input of the device, the output of the analog-to-digital converter is connected to the first information the adder input, the second information input and output of which are connected respectively to the output of the memory unit and the information input of the buffer register, the recording permission input of which is connected to the first output of the synchronization block, the second output of which is connected to the recording permission input of the memory block, and the input is the device start input, the information output of the first reversible counter through the first digital-to-analog converter is connected to the input of the horizontal oscilloscope job, the vertical job input which is connected to the output of the second digital-to-analog converter, characterized in that, in order to improve accuracy, a subtraction is introduced into it a threshold element, a register, three multiplexers, a frequency divider, an OR element, a pulse shaper, a trigger, a second reversible counter, the bit outputs of the buffer register being connected to the first input of the subtractor, the outputs of the upper bits and the outputs of the lower bits of the buffer register are connected respectively to the first and the second information inputs of the first multiplexer, the output of which is connected to the input of the second digital-to-analog converter, the second input of the subtractor is connected to the output of the register, the information input to connected to the output of the memory unit, the address input of which is connected to the information output of the second reversible counter, the information input of which is connected to the third output of the synchronization unit and the information input of the frequency divider, the input of the initial installation of the second reversible counter is connected to the first input of the second multiplexer and is the input of the code device labels, input, write permissions of the first reversible counter connected to inputs of write permissions of the second reversible counter and register, and dynamin with the output of the pulse shaper, the input of which is connected to the counting input of the trigger and the output of the OR element, the first, second and third inputs of which are connected respectively to the overflow outputs of the first and second reversible counters and the output of the third multiplexer, the information input of which is connected to the output of the threshold element , the input of which is connected to the exit 5 of the subtractor house, the output of the trigger is connected to the inputs of the control of the choice of the direction of counting of the first and second reversible counters, the information input and the output of The first installation of the first 1θ reversible counter is connected respectively to the outputs of the frequency divider and the second multiplexer, the second information input of which is the input of the job of the center of the device’s scan15, and the control input is connected to the input of the job of the division factor of the frequency divider, the inputs of the first and third multiplexer of the same name are input 20 set the display type of the device.