SU980159A1 - Device for selection of free zones in storage - Google Patents

Description

The invention relates to memory devices and can be used * * to select free zones in memory.

A device is known for selecting information from memory blocks, which contains a drive, registers and drivers of control signals and allows you to select information from the drive by converting the code entering the input register into the address of the cell from which the information is read [C. However, this device does not allow you to select the addresses of free zones of memory. fifteen

Closest to the proposed one is a memory allocation device containing an exchange register, two decoders, an encoder, a counter, registers, AND elements, OR elements 20 and allowing to search for free zones and enter their address codes in the corresponding registers and read from these registers by signal `` Issue '' from the processor (2). 25

A disadvantage of the known device is the low speed, since the search for a free zone is carried out by analyzing a word, reading it from the memory at the specified address coming from the output of the address counter, and switching to reading the word at the next address is possible only / after the analysis of the word is completed at the previous address and writing the free zone code to the auxiliary registers by adding +1 to the address counter. In addition, it is impossible to simultaneously search for and issue codes of 'free zones in the processor.

The purpose of the invention is to increase the speed of the device.

This goal is achieved by the fact that in the device for selecting free zones in memory, containing the first decryptor _g counter, the outputs of which are connected to the inputs of the second decryptor, an encoder, a drive, an OR element and a control unit, the blocks of the order of choice are introduced, and the first 'control input the first block of the order of selection is connected to the first output of the control unit, the outputs of which from the second to the sixth are connected respectively to the second, third and fourth control inputs of the blocks of the order of choice and one of the inputs A storage device, the other inputs of which are connected to the outputs of the decoders, and the outputs are connected to the information ones. the inputs of the selection sequence blocks / information outputs of which are connected to the inputs of the OR element and one of the inputs of the encoder, ”the other inputs of which are connected to the outputs of the second decoder, the first control * input of each block of the selection sequence, except the first, ^ is connected to the control output of the previous priority block selection, the control output of the last block of the order of choice is connected to the input of the counter and the first input of the unit UP.

equation, the second input of which is connected to the output of the OR element.

Each priority block selection is co. holds the AND elements, the NOT element and triggers ³ , the output of the first AND element being connected to the input of the NOT element, the output of which is connected to one _: from the inputs of the second AND element, and the input to one of the inputs of the third AND element, 20 whose output connected to one of the inputs of the first trigger, the output of the last connected to one of the inputs of the fourth element And, the output of which is connected to one of the inputs of the second 25 trigger, the output of the last connected to one of the inputs of the first element And, the other inputs of the second and third elements And are combined and are alone from block inputs, the other inputs 30 Ko torogo are other inputs of first and fourth AND gates and flip-flops and the outputs are the outputs of the second and fourth elements I.

In FIG. 1 shows a functional 35 diagram of a device for selecting free zones in memory; in FIG. 2 functional block diagram of the order of choice; in FIG. 3 - functional diagram of the drive; in FIG. 4 - dd timing diagrams explaining the operation of the device.

The device (Fig. 1) for selecting free zones in the memory unit 1 contains a first address decoder 2, a drive 3, selection order blocks .4, a control unit 5, an encoder 6, an OR element 7, a counter 8 and a second decoder 9. The encoder 6 has exit 10.

Each block 4 of the order of choice ^3υ includes (Fig. 2) the first 11, second 12, third 13 and fourth 14 elements AND, element NOT 15 and the first 16 and second 17 triggers.

The control unit 5 is introduced (Fig. 1 .. 55 multi-cycle generator 18 pulses, third 19, fourth 20 and fifth 21 triggers, register 22 teams, fifth 23, sixth 24, seventh 25, eighth 26 and ninth 27 elements And and elements _to 60 OR 28-30.

The drive 3 contains (Fig. 3) a first group of AND elements 31, registers 32, an element NOT 33, a second group of AND elements 34 and a group of OR elements 35. ¢ 5

The proposed device operates as follows.

The drive 3 is designed in such a way that each address 1-2 * in the memory block to which the information is recorded corresponds to one bit of memory in drive 3, i.e.; the busy address code is written in the unit position code. ·.

When recording information in the memory unit 1 by command ^11, Recording ¹ 'from the processor (not shown) through the OR element 30 simultaneously records. The units from the decoder output to the corresponding bit of the corresponding register 32 in the drive

3. The length of one register 32 corresponds to the number of blocks 4 '. If there is a command ¹ 'Sign' ¹ from the processor (the device is in the free zone search mode), a constant signal from register 22 is supplied to the input of drive 3, through which the inverse outputs of the registers 32 are connected to the outputs of drive 3.

Upon receipt of command ¹ “Issue” from the processor with “Sign” of free zone selection, both commands are written to register 22 and at the same time the signal “Issue” sets trigger 20 through OR element 29 to “1”, the output signal which arrives at one of the inputs of the And 24. element. When the I And 24 element receives a clock pulse T1 (Fig. 4) from its output, a Start signal is generated at the input of the first block 4. At the same time, the “Start” signal sets trigger 21 to “1”. According to the clock pulse T2, the signal from the output of trigger 21 sets the trigger 20 to ¹ “O”, and according to the clock pulse T3 it sets to “0” trigger 21 .

The start signal from the output of block 5 goes to the input of the first block 4 and polls the state of the first output of the first register 32 of drive 3. If there is 'Ί' at this output, which corresponds to a free address, the signal from the output of element 11 is given by the signal '' Start '' installs through trigger And 13 to 1 of trigger 16 and simultaneously prohibits passage of trigger pulse through And And 15 through And And 12 to the input of the second block 4.

According to the clock pulse T2, the signal from the output of the trigger 16 through the AND element 14 is fed to the input of the encoder 6 and to the input of the OR element 7. At the Output 10 of the encoder 6, the address of the free memory zone is received, which is supplied to the processor. At the same time, trigger 17 is set to '’1’ ’, the zero potential from the inverse output of which blocks the input of the And 11 element, inhibiting the passage of the signal

I from the input of the element And 11 to the input of the element And 13. Then, according to the clock pulse TK coming from the control unit 5, it is set to `` О '* trigger 16. At the signal from the output of the element OR 7, a message is generated to the processor''Executed'' about the presence of a free zone address on the device outputs. At the same time, if, together with the signal `` Issue ¹ '', the processor also issued a signal `` Record '', according to the signal `` Completed '', the signal `` Record '' is generated through the elements And 26 and OR 30) according to which, if the processor has information information for recording can be immediately recorded to the selected address.

The signal from the output of the OR element 7 sets, via the OR element 29, into '' 1 '* trigger 20, from the output of which through the And 24 element, a repeated' Start '* signal is generated to the blocks 4 by the clock pulse 11. Since the input of the And 11 element receives a zero signal from the inverted output of the trigger 17, the signal from the output of the And 11 element prevents the passage of the second Start pulse through the And 13 element and allows the passage of the start pulse to the start input of the second block 4 through the And 12 element through the HE 15 element 'Start' 'passes to the input of the element And 11 of the second block 4 and about it asks for the state of the second input of block 4. If there is ’'1' 'at this input, the address of the second free zone is formed. If there is a `` О * '' at the second input (i.e. the address is busy), the trigger signal through element And 12 of the second block 4 is fed to the trigger input of the third block 4 and polls the state of the third input, and if there is '' 0 on its input '', the starting pulse immediately '' is also fed to the starting input of the fourth block 4, i.e. the time of polling busy addresses is determined only by a delay on AND elements 12 of blocks 4 and only when polling an address of a free zone, there is a delay for the time the address of the free zone is sent to the output address buses and the signal is 'Completed'.

The start signal from the output of the last block 4 is supplied to the inputs of the counter 8 and block *. 5 controls. The counter 8 goes into the next state, the status code signals from its outputs go to the inputs of the decoder 9, the output of which forms a control signal that goes to the input of the drive 3 and connects the outputs of the second register to the inputs of blocks 4.

At the same time, the signal from the output of the last unit 4 is fed to the input of the control unit 5 and sets trigger 19 to '4', from the output of which a signal * 'Reset' is generated in blocks 4 through 65 T elements 23 and OR 28 according to which all the triggers 17 of all blocks 4 are set to 'Ό, the signal from the output of the And 23 element also goes 5 to the input of the OR element 29 and sets the trigger 20 to' Ί ' ¹ , from which the signal is generated through the And 24 element by the clock pulse 11 ¹ 'Start *' in blocks 4, according to which the poll of the second register of drive 3 begins. T Thus, all the registers of drive 3 are interrogated. The overflow signal of counter 8 is sent to the output `` Stop '' of the device, serves to stop the search for a free memory zone and at the same time is a report on. no free zones in memory unit 1.

2Q By the signal '' Issue * 'without''Sign''of the choice of free aeons from the processor, there is no constant signal at the input of drive 3. In the absence of this signal, 25 is connected through the element NOT 33 to the inputs of the blocks 4 of the direct rather than the inverse outputs of the registers 32 of the drive 3, which allows the opera to be performed. An active search for occupied, zones of memory block 1 from the output of information by signal ³ “Read”, generated by the control unit 5 when each address of the occupied zone is found, and simultaneously the addresses of the occupied zones are output to the device outputs.

Design features of the proposed technical solution can improve the speed of the device by introducing blocks of the order of choice, allowing 40 automatic skipping addresses of occupied memory zones, and also due to the fact that the sampling time of free memory zones is determined only by the number of free memory addresses.

Claims (2)

(54) DEVICE TO SELECT FREE ZONES IN MEMORY The invention relates to storage devices and can be used to select free zones in memory. A device for selecting information from memory blocks, which contains a drive, registers and drivers of control signals, and allows you to select information from the drive by converting the code received in the input register to the address of the cell from which information 11 is read is known. However, this device does not allow selecting addresses of free memory zones. The closest to the proposed is a device for distributing .pam, which contains the exchange register two decoders, encoder, counter, registers, AND elements, OR elements and allows to produce -search of free zones and entering codes of their addresses into the corresponding registers and reading from these registers on the signal issued from the processor .2. A disadvantage of the known device is low speed, since the search for a free zone is carried out by analyzing a word read from the memory at a given address, coming from the output of the address counter, and the transition to reading a word at the next address is possible only. after completing the analysis of the word on the previous page and writing the code of the free zone in the auxiliary registries by adding -Y to the address counter. In addition, it is impossible to simultaneously search and issue codes of free zones in the processor. The purpose of the invention is to increase the speed of the device. The goal is achieved in that the device for selecting free zones in the memory containing the first decoder, a counter whose outputs are connected to the inputs of the second component, the encoder, the drive, the OR element and the control unit, has been entered The input of the first block of the selection sequence is connected to the first output of the control unit, the outputs of which from the second to the sixth are connected respectively to the second, third and fourth control inputs of the blocks of the priority selection and one of the inputs accumulator, other inputs: which are connected to the outputs of the decoders, and outputs are connected to the information inputs of the selection sequence blocks / information outputs of which are connected to the inputs of the OR element and one of the inputs of the encoder, the other inputs of which are connected to the outputs of the second decoder, first, left equal} is the input of each block of the selection sequence, except the first one (connected to the control output of the previous block of the sequence of choice, the control output of the last block of the sequence of selection is connected to the input of the counter and the first block input pack. The second input is connected to the output of the OR element. Each block of the selection sequence contains AND elements, the element NOT and triggers, the output of the first element AND is connected to the input of the element NOT, the output of which is connected to one of the inputs of the second element AND, and the input to one of the inputs of the third element AND whose output connected to one of the inputs of the first trigger, the output after it is connected to one of the inputs of the fourth element And whose output is connected to one of the inputs of the second trigger, the output of the last connected to one of the inputs of the first element And the other inputs of the second and third elements And are combined and are one of the inputs of the block, the other inputs of which are the other inputs of the first and fourth And elements and flip-flops, and the outputs of the block are the outputs of the second and fourth elements I. 1 shows a functional diagram of an apparatus for selecting free zones in a memory; in fig. 2 is a functional block selection sequence; Fig, 3 - the functional scheme of the drive; in fig. 4 timing diagrams that show how the device works. The device (Fig. 1) for selecting free zones in memory block 1 contains the first decoder 2 addresses, drive 3, selector sequence blocks. 4, control block 5, the encoder 6 or 7, the counter 8 and the second decoder 9. The encoder 6 It has an output of 10. Each block 4 of the selection sequence includes (Fig. 2) the first 11, the second 12, the third 13 and the fourth 14 AND elements, the element NOT 15 and the first 16 and second 17 triggers. Control block 5 has been entered (Fig. 1 multi-cycle pulse generator 18, third 19, fourth 20 and fifth 21 triggers, command register 22, fifth 23, sixth 24, seventh 25, eighth 26 and ninth 27 elements AND and element OR 28 30. The accumulator 3 contains (FIG. 3) the fifth group of elements AND 31, the registers 32, the element NOT 33, the second group of elements AND 34 and the group of elements OR 35. The proposed device works as follows. that each address 1-2 in block 1pami, on which information is recorded, corresponds to one memory bit in the drive 3, i.e., the code of the occupied address is recorded in the one-position code .... When writing information to memory block 1 by the command Record from the processor (not shown), OR 30 is simultaneously recorded from the output of the decoder 2c. the corresponding bit of the corresponding register 32 in the drive 3. The size of one register 32 corresponds to the number of blocks 4. When the Attribute command from the processor (the device is in the free zone search mode) is present, the input of the drive 3 receives a constant signal from the register 22, whichThe outputs of accumulator 3 are connected to the inverse outputs of registers 32. When a command to issue from the processor is received with a free zone selection sign, both commands are written to register 22 and at the same time the output signal sets OR through 29 element to H trigger 20, the signal from which output goes to one of the element inputs And 24. On admission to the other input element And 24 clock pulse T1 (Fig. 4) from its output a Start signal is input to the input of the first block 4. At the same time, the Start start sets to trigger 21. According to the clock pulse T2, the signal from the trigger output 21 sets the trigger to O, and the clock pulse sets the TOR to the trigger 21. The start signal from the output of block 5 enters the input of the first block 4 and polls the state first output of the first register 32 of the drive 3. If available on this output. which corresponds to the free address, the signal from the output of the element 11 on the signal sets the start through the element 13 and 13 to the flip-flop 16 and at the same time prohibits the passage of the pulse 15 through the element 15 to the input of the second block 4. On the clock pulse T2 the trigger 16 through the AND 14 element is fed to the input of the encoder 6 and to the input of the element OR 7. At the bypass 10 of the encoder 6, the address of the free memory zone is received, which enters the processor. At the same time, it is set to 1 flip-flop 17, the zero potential from the inverse output of which blocks the input of element 11, prohibits the passage of the signal from the input of element 11 to the input of element i 13. Then, the clock pulse TZ from the control unit 5 is set to O flip-flop 16. According to the signal from the output of the element OR 7 Form1, a report is sent to the processor. Complied with the presence of a free zone address at the device outputs. At the same time, if, together with the signal Issue, the processor issued a signal and a Record, the Executed signal is formed using the AND 26 and OR 30 elements. A signal that, if there is information in the processor for recording, can immediately be recorded at the selected address. The signal from the output of the element OR 7 sets through the element OR 29 to the H flip-flop 20, from the output of which through the element 24 and the clock pulse T1 generates a repeated signal. Starting up the blocks 4. Since the input signal of the element 11 is a zero signal from the inverse output of the flip-flop 17, the signal from the output of the AND 11 element prohibits the passage of the second pulse. Starting through the AND 13 element and allowing the NOT 1 element to pass the starting pulse to the starting input of the second block 4 through the And 12 element. The start signal passes to the input of the And 11 element of the second block 4 and polls with The second entry of block 4 is established. If available, an address is generated. This input is the second free zone. If O is present (i.e. the address is at the second input of n t), the start signal through the And 12 element of the second block 4 enters the start input of the third block 4 and polls the state of the third input, and, if O is present, the start pulse immediately enters the starting input of the fourth block 4, i.e. the polling time of occupied addresses is caused only by the delay on the elements of AND 12 blocks 4 and only when polling the address of a free zone, a delay occurs at the time of issuing the free zone address to the output address bus and forming a signal. The starting signal from the output of the last block 4 is fed to the inputs of the counter 8 and the block. 5 controls The counter 8 enters the next state, the signals of the state code from its outputs are fed to the inputs of the decoder 9, the output of which forms a control signal which is fed to the input of the accumulator 3 and connects the outputs of the second register to the inputs of the blocks 4 is fed to the input of the control unit 5 and sets to the trigger 19, from the output of which, by the clock pulse T2, through the elements AND 23 and OR 28, a reset signal is generated into blocks 4, according to which all the triggers 17 of all blocks 4 are set to O, the signal From the output of the sensor And 23 also goes to the input of OR 29 and sets to the trigger 20, from the output of which, through the element 24 on the clock pulse T1, a Start signal is generated in blocks 4, through which the second register of the accumulator 3 is polled. interrogation of all registers of accumulator 3. The overflow signal of counter 8 arrives at the output of the device Stop, serves to stop the search for a free memory zone and at the same time is a report about the absence of free zones in memory block 1. On a signal to Issue without a Sign of a free zone selection from the processor, there is no constant signal at the input of drive 3. In the absence of this signal, the NOT 33 element is connected to the inputs of blocks 4 of direct, rather than inverse, outputs of registers 32 of drive 3, which allows an operational search of occupied zones of memory 1 from information output by the Read signal generated by the block. -. control 5 when finding each address of the occupied zone, and simultaneously issuing addresses of the occupied zones to the outputs of the device. The design features of the proposed technical solution make it possible to increase the speed of the device by introducing blocks of the selection sequence that allow automatic address skipping of occupied memory areas, and also because the time of sampling of free memory areas is determined by the number of free memory addresses. ti. ; Claim 1. Device for selecting free zones in a memory, comprising a first decoder, a counter, the terminals of which are connected to the inputs of the second decoder, an encoder, a drive, an OR element and a control unit that is different in order to improve the speed of the device into it. Selection order blocks are entered, the first control input of the first selection queue is connected to the first output of the control unit, the outputs of which from the second to the sixth are connected respectively to the second, third and fourth control inputs of the selection priority blocks and one of the accumulator inputs, the other inputs of which are connected to exits decoders, and the outputs are connected to the information inputs of the blocks Ocher, selection values, the information outputs of which are connected to the inputs of the OR element and one of the inputs of the encoder, the other inputs of which are connected to the outputs of the second decoder, the first control input of each block of the priority of selection, the first is connected to the control the output of the previous block of priority of choice, the control OUTPUT of the last block of the sequence of choice is connected to the input of the counter and the first input of the control block, the second input of which is connected to the output - OR element. 2. Device pop 1, which differs in that each block of the sequence of choice contains elements AND, element NOT and triggers, with the output of the first element AND connected to the input of the element NO, whose output is connected to one of the inputs of the second element And, and the input with one of the inputs of the third element And, the output of which is connected to one of the inputs of the first trigger, the input of the latter is connected to one of the inputs of the fourth element And, the output of which is connected to one of the inputs of the second trigger, the output of which is connected to one from the inputs of the first element Q, the other inputs of the second and third elements AND are combined and are one of the inputs of the block, the other inputs of which are the other inputs of the first and fourth elements AND and the flip-flops and the outputs of the block are the outputs of the second and fourth rtogo elements I. Sources of information taken into account in the examination 1. USSR author's certificate number 557414, cl. G 11 C 8/00, 1974. 20 2. USSR author's certificate No. 580556, cl. G And C 7/00, 1976 (prototype). , 1J L. Fi & .2 Phi 3