SU1037236A1 - Main memory to processor interfacing device - Google Patents

Abstract

DEVICE DR CLEARANCE OF MAIN MEMORY WITH THE PROCESSOR, containing information register, information and control inputs of which are connected respectively with the first information input of the device and the first output of the synchronization node the first, second, third and fourth inputs of which are respectively inputs of the signals Read Write, Sync and Ready the device, the output register, the output of which is connected to the first information output of the device, the first and second information inputs - respectively to the input the home and the output of the correction code generation, and the control input with the second output of the synchronization node, the third output connected to the control input of the memory block select decoder whose output is the device access output, and the information input is connected to the address output of the device and the register output the address whose information input is the address input of the device, the correction unit, the first output connected to the first information inputs of the AND-OR group elements, and the information input from the output An input register, the information input of which is the second information input of the device, is characterized in that, in order to increase the speed of the device, an element is introduced into the NOT, the output of the information register connected to the first information input of the output register, the control input of which is connected to the fourth output of the synchronization node, and the output with the second information inputs of the elements —OR-OR, whose outputs are the second information output of the device, and the first and second control The e inputs are connected to the second output of the correction and the output 00 of the HE element, the input of the device blocking connected to the second output of the correction block and the 1C control block, the first from the control input of the correction block O) is connected to the input clock of the device processor, and the second control input with the fifth output of the synchronization node, the sixth and seventh outputs of which are, respectively, the read and write signal outputs of the device.

Description

1 The invention relates to computing and can be used in the development of main memory management devices used in the composition of the processor. There are known devices for interfacing the main memory with a processor, containing by the number of groups of memory blocks address registers, information registers and output registers, a correction node, a correction code generator and a group of elements AND-OR SP The disadvantage of this device is low speed. The closest in technical essence to the present invention is a device for -framing a main memory with a processor, containing information and address registers, input and output registers, a group of AND-OR elements, a correction node, a correction code driver, two OR elements, a sample node BlokKa memory and synchronization node f 2}. The disadvantage of the known device is low speed, since when issuing each information word from the memory to the processor, there is a delay in the processing time of this word in the correction node. The aim of the invention is to increase the speed of the device. The goal is achieved by the fact that the device containing the information, register, information and control inputs of which are connected respectively to the first information input of the device and the first output of the synchronization node, the first, BTSpoCf, the third and fourth inputs of which are respectively inputs of signals. , Record, Synchronization and Device Availability, the output register, the output of which is connected to the first information output of the device, the first and second information inputs, respectively, with BxcflOM and output f arranged in a ring. When the | | nal appears, the first output of the ring register 36 produces a reception strobe for register 1, and on an I 37 element, a reception gate for information register 3. Information received on register 1 is fed to decoder 2, as well as by address outputs 17 post in the memory block. Under the influence of the address information and control signal from the output of the node 9, the decoder 2 generates, at the output 21, signals providing a choice (reference) to the corresponding memory block. If there are several memory blocks that use common information and address trunks, the readiness signal at input 13 represents the result of the readiness signals from each of the memory blocks of this group and indicates that any block of the group is ready for operation from the output of the information register 3 the information is fed to the output register 5 as well as to form additional check bits (for example, according to Hamming) into the driver k. The inputs of the imaging unit 4 receive certain sets of information bits of the information register 3. Additional outputs are formed at the outputs of the nodes 26, which go to the inputs of the output register 5. When the signal coincides At the second output of the ring ZB register with the signal at input 11, at the output of the element And 38, a reception strobe appears at the output register 5. The main bits and additional control bits entered into it through the information output 20 enter the memory block. When a signal arrives at the memory block Recording from output 15, a signal from output 21, the memory block records information from output 20 into a cell whose address is shown at output 17 When signals are detected at the fourth output of the ZB ring register at the output of the one-shot 0, a pulse that ensures that the trigger 32 is set to the zero state, the synchronization signals to the sync input of the register 3 stop, and the device is reset. A sign of the device's start in the read mode is the readiness and reading signals at inputs 13 and 10. Simultaneously with the appearance of the read signal, inputs 10 and address inputs 16 receive information, a correction code, and a control input with the second output of the synchronization node, the third output of the memory block selector connected to the control input of the selector, the output of which is the device access output, and the information input is connected to the device’s output output and the address register output, whose information input is the address input of the device, the correction block, the first output connected to the first information inputs of the AND-OR group elements, and the information input - with the output of the input register, whose information input is the second information input of the device, the element is entered, the output information | the first register is connected to the first information input of the output register, whose control input is connected to the fourth output of the synchronization node, and the output to the second () information inputs of the AND-OR group elements, The outputs of which are the second information output of the device, and the first and second. The control inputs are connected respectively to the second output of the correction unit and the output of the HE element, the input connected to the second output of the & correction and blocking device output, the first control input of the correction unit is connected to the receive synchronization input. The processor's mother and the second control input are with the fifth output of the synchronization node, the sixth and seventh outputs of which are the read and write outputs of the device, respectively. FIG. 1 shows a block diagram of the proposed device; in fig. 2 is a functional block diagram of the correction in FIG. 3 is a functional diagram of the correction code driver; in fig. - functional diagram of the device synchronization node. The device (Fig. 1) contains an address register 1, a selector decoder 2: a memory block, an information register 3, a correction code generator i, an output register 5, an input register 6, a correction block 7, a second information output 8, a synchronization node 9, an input 10 signals Read signal input 11 Record, synchronization input 12, signal input 13 Ready, signal output Read 14, Record output 15, address input 16 and output 17, first 18 and second 19 information inputs of the device, first information output 20 of the device , output 21 of circulation 364 devices, The cops are AND-OR 22 groups, the blocking output 23, the element 24 and the synchronization input 25 of the processor processor. Correction block 7 (3) contains three modular convolution nodes 26, whose inputs are the information input of the block, and the outputs are connected respectively to the inputs of the decoder 27 of the corrected order, the first output of the block and the first input of the And 28 element. The outputs of the decoder 27 are connected to the inputs of the second node 26. The second input of the element 28 is connected to the second control input of the block, a. the output is connected to the installation input of the trigger unit 29, the output of which is connected to the second control output of the unit, and the installation input zero to the first control input of the unit. The imaging unit 4 (FIG. 3) of the correction code can be executed as a module section of convolutions 26. Node 9 synchronization (Fig. 4) contains an element OR 30, an element AND BF trigger 32, elements AND AZZZZ, a circular register of the shift shear, elements AND 37-39, a pulse shaper (odiovibrator) 0. The device operates as follows. A sign of the start of operation of the device in the recording mode is the readiness and recording signals, respectively, coming from the memory unit and the processor (not shown) through inputs 13, 11 and starting the node. Simultaneously with the appearance of a signal Recording at input 11, address of address 1b is used to output the address of a block cell, a memory, along which memory block over which it is necessary to record, information issued at information input 18. The recording signal at node 9 passes through the OR element 30 and in coincidence with the readiness signal on the element I, 31 installs into the trigger unit 32 A single potential from the output of the trigger 32 permits the passage of clock signals from input 12 to the synchronization input of the ring register 36, ensures the output of a signal. lementa and 35 in a storage unit on an output 15 and also postu1paet to a control input of the decoder 12 select the memory block. Initially, prior to the start of work, the last digit of the ring register 36 records a unit that, during operation, when signals are received at the synchronization input, is rewritten to the first, second, and so on. bits and a move indicating the address of the memory cell that is to be read. The read signal sets up trigger unit 32, permits the passage of snary signals to the synchronization input of the ring register 36, provides a signal to be read from the AND 3 element to the AND output, and issues a signal to the decoder 2 control. When a signal appears at the first output of the ZB dereg register, receiving address information to the register 1. Information from the register 1. enters the decoder 2 and through the address outputs 17 is fed into the address. main memory block,. If the signal AND 39 from the second output of the annular register of the ST with the signal reads, the input gate 10 is formed at reception 10 at the input register 6. The information received at the input register 6 is read from the memory block when the signal is read signal selection (reversal). output 21. Information without additional. the control bits from the input register 6 through the elements AND-OR 22 (at the second control inputs there is a resolving potential initially) goes to output 8, and then to the processor. The same information with additional control bits goes to block 7 (Fig. 2). At the output of the third node 2b, a signal is generated indicating the presence or cc / of an error in the information received from the memory block. If there is an error, a signal appears at the first input of the And 28 element, which coincides with the control signal coming from the node E from the third output of the Zb register, and is set to a trigger unit 29. The unit potential of the trigger 29 enters output 23 and allows the information to pass 366 from block 7 through the elements AND-OR 22 to output 8 and creates at the output of the element NOT 2 a signal that prohibits the passage to output 8 of the contents of the input register 6. At the first node 2b and the decoder 27, a specific faulty bit is detected Yes information, and on the second node 2b, the correction of this bit is made. The corrected information enters the first information inputs of the AND-OR elements 22. The output Q signal 23 triggers a time delay in the processor, during which the reception of information from output B to the processor registers is blocked. The blocking duration is defined as the total delay time of the passage of information from the input register 6 through the first node 26, the decoder 27, the second node 26, and the AND-OR elements 22. As a result of this blocking, the information receiving gate in the processor is formed at the moment when output 8 there is a corrected information. If there is no error, trigger 29 is not activated. There is no blocking signal, the reception strobe in the processor is generated at the moment when the output 8 contains information passing through the AND-OR 22 elements directly from the outputs of the input register 6. The trigger 29 is set to the zero state by the signal at the input 25 of the device, coming from the processor after receiving information from output 8 on the processor registers. When a signal appears at the fourth output of the register 36, the node 9 is set to the zero state of the trigger, 32, stopping the movement of the unit in the register 36, i.e. setting the device to its original state. Thus, the proposed device allows reducing the DURATION of the cycle of information output from the main memory to the processor, which allows increasing the speed of the device.

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Claims (1)

A device for interfacing the main memory with a processor, containing an information register, the information and control inputs of which are connected respectively to the first information input of the device and the first output of the synchronization node ^ the first, second, third and fourth inputs of which are respectively the signals of Read '^,; , Record, Synchronization and Availability of the device, the output register, the output of which is connected to the first information output of the device, the first and second information inputs, respectively, with the input and output of the formation of the correction code, and the control input with the second output of the synchronization node, the third output connected to the control input of the decoder select the memory block, the output of which is the output of the device access, and the information input is connected to the address output of the device and the output of the address register, information the input of which is the address input of the device, the correction unit, the first output connected to the first information inputs of the AND-OR elements of the group, and the information input - with the output of the input register, the information input of which is the second information input of the device, characterized in that, for the purpose to increase the speed of the device, the element NOT is introduced into it, and the output of the information register is connected to the first information input of the output register, the control input of which is connected to the fourth output node synchronization, and the output with the second information inputs of the elements AND-OR groups, the outputs of which are the second information output of the device, and the on / off and the second control inputs are connected respectively to the second output of the correction unit and the output of the element NOT connected to the second output the correction unit and the output of the device lock, the first control input of the correction unit is connected to the synchronization input of the receive processor of the device, and the second control input is connected to the fifth output of the synchronization unit, the sixth and seventh the outputs of which are respectively the outputs of the Read and Write signals of the device. 1 1037236