SU943726A1 - Memory control device - Google Patents

Description

The invention relates to digital computing and can be used in memory management devices in digital computerized control systems. Devices are known for managing the memory of instructions located in permanent memory blocks of digital computing control buses l. This device contains a fixed memory block and a semi-permanent memory block. At the stage of debugging, a program of semi-empty memory replaces one of the blocks of the permanent memory, i.e. the information recorded in the block of permanent memory in a certain position of the switch is replaced by the contents of the block of semi-permanent memory. The accuracy of the indication of the replacement arrays in this device is determined by the randomness of the register and, in some cases, is insufficient. The closest in technical essence is a program debugging device for a persistent storage device that contains a storage unit without destroying information, the first inputs of which are connected to the outputs of the distributor, the first input of which through the control unit is connected to a circulation bus connected to the input of a fixed memory block , the second inputs of which are associated with the second inputs of the storage unit without destroying information and through the unit, forming the address — with address buses connected through the unit to form the address of the section is with the second inputs of the distributor, the third inputs of which are connected to the unit of registers of the installation (RU). In addition, the device contains an input / output unit associated with the outputs of a permanent memory block, a memory block without destroying information. In this device, the choice of substitution arrays, i.e.

The accuracy of specifying information arrays due to the use of a block of installation registers increases, since the storage block array without breaking information is divided into sections according to the number of installation registers and each section is addressed independently.

However, when debugging computer task programs, the accuracy of specifying the data arrays provided by the data is satisfactory. The process of recording information into a memory storage unit without destroying information is carried out in two stages. At the first stage, it is filled with arrays of initial information. At the second stage, the correction of the recorded information is performed. Taking into account the fact that at the final stage of debugging the proofreading programs are of a single character against the background of arrays of debugged information, the replacement of information with large arrays is impractical.

The aim of the invention is to improve the accuracy of replacing the zones of the blocks of the permanent memory with the zones of the Information Destruction Block.

The goal is achieved by the fact that in the device for pack | A memory module containing a comparison unit, a constant memory unit, the first and second address formation units are a register and an output unit, the output unit output is the output of the device, the address input of the device is connected to the inputs of the first and second address formation units, the output of the first block forming the address is connected to the first inputs of the memory and the memory block, the control input of the device is connected to the second input of the memory block and to the first input of the comparison block, the output of which is connected to the second input n AM, the output of the second address generation unit is connected to the third input of the permanent memory unit and the second input of the comparison unit, the third input of which is connected to the register output, the first, second, third and fourth elements I, trigger, single-bit memory unit are entered and a delay element, the output of the first address generation unit and the output of the comparison unit are connected respectively to the first | and second inputs of a single-bit memory block, the output of which is connected to the first trigger input, the memory output is connected to the first inputs And, the output of which is connected to the first input of the output unit, the second input of which is connected to the output of the second element And, the output of the constant memory block is connected to the first input of the second element And, the second input which is connected to the output of the third element And, the clock input of the device a third of its fourth and fourth elements is connected to the first inputs, and to the input of a delay element, the output of which is connected to the second input of the first and second outputs of which are connected respectively to the second inputs of the third and fourth elements ents And, the output of the fourth element And is connected to the second input of the first element I.

The block diagram of the memory management device is shown in the drawing.

The device contains memory 1, the second inputs of which are connected to the output of the comparison unit 2, output 3 of the device, the input of the comparison unit 2 is connected to the control input of the device and to the second input of the permanent memory unit 5, the second input of which is connected to the second inputs of the memory TI 1 and through the address generation unit 6 — with the device’s address input 7 connected via the second address generation unit 8 — with the second inputs of the ERA-, OUTNI block 2, the third inputs of which are connected to the register output 9- The first and second inputs of the one-bit unit 10 memory soya Dineny with the corresponding inputs of memory 1, the third element And 11 the first input of which is connected to the clock input 12 of the device, the first and second elements And 13 and 1f, respectively, the first input of the first element I13 connected to the outputs of memory 1, and the output to the first input of the output unit 15. The first input of the second element And 1 is connected to the output of block 5, and the output of the second element I 1 is connected to the second input of block 15. The output of the one-bit memory block 10 is connected to the first input of the trigger 16, the second input of which is connected with the release of the delay element 17, the fourth ele ene Ta and 18. The entrance member 17, the first inputs of the third AND gate 11 and fourth AND gates 18 are coupled to a clock input of the device.

The device works as follows. The address input 7 of the device from the computer in block 6 and block 8 receives the address code, which is fixed in these blocks. From the output of block 6, the address code goes to the inputs of memory 1, one-bit block 10 of memory and block 5- From the output of block 8 the higher address bits come in block 5 and in block 2 of the comparison, where they are compared with the codes set on reg ister 9. When the polling signal appears on the control input of device 4, block 5 will read information that is in the form of a potential code the inputs of the second element And It. If the code set in block 8 does not match the contents of register 9, then the signal received at input of block 2 from input j does not pass to output of block 2. Thus, access to memory 1 and to one-bit block 10 is not performed, initially the (zero) state of the trigger 16 does not change. In this case, the clock pulse coming through the clock input 12 passes through the third element And 17 to poll the second element And 14. Through the element 18 And the clock pulse does not pass. As a result of this, the information, -read, from block 5 enters through the element 14 and block 15 to the output 3 of the device. If the code set in block 8 matches the contents of register 9, then, together with polling of block 5, memory 1 and single-bit memory block 10 are polled. The information read from memory 1 is fed to the input of the element 13 in the form of a potential code. The one-bit memory block 10 is a one-bit memory device where information controlling the operation of the trigger 16 is stored. Oh, trigger 16 does not change its state. In this case, a clock pulse from input 12 through element 11 is fed into element 14 and output 3 also contains information read from block 5. If the signal 1 is read during polling of the second block 10, then the trigger 16 goes into one state . As a result, the clock pulse from input 12 through element 18 and redelete into element 13 and output 3 through element 13 and block 15 receives information read from memory 9 6. After some time determined by the belt passing through the clock signal delay 17 trigger 16 is reset. Thus, in this device, with the help of register 9 and comparison block 2, arrays are indicated, in which the information of block 5 is replaced with information recorded in memory 1, and the contents of block 1 O indicate the addresses that will be replaced by addresses. Therefore, in this device, the indication of information is carried out with an accuracy of one address. The proposed device, in comparison with the known ones, increases the efficiency of using storage blocks without destroying information, which leads to a reduction in the required memory volumes of this type when debugging. In addition, the cumulative recording time of information in memory 1 is shortened, resulting in improved performance and shorter debugging times. Claims A memory management device comprising a comparison unit, a permanent memory unit, first and second, address generation units, a register and an output unit, receive the output of the output unit is the output of the device, the address input of the device is connected to the inputs of the first and second blocks generating the address, the output of the first address shaping unit is connected to the first memory inputs and the permanent memory unit, the control input of the device is connected to the second input of the permanent memory unit and to the first input of the comparison unit, output which is connected to the second memory input, the output of the second address generation unit is connected to the third input of the permanent memory unit and to the second input of the comparison unit, the third output of which is connected to the register output, characterized in that, for the purpose of improving the accuracy, the device contains The first, second, third and fourth elements And, the trigger, the one-bit memory block and the delay element, the output of the first address generation unit and the output of the comparison block are connected respectively to the first and second inputs of the one-bit block am ti, yield

which is connected to the first input of the trigger, memory output is connected to the first input of the first element And whose output is connected to the first input of the output unit, the second input of which is connected to the output of the second element And, the output of the permanent memory unit is connected to the first input of the second element And , the second input of which is connected to the output of the third element And, the clock input of the device is connected to the first inputs of Tpefbero and the fourth element And, and to the input of the delay element, the output of which is connected to the second

the trigger input, the first and second outputs of which are connected respectively to the second inputs of the third and fourth elements And, the output of the fourth element And connected to the second input of the first element And,

Sources of information taken into account in the examination

1. USSR author's certificate No. 613326, class G 06 R 15/06, 1976.

2. USSR author's certificate number 29107, cl. Q About P P / 00, 1976 (prototype).

Claims (1)

Claim A memory management device comprising a comparison unit, a read-only memory unit, first and second „address generation units, a register and an output unit, wherein the output of the output unit is an output of the device, the address input of the device is connected to the inputs of the first and second address generation units, the output of the first unit the formation of the address is connected to the first inputs of the memory and the read-only memory block, the control input of the device is connected to the second input of the read-only memory and to the first input of the comparison unit, the output of which is connected to the second memory input, the output of the second address generation unit is connected to the third input of the read-only memory unit and to the second input of the comparison unit, the third output of which is connected to the register output, characterized in that, in order to increase accuracy, the device contains the first, second, third and the fourth AND element, a trigger, a single-bit memory unit and a delay element, the output of the first address generation unit and the output of the comparison unit being connected to the first and second inputs of the single-bit memory unit, the output of which is is dined with the first input of the trigger, the memory output is connected to the first input of the first element And, the output of which is connected to the first input of the output unit, the second input of which is connected to the output of the second element And, the output of the permanent memory unit is connected to the first input of the second element And, the second input which is connected to the output of the third AND element, the “0” input of the device is connected to the first inputs of the third and fourth AND elements and to the input of the delay element, the output of which is connected to the second & the trigger input, the first and second outputs of which are connected respectively to the second inputs of the third and fourth elements AND, the output of the fourth 5 elements And is connected to the second input of the first element I.