RU1771533C - Device for digital recording and playback of speech - Google Patents

Abstract

The invention relates to instrumentation and can be used for digital recording / reproduction of voice information. In order to improve performance, a code generator, a second switch, a third trigger, a third multiplexer, a code detector, and a second counter are additionally introduced, which ensures the detection of the marking channel code and reduces the access time to the recorded voice information 2 1 / g

Description

The invention relates to the field of information storage, and in particular to devices for digital recording-reproduction of voice information

The purpose of the invention is to increase the speed of the device

In FIG. 1 is a structural diagram of a device; Fig. 2 is a timing chart of pulses generated at the outputs of the driver 3 of the control pulses. A device for digital recording-reproduction of voice information contains sequentially connected elements 1 of random access memory connected to the outputs of the information inputs of the first multiplexer 2 and connected to the inputs of the address line lock inputs fixing the column address and write enable inputs, respectively, to the first, second and third outputs of the driver 3 of the control pulses connected an input with an input bus 4 of the clock signal connected to the clock input of the analog-to-digital converter 5, to the clock input of the digital-to-analog converters 7 equipped with output buses, and to the counting of the first counter 3, the second, multiplexer 9, the first switch 10, the first and second triggers 11 and 12 register 13 microphone 14 element OR 15, decoder 16, input buses for setting playback and recording modes 17 and 18, and control bus 19

The first counter 8 is connected by the first and second groups of outputs, respectively, with the first and second groups of information inputs of the second multiplexer 9 connected by the control input to the fourth output of the control pulse generator 3 and connected by the outputs to the address inputs of the RAM elements 1 The first switch 10 is connected by the control the input with the output of the first trigger 11 and is connected by the first information input to the output of the analog-to-digital converter 5 connected by the information input to mi 14 rofonu register 13 podklyusl

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than a clock input to the output of the second trigger 12, connected by the installation input to the output of the OR element 15, connected by the first input to the input bus 17 for setting the playback mode. The decoder 16 is connected by the output to the second input of the OR element 15 and connected by inputs to the third group of outputs of the first counter 8, connected to the information inputs of the register 13, the outputs of which are connected to the control inputs of the first multiplexer 2. The input bus 18 for setting the recording mode is connected to the reset input of the first and second triggers 11 and 12.

The device also contains an additional element 20 of dynamic dynamic memory connected between the output of the first switch 10 and the information input of the first of the elements 1 of dynamic dynamic memory, connected to the input of fixing the address of the row, the input of fixing the address of the column and the input of recording permission, respectively, to the first, second and third the outputs of the driver 3 of the control pulses and connected by the address inputs to the outputs of the second multiplexer 9, a code generator 21, a second switch 22 and a third trigger 23.

The code generator 21 is connected to the first information input of the second switch 22, connected by the output to the second information input of the first switch 10. The third trigger 23 is connected by the clock input to the clock input of the first trigger 11, connected to the senior bit of the second group of outputs of the first counter 8.

In addition, the device comprises read channels, each of which consists of a third multiplexer 24, connected by information inputs to the outputs of the dynamic memory elements 1, from a code detector 25 and a second counter 26.

In each read channel, the third multiplexer 24 is connected by an output to the input of the code detector 25, and the second counter 26 is connected by the outputs to the control inputs of the third multiplexer 24 and connected by a counting input to the output of the code detector 25, The first multiplexer 2 is connected by the output to the second information input of the second switch 22, connected by the control input to the output of the third trigger 23, connected by the reset input to the input bus 18 for setting the recording mode. The information input of the third trigger 23 is connected to the output of the first trigger 11 connected by the information input

with the output of the second trigger 12. In this case, the information inputs of digital-to-analog converters 7 are connected to the inputs of the code 25 detectors, and the control bus 19

connected to counting enable inputs of second counters 26 of all readout channels.

The device operates as follows.

0 In the recording mode, a short-term logical level difference (from logical 0 to logical 1) is sent along the input bus 18 for setting the recording mode, resetting the first, second and third triggers 11.

5 12 and 23 to the zero state. In this case, the first trigger 11 switches the first switch 10 to the state of signal transmission from the output of the analog-to-digital converter 5 to the information input of the auxiliary dynamic memory element 20, and the third trigger 23 switches the second switch 22 to the state of signal transmission from the code generator 21 to the second information input of the first

5 of the switch 10. Simultaneously, according to the clock signal from the input bus 4 of the clock signal, the driver 3 of the control pulses generates control pulses arriving at the elements 1 of the operative dynamic memory, to the additional element 20 of the operative dynamic memory and to the first multiplexer 2,

The clock signal also arrives at

5 is the counting input of the first counter 8 and to the clock input of the analog-to-digital converter 5. The timing diagram of the pulses generated at the outputs of the driver 3 of the control pulses is shown in

0 FIG. 2, provides the operation of the elements 1 of the dynamic dynamic memory and an additional 20 elements of the operational dynamic memory in the read-modify-write mode. Impulse signal

5 from the fourth output of the driver 3 of the control pulses switches the second multiplexer 9 to sequentially enter the address codes of the lines from the first group of outputs and address codes

0 columns from the second group of outputs of the first counter 8 to the address inputs of elements 1 and additional element 20 of random access memory. The speech information from the microphone 14 is converted

5 by an analog-to-digital converter 5 by a clock signal into a digital code, supplied through the first switch 10 to the information input of an additional random access memory element 20. In this case, the timing diagram of the control address and information pulses (Fig. 2) at the same inputs of the additional dynamic random access memory element 20 (read-modify-write mode) determines the sequential filling of its cells with a digital code of voice information.

Upon completion of the filling of the additional element 20, this code sequentially fills the elements 1 of random access memory, shifting from the first to the last.

At the same time, from the third group of outputs of the first counter 8 to the decoder 16, as well as to the control inputs of the first multiplexer 2, the code of the element serial number is received through register 13, to which the beginning of the digital code of voice information in the store memory has shifted from additional element 20 and operational elements 1 dynamic memory.

Upon forced transfer to the playback mode, a short-term difference in the logical level (from a logical zero to a logical unit) from the input bus 17 for setting the playback mode through the OR element 15 puts the second trigger 12 into a state in which the logical signal from its output causes the code to register in code 13 the serial number of the additional element 20 or that of the random-access memory elements to which the beginning of the recorded digital voice information code has moved. At the same time, the logical level at the information input of the first trigger 11 is changed. In this case, the first multiplexer 2 is fixed in the state of transmitting a digital code of voice information from the output of one of the elements 1 of the dynamic memory to the second information input of the second switch 22. The serial number of this element is one is greater than the number of the element to which the beginning of the digital code of voice information in the store memory has shifted from additional element 20 and random-access memory elements 1. At the end of the cycle of accessing all cells of the memory element, (its full filling) in which the beginning of the digital code of voice information was located at the time the playback mode was set, the clock input of the first trigger 11 from the high-order bit of the second group of outputs of the first counter 8 receives a logic difference level In this case, the state of the first trigger 11. changes, which leads to a change in the logic level at the information input of the third trigger 23 and

switching the first switch 10, as a result of which the code generator 21 is connected to the information input of the additional random access memory element 20.

The code generator 21 provides the generation of a digital code marking the end of the digital code of the speech signal. Filling an optional item 20

The marking code is accompanied by a shift in the digital code of voice information to the output of the dynamic dynamic memory element 1 connected through the first multiplexer 2. to the second information input of the second switch 22.

Upon completion of the filling of the additional element 20 logic level from the high-order bit of the second group of outputs of the first counter 8, affect

0, the clock input of the third flip-flop 23 throws the latter to the state causing the second switch 22 to switch. When this happens, the information element is accessed by the additional element 20 through the first

5, the multiplexer 2 connects the output of one of the dynamic random access memory elements 1 to which the beginning of the digital voice information code has shifted. Thanks to this for c and d t) P o and co, speech

0 information and a marking code begin to circulate in the annular register formed by elements 1 and additional elements 20 of random access memory.

5

The appearance of the marking code at the output of the first of the elements 1 of dynamic random access memory is accompanied by its transmission through the third multiplexer 24

0 to the input of the detector 25 code in each recording channel. The latter triggers the code detector 25 and generates a logic level difference at its output that accompanies the end of receipt of the code 5 of the marker at the input of the code detector 25. The difference in the logic level changes the state of the outputs of the second counter 26, as a result of which the third multiplexer 24 switches the output of the second of the elements 1

0 operational dynamic memory to the input of the code detector 25 in all recording channels. Similarly, the shift of the marking code to the output of the next of the memory elements 1 causes another

5, switching a third multiplexer 24 in each read channel. In this case, the information inputs of digital-to-analog converters 7 are periodically connected to the output of one of the elements 1 of the dynamic memory, to the output

which shifted the start of the marking code.

When the request for information is received via the input control buses 19, a logic level is supplied blocking the operation of the second counter 26 at the input of the account enable in the corresponding read channel. The latter causes the third multiplexer 24 to be locked in the state of digital data transmission from the output of the dynamic dynamic memory element 1, in which the marker code is shifted to the information input of the digital-analog converter 7 corresponding to the control input bus 19, on which the request was received. Upon completion of the output from this element of memory 1 marker code to the information input of the corresponding digital-to-analog converter 7, a digital code of voice information is received, which is converted into speech information supplied to the corresponding output bus 6. Moreover, the speech information is supplied to the output bus 6 in the sequence corresponding to its record (from the beginning), and the maximum waiting time after receiving a command on the control bus 19 does not exceed the shift time of the digital data in one of the elements 1 opera dynamic memory.

When automatically switching to playback mode, setting the code of the last of the dynamic random access memory elements 1 on the third group of outputs of the first counter 8 causes the decoder 16 to trigger, which throws the second trigger 12 through the OR element 15. As a result, the logic level at the information input of the first trigger 11 changes and the state of the decoder 16 is recorded. In this case, the beginning of the digital code of voice information is located in the penultimate of the RAM elements 1. Upon completion of its filling with a logic signal difference from the high-order bit of the second group of outputs of the first counter 8, the state of the first trigger 11 changes. Further, similar to the described description of the forced transfer to the playback mode, the additional dynamic dynamic memory element 20 is filled with a marking code, and the speech digital code is information is shifted to the output of the last of memory elements 1. In this case, the first multiplexer 2 is fixed in the state of signal transmission from the output of the last of the memory element 1 to the information input of the additional element

20 of the memory, in the form of a circular register, in which a digital code of voice information and a marker code circulate. The receipt of voice information on the output bus 6

is performed similarly to that described in the description of the forced transfer to the playback mode, while the duration of the speech information is determined by the number used in the proposed

the device elements 1 random access memory.

The technical solution proposed by the authors has significant advantages over the prototype, consisting in

the fact that it allows to increase the speed of the device, thereby reducing the time of access to the recorded voice information.

Claims (1)

Formula invented and A device for digital recording-reproduction of voice information, containing serially connected elements of random-access memory, connected by outputs to the information inputs of the first multiplexer and connected by inputs of a line address fixation, column address fixation inputs and recording enable inputs, respectively, to the first, second and third outputs of the driver control pulses connected by the input to the input bus of the clock signal connected to the clock input of the analog-to-digital converter watel to the clock input of the digital-to-analog converters equipped with output buses and to the counting input of the first counter, the first and second group of outputs of which are respectively connected to the first and second groups of inputs of the second multiplexer, connected by the control input to the fourth output of the control pulse generator and connected by the outputs to the address inputs of the elements random access memory, the first switch connected to the control input with the output of the first trigger and connected by the first information input to the analog-to-digital output 0 a converter connected to the microphone by the information input, a register connected by a clock input to the output of a second trigger connected by a setup input to the output of an OR element connected 5 by the first input to the input bus of the playback mode setting and connected by a second input to the output of a decoder connected by inputs to the third group the outputs of the first counter connected to the information inputs of the register connected by the outputs to the control inputs of the first multiplexer, the input bus setting mode a message connected to the reset input of the first and second triggers and the control bus, which means that, in order to improve performance, an additional dynamic random access memory element is introduced into it, a third trigger connected in series with a code generator and a second switch, read channels , each of which consists of a third multiplexer with an output connected to the input of the detector of the code, the output of which is connected to the input of the second counter, the outputs of which are connected to the control inputs of the third multiplexer, under for prison data inputs to the outputs of the operational elements of the dynamic memory, and data inputs tsifroana- analog converters and a control bus are connected respectively to the detectors and inputs the code by allowing all inputs of the second counter reading channels, a first output multiplexer connected to the second information input of the second switch connected by the control input to the output of the third trigger, the reset input of which is connected to the input bus to set the recording mode, and the information input to the output of the first trigger connected by the information input to the output of the second trigger, the output of the second switch is connected to the second information input of the first switch, the clock input of the third trigger is connected to the same input of the first trigger and the senior bit of the second group the outputs of the first counter, an additional element of RAM is connected between the output of the first switch and the information input of the first of the elements of the operational dynamic s input and is connected whith fixing the row address, the input of fixing the column address and the recording enable input, respectively, with the first, second and third outputs of the control pulse generator, and address inputs - to the outputs of the second multiplexer Timing Chart Out (W) Out (W Out SJ Fig 2