SU1213554A1 - Device for checking and controlling reconfiguration - Google Patents

Description

The invention relates to automation and computer engineering and can be used in digital systems to control redundant units and select a workable Configuration.

The purpose of the invention is improving performance and simplifying the device.

In FIG. 1 shows a functional diagram of the device; in FIG. 2 is a functional diagram of the test driver, and in FIG. 3 is a functional diagram of a majorization block.

The reconfiguration monitoring and control device 15 (Fig. 1) contains redundant blocks 1–3, a 4 test shaper, a majority block 5, a control register 6, a control register, a comparison unit 8, a trigger 9, a pulse generator 10, and elements 11–17 , OR element 18, 5 start input 19, first 20 and second outputs of the device control results, standards 22 outputs and tests 23 of the shaper 4 tests, outputs 24 - 27 of the control register 7, output 28 End of the shaper control 4 tests, as well as the first and second 30 outputs of the pulse generator. Output 22 Standard • of the shaper of 4 tests and the output of majorization block 5 are connected respectively to the first and second inputs of comparison block 8, the output of which is connected to the first inputs of I-11 - 14. Output 23

The test driver 4 test is connected to the output of control tests (inputs of reserved blocks 1-3), the first and third information inputs of which are connected respectively to the first and third information inputs of majorization block 5. The outputs 24-27 of the 7 'control register are connected to the second inputs of AND elements 11-14, respectively _} whose outputs are connected to the first to fourth information inputs of the control register 6, respectively. The fifth output 20 of the control register 7 and the first output of the control register 6 are connected to the first inputs of the fifth and sixth 16 And elements, respectively. The second 25 - fourth outputs of the control register 7 are connected to the first - third control inputs of the majorization unit 5, respectively. Input 19 of the device start-up and the output of the OR element 18 are connected respectively to the single and zero inputs of the trigger 9, the output of which is connected to the input of the pulse generator 10 <First output 29 of the pulse generator 10 is connected to the first synchronization input of the test driver 4, the synchronization input of the control register 6 and the second input of the fifth element And 15, the output of which is connected to the first synchronization input control 7 and the first input of the OR element 18 .. The second output 30 of the pulse generator 10 is connected to the second input of the sixth and first input of the seventh 17 And elements, as well as to the second synchronization input of the shaper 4 tests, output 28 of which control is connected to the third input of the sixth and the second input of the seventh 17 elements I. The output of the sixth element And 16 is connected to the second synchronization input of the control register 7, the fifth output of which is connected to the first output 20 The end of the control device. The first output of the control register is connected to the inverse input of the seventh AND element 17, the output of which is connected to the second output 21 of the end of the device control and the second input of the OR element 18. The second and fourth outputs of the control register 6 are connected to the first and third information inputs of the control register 7, respectively.

Shaper 4 tests (Fig. 2). contains a counter 31 addresses, block 32 of the memory (ROM) and the register 33 tests. The first and second inputs of the synchronization of the shaper 4 tests are connected respectively with the counting input of the counter 31 addresses and the synchronization input of the register 33 tests, the outputs Standard, Test and End of control are outputs 22, 23 and 28, respectively, Standard, Test and End of control of the shaper 4 tests, respectively. The output of the address counter 31 is connected to the address input of the memory unit 32, the output of which is connected to the information input of the test register 33.

¹ Majority block 5 (Fig. 3) contains a group of 34 majority elements, a group of 35 OR elements, a group of 36-38 AND elements and an OR-NOT 39 element. The first control input of the majorization block 5 is connected to the first inputs of the AND elements of the first group 36 and the element OR NOT 39, the output of which is connected to the control input of the group of 34 majority elements. The second control input of majorization unit 5 is connected to the second input of the OR-NOT 39 element and the first inputs of AND elements of the second group 37. The third control input of the majorization unit 5 is connected to the third input of the OR-NOT 39 element and the first inputs of AND elements of the third group 38. The first information the input of the majority unit 5 is connected to the first information inputs of the majority elements of group 34 and the second inputs of the AND elements of the first ·. group 36, the outputs of which are connected to the first inputs of the OR elements of group 35. The second information input of the majority unit 5 is connected to the second information inputs of the majority elements of group 34 and the second inputs of the elements AND of the second group 37, the outputs of which are connected to the second inputs of the OR elements of group 35. Third the information input of the majorization unit 5 is connected to the third information inputs of the majority elements of the corpse 34 and the second inputs of the elements of the third group 38, the outputs of which are connected to the third inputs of the cops OR group 35. The outputs of the majority elements of group 34 are connected

1213554 6 with fourth inputs of OR elements of group 35, the outputs of which are connected to the output of majorization block 5.

Shaper 4 tests (Fig. 2) is intended for the formation of test signals for the objects of control, reference reactions and the signal of the end of the control. The inputs of the shaper 4 tests are fed with clock pulses from the outputs 29 and 30 of the generator 10. On the first clock pulse in the counter 31 of the address is written unit. The resulting single set from its output goes to the address input of a 32 _L ROM designed to store the test control program. ROM 32 is divided into storage zones for test signals of reference reactions and microoperations of the end of control. It is a static type storage device. The information read from the ROM 32 is fed to the D input of the register 33, intended for receiving, storing and issuing information. Information is recorded in the register 33 on the trailing edge of the clock pulse supplied to the C-input of the register 33. s_output 30 of the generator 10. Test signals are fed to input 23, the reference reactions to output 22, and the signal from the end of the command to the output of the end of the shaper command 4.

The counter 31 has a conversion factor equal to the length of the test sequence, after reading which with the next pulse received at the input +1, it returns to its original state.

Majority block 5 (Fig. 3) is intended for majority processing of signals issued by redundant blocks 1-3, or for connecting operable redundant blocks to the output in accordance with the control signals received at its control inputs from outputs 25-27 of control register 7. The output signals of the reserved blocks 1-3 are fed to the inputs of the groups of elements AND 36 - 38, respectively, as well as to the inputs of the group 39 major-. container elements. If all the control signals from the outputs 25-27 of register 7 are equal to zero, then a single signal is generated at the output of the OR-NOT 39 element, allowing the functioning of the group of 34 majority elements. As a result of this, the output of block 5 through the group of 35-elements OR receives only the output signals generated by the group of 34 majority 5 elements.

If one of the control signals is equal to one, then through the OR-NOT 39 element it prohibits the functioning of the group of 34 majority elements 10 and allows through the corresponding group of 36 and 37 elements AND and the group of 35 elements OR to connect the output of block 5 to the output of one of the reserved blocks (1 -3).

The control register 6 is intended for storing the results of the control. The first category of register 6 is intended for storing the results of the control of the redundant system in the majority configurations, and the second fourth category is for storing the results of the control of reserved units 1-3, respectively. The register is built on synchronous RS-triggers.

Information is recorded in the register 6 on the trailing edge of the clock pulse from the output 29 of the generator 10. Information on the control results is sent to the S-inputs of the corresponding bits of the register 6 through the elements 11-14, which are controlled by the output signals of the control register 7.

The control register 7 is intended for generating signals controlling the majorization unit 5 and the elements 11-15. It sets the verification sequence of the redundant system, controls the recording of 40 control results in register 6, and controls the configuration of the redundant system based on the results of its control. ’Register 7 is constructed according to the scheme of the shift register with the inputs of parallel information recording.

Information is recorded in the second and fourth bits of register 7 through the inputs D 2 - D 4 of these bits on the trailing edge of the clock 50 pulse received at input 01 from the output of element 15. 15. The shift of the number recorded in register 7 is carried out on the trailing edge of the clock pulse generated element And 16 and entering the input C2. The outputs 24-27 of register 7 are the outputs of the first to fourth digits, respectively. The fifth output, the input 19 of the device and the output signal of the resolution of the generator 10 are fed. The original trigger 9 returns from the output of the elements AND 15 of the discharge is connected to the output 20 of the device. During the initial installation, the second and fifth digits of the register are set to zero, and the first digit is set to one (the circuits and inputs of the initial installation of register 7 are not conventionally shown).

Block .8 comparison is designed to compare the output signals of the redundant system with the standard. If the reaction of the system coincides with the standard, a zero signal is formed at its inverse output, and otherwise, a single signal.

The trigger 9 is designed to control the pulse generator 10. It is triggered by a start signal of a dull unit, the state of the signals and 17, which enter its

-input through the element OR 18 and correspond to the end of the control cycle.

The pulse generator 10 generates two sequences of clock pulses shifted relative to each other, which synchronize the operation of the device. It works only with a single signal at its control input.

Element And 15 forms a pulse, which at the end of the control cycle records its results in register 7 and stops the device, returning trigger 9 to its initial state.

Element And 17 generates a signal about the end of the control cycle, which returns trigger 9 and goes to the output 21 of the device, signaling the end of the control cycle and the correct operation of the redundant system in the majority configuration.

Element And 16 generates a shift signal to the input C2 of register 7 at the end of the next control cycle.

The control and reconfiguration device operates in a manner.

In the initial state, the memory of the device is in the zero state, with the exception of the least significant bit of register 7 j, as a result of which a single signal is output to the output 24 of register 7 (the installation chains are not shown conditionally).

control next all elements

1213554 ⁸ .

The operation of the device begins after the start signal arrives at the input 19 of the device, by which the trigger 9 switches to a single state and starts the pulse generator 10. Since the inputs of majorization unit 5 receive zero signals from the outputs 25-27 of register 7, block 5 implements the function of the output output signal redundancy of blocks 1-3. Thus, the functioning of the device begins with the control of the correct functioning of the redundant system in the majority configuration. This is the first mode of operation. you are a device.

The first clock pulse from the output 30 of the generator 10 is fed to the input of the shaper 4 tests and on its trailing edge in the register 33 (Fig. 2) is written the first test command, which is stored in the memory unit 32 at the zero address. As a result of this, a test is received at the inputs of reserved blocks 1-3 from the output 23 of shaper 4, and the reaction of reserved blocks 1-3 after majorization in block 5 is fed to the input of comparison block 8 .. At the same time, from output 22 of shaper 4 to another input of block 8 'reference reaction. If the signals generated by block 5 and the reference signals coincide, then a zero signal (otherwise, a single signal) is generated at the inverse output 8, which enters through the open element And 11 to the input S1 of register 6.

After that, the first clock pulse is generated at the output 29 of the generator 10, shifted relative to the pulse at the output 30 by the time necessary for generating a reaction to the first test and a signal from the output of block 8 to the input S1 of register 6. This clock pulse writes a unit to bit S1 of register 6, if the reaction is incorrect, or zero, if the system is operational. At the same time, one is added to the counter 31 (Fig. 2) along the trailing edge of the same pulse, and the next test command is read from the memory unit 32.

Then, according to the next pair of clock pulses from the outputs 30 and 29 of the generator 10, the test command read from block 32 is written to register 33, and one is written to the S1 bit of register 6 if the reaction of the reserved system is incorrect. Otherwise, the discharge S1 of the register 6 remains in the previous state.

In the future, the device operates as described until the last test command is read into register 33 from the memory unit 32 of the driver 4. - Unlike previous test commands, it contains the micro-operation End of control, by which the least significant bit of register 33 is set to a single state and at the output 28 of the former 4, a single signal appears that goes to the inputs of elements 16 and 17. The next clock pulse from output 29 generator 10 writes to unit 1 in bit S1 of register 6, if the system reaction to the last test is incorrect, and counter 31 returns to the zero state.

If the controlled system, consisting of redundant blocks 1-3 and majorization block 5, is operational in the majority configuration, then in bit S1 of register 6 zero is written, and the output signal of this discharge element 16 closes and element 17 opens. Then the next impulse from the output 30 of the generator 10 passes through the element And 17 to the output 21 of the device, signaling the end of the control and the system is working in the majority configuration, and the input of the R-trigger 9, crashing the operation of the device.

. If the system is faulty, then on one of the test checks, one is written to the S1 bit of register 6, and a single signal from the output of this discharge closes the And 21 element and opens the And 16. Then the pulse from the output 30 of the generator 10 passes through the And 16 element input C 2 of register 7 and shifts the unit from the first digit to the second. At the same time, he writes the first test command to register 33. At the output 25 of register 7, a single signal appears, which opens the And 12 element and switches the majority block 5. operation in the mode in which the output of the reserved unit 1 is connected to the input of the comparison unit 8. Thus, the device goes into the second mode - the control mode of the reserved unit 1.

The operation of the device in this mode is similar to that described with the difference 5 that the control result is recorded in bit S2 of register 6. In the last test command, a signal is sent to the end of the control, which opens element And 16 (element And 17 is closed by a single signal from the output of discharge S1 of register 6 ), the next clock pulse from the output 30 of the generator 10 passes through the element And 16 to the input C 2 of the register 7 and shifts the unit in it to the third, discharge. At the output 26 of register 7, a single signal appears, which puts the device into the third mode, the monitoring mode of the reserved unit 2.

After checking the operability of block 2, the device switches to the control mode of block 3 (fourth mode). At the end of this mode 25 in register 6 (bits S2 - S4) contains information about the health of all three reserved blocks. After the signal from the end of the control appears, at the output 28 of the shaper 4, the next ₃₀ pulse from the output 30 of the generator 10 passes through the element 16 and shifts the unit to the last fifth digit of the register 7. From its output, a single signal is sent to the output 20 of the device, signaling the end of ³³ control and exit of the system from the majority configuration. At the same time, this signal opens the element And 15, and the next pulse from the output 29 of the generator 10 passes through the element ⁴⁰ And 15 to the input C1 of the register 7 and the input R of the trigger 9. As a result, the inverse code is written to the register 7, which determines the block setting 5, which, ⁴³ ensures the operational state of the redundant system, and trigger 9 returns to its original state and stops the operation of the device.

5 ° The use of the invention improves the efficiency of control and the cost-effectiveness of devices that verify and manage the reconfiguration of redundant systems.

Figure 1

FIG?

Figure 3

Claims (3)

one The first outputs of the control register are connected respectively to the first and third informational inputs of the control register. 2. The device according to claim 1, wherein the test driver contains an address counter, a memory unit and a test register, the first and second synchronization inputs of the test driver are connected to the counter input of the address counter, respectively and the synchronous input of the register of tests, the outputs of the Standard, Test and End of control of which are the same outputs of the former, the output of the address counter is connected to the address input of the memory block, the output of which is connected to the information input of the register of tests. 3. The device according to claim 1, which is based on the fact that the majority block contains a group of majoritarian elements, a group of OR elements, the first - a third group of AND elements. and the OR-NOT element, the first control input of the majoritarian unit is connected to the first inputs of the AND elements of the first group and the OR-NOT element, the output of which is connected to the control / input group of the majority elements, the second control input to the automatic - ke and computer technology and can be used in digital systems to control redundant blocks and select a workable Configuration. The purpose of the invention is to increase the speed and simplify the device. Fig 1 shows a functional diagram of the device; in fig. 2 is a functional diagram of a test driver, and in FIG. 3 - functional block diagram majorization. The reconfiguration control and management device (Fig. 1) contains redundant blocks 1–3, a 4 test driver, block 5 majority 3554 majorization is connected to the second input of the element OR NOT and the first inputs of the elements AND of the second group, the third control input of the majorization unit is connected to the third input of the element OR-NOT and the first inputs of the elements AND of the third group, the first information input of the majorization block is connected to the first information inputs the majority elements of the group and the second inputs of the AND elements of the first group, the outputs of which are connected to the first inputs of the elements of the OR group, the second information input of the majoritarian unit is connected to W the information inputs of the majority elements of the group and the second inputs of the elements of the second group, the outputs of which are connected to the second inputs of the elements of the OR group, the third information input of the majority block is connected to the third information inputs of the majority elements of the group and the second inputs of the elements of the third group, the outputs of which are connected to the third the inputs of the elements of the OR group, the outputs of the majority elements of the group are connected to the fourth inputs of the elements of the OR group, the outputs of which are connected to the output of the block majorization. vania, control register 6, control register, control unit 8, trigger 9, pulse generator 10, AND elements 11-17, OR element 18, start input 19, first 20 and second 21 outputs of the device control results, outputs of standards 22 and tests 23 of the driver of 4 tests, outputs 24-27 of control register 7, output 28 End control of the driver 4 tests, as well as the first 29 and second 30 outputs of the generator 10 pulses. Output 22 The test driver standard 4 and the output of the majoritarian unit 5 are connected respectively to the first and second inputs of the comparison block, the output of which is connected to the first inputs I-11 elements - 14. Output 23 The test driver of 4 tests is connected with the output of control tests (inputs of redundant units 1-3), the first - third information inputs of which are connected respectively with the first - third information inputs of the 5 majoritarian unit. Exits 24-27 The control register 7 is connected to the second inputs of the AND 11-14 elements, respectively, which outputs are connected to the first to fourth information inputs of the control register 6, respectively. The fifth output 20 of the control register 7 and the first output of the control register 6 are connected to the first inputs of the fifth 15 and sixth 16 elements AND, respectively. The second 25 - fourth 27 outputs of the control register 7 are connected to the first - third control inputs of the 5 majorization unit, respectively. The device start input 19 and the output of the OR element 18 are connected respectively to the single and zero inputs of the trigger 9, the output of which is connected to the input of the pulse generator 10, The first output 29 of the pulse generator 10 is connected to the first synchronization input of the test driver 4, the synchronization input of the control register b and the second input of the 15th element 15, the output of which is connected to the first synchronization input register 7 control and the first input element OR 18., 35 and the first inputs of the elements And the third The second output 30 of the generator 10 pulses are connected to the second input of the sixth 16 and the first input of the seventh 17 And elements, as well as the second synchronization input of the former 4 test generator output 28 The end of control of which is connected to the third input of the sixth 16 and the second input of the seventh 17 elements I. The output of the sixth element I 16 is connected to the second synchronization input of control register 7, the fifth output of which is connected to the first output 20 End of control of the device . The first output of the control register is connected to the inverse input of the seventh element AND 17, the output of which is connected to the second output 21 of the device control and the second input of the OR element 18. The second - fourth outputs of the control register 6 are connected to the first - third information inputs of the control 7 register, respectively. 40 45 50 55 group 38. The first information input of the 5 majoritarian unit is connected to the first information inputs of the majority elements of group 34 and the second inputs of the AND elements of the first group 36, the KOTopfejx outputs are connected to the first inputs of the OR elements of the 35 group. The second information input of the 5 majoritarian unit is connected to the second information inputs the major elements of the group 34 and the second inputs of the elements of the second group 37, the outputs of which are connected to the second inputs of the elements of OR of group 35. The third information input of the block 5 is majoritarian nor connected to the third information inputs of the majority elements of the groups. 34 and the second inputs of the elements of the third group 38, the outputs of which are connected to the third inputs of the elements of OR group 35. The outputs of the majority elements of group 34 are connected Shaper 4 tests (Fig. 2). contains an address counter 31, a memory block 32 (ROM) and a register of 33 tests. The first and second synchronization inputs Forming 4 tests are connected respectively with the counting. the input of the address counter 31 and the synchronization input of the register 33 of tests, the outputs of the Standard, Test and End of control of which are outputs 22, 23 and 28 respectively of the Standard, Test and End of control of the driver of the 4 tests respectively. The output of the counter 31 of the address is connected to the input the address of the memory block 32, the output of which is connected to the information input of the register 33 of tests. Majorization block 5 (Fig. 3) contains a group of 34 major elements, a group of 35 OR elements, a group of 36-38 AND elements and an OR-NOT 39 element. The first control input 25 of block 5 are majorized and connected to the first inputs of the elements AND of the first group 36 and the element OR-NOT 39, the output of which is connected to the control input of the group 34 of the majority elements. Second control input 26 block 5 majorization connected to the second input of the element OR NOT 39 and the first inputs of elements And the second group 37, the Third control input 27block 5 majorization & single with the third input of the item ШШ-НЕ 39 group 38. The first information input of the 5 majoritarian unit is connected to the first information inputs of the majority elements of group 34 and the second inputs of the AND elements of the first group 36, the KOTopfejx outputs are connected to the first inputs of the OR elements of the 35 group. The second information input of the 5 majoritarian unit is connected to the second information inputs the major elements of the group 34 and the second inputs of the elements of the second group 37, the outputs of which are connected to the second inputs of the elements of OR of group 35. The third information input of the block 5 is majoritarian nor connected to the third information inputs of the majority elements of the groups. 34 and the second inputs of the elements of the third group 38, the outputs of which are connected to the third inputs of the elements of OR group 35. The outputs of the majority elements of group 34 are connected five with the fourth inputs of the elements OR of the group 35, the outputs of which are connected to the output of the 5 majoritarian unit. The shaper of 4 tests (Fig. 2) is designed to generate test signals to control objects, reference reactions and a control end signal. The inputs of the shaper 4 tests are supplied with clock pulses from generator codes 29 and 30 of generator 10. The first clock pulse is written to address counter 31 unit. The resulting single unit from its output goes to the address input of the ROM 32 intended for storing the test control program. ROM 32 is divided into storage areas for test signals of reference reactions and end-of-operation microoperations. It is a static type storage device. The information read from the ROM 32 is fed to the D input of the register 33, intended for receiving, storing and issuing information. Information is recorded in the register 33 on the falling edge of the clock pulse arriving at the C input of the register 33 ... From output 30 of the generator 10. The test signals arrive at input 23, the reference reactions at 22, and the command end signal at the output end team shaper 4. Counter 31 has a conversion factor, equal to the length of the test sequence, after reading which by the next pulse received at input +1, returns to the initial state. Majorization block 5 (Fig. 3) is designed for the majority processing of signals issued by redundant blocks 1-3, or for connecting to the output of working redundant blocks in accordance with the control signals received at its control inputs from the outputs 25-27 of control register 7 . The output signals of the reserved blocks 1-3 are fed to the inputs of groups of elements And 36 - 38, respectively, as well as to the inputs of a group of 39 majority elements. If all control signals from outputs 25-27 of register 7 are equal to zero, then a single signal is generated at the output of element S1I-HE 39, allowing the operation of a group of 34 majority elements 2135546 Comrade As a result, the output of block 5 through a group of 35-elements OR receives only output signals generated by a group of 34 majority elements 5. -. If one of the control signals is equal to one, then it denies the operation of the group 34 of the majority elements through the element S1I-HE 39 and allows the group 36 of the elements AND the connection of the output of the block 5 to the output of one of the reserved blocks (1-3). 15 Register 6 control is designed to memorize the results of control. The first bit of register 6 is designed to memorize the results of monitoring a redundant system in 20 majority configurations, and the second - the fourth bit - to memorize the results of monitoring the redundant blocks 1-3, respectively. The register is built on synchronous RS-triggers. 25 Writing information to the register 6 is carried out on the falling edge of the clock pulse from the output 29 of the generator 10. Information about the monitoring results is fed to the S-inputs of the corresponding register bits 6 through AND 11-14, which are controlled by the output signals Register 7 control. The control register 7 is intended to generate signals controlling the majorizing unit 5 and the AND elements 11-15. It specifies the check sequence of the redundant system, controls the recording 40 control results to register 6 and controls the configuration of the redundant system based on the results of its control. Register 7 is constructed according to the scheme of a shift register with inputs of parallel recording of information. Information is recorded in the second - fourth bits of register 7 through the inputs D 2 - D 4 of these bits along the falling edge of the sync pulse 50, which enters the input C1 from the output of the And 15 element. The shift of the number written in register 7 is carried out through the rear the front of the sync pulse formed by the element 55 And 16 and entering the input C2. The outputs 24-27 of register 7 are the outputs of the first to fourth bits, respectively. Output p that The bit is connected to the output 20 of the device. With the initial installation of the second - the fifth time () the register register is set to zero, and the first bit is set to one (the circuits and inputs of the initial setup of register 7 are conventionally not shown). Comparison block .8 is designed to compare the output signals of a redundant system with a reference. When the response of the system coincides with the standard, a zero signal is formed at its inverse output, and otherwise a single signal. The trigger 9 is designed to control the pulse generator 10. It is triggered by a start signal input to the device input 19 and a single output signal enables the generator 10. The initial state of the trigger 9 is returned by signals from the output of the elements 15 and 17 that go to its - input through the element OR 18 and correspond to the end of the control cycle. The generator 10 pulses forms two sequences shifted from each other sync pulses | Sov, providing synchronization of the device. It works only with a single signal at its control input. Element I 13 generates a pulse, which at the end of the monitoring cycle records its results in register 7 and stops the operation of the device, returning to its initial state trigger 9. Element And 17 generates a signal about the end of the monitoring cycle, which returns to its initial state trigger 9 and arrives at the output 21 of the device, signaling the end of the monitoring cycle and the correct operation of the redundant system in the majority configuration. Element And 16 generates a shift signal at the input of the C2 register 7 at the end of the next control cycle. The device control and management of reconfiguration works as follows. In the initial state, all the memory elements of the device are in the zero state, with the exception of the low-order bit of register 7, as a result of which, the output 24 of the register 7 receives a single signal (conditional circuits are not shown conditionally in the initial state). 20 25 2135548 Operation of the device begins after the signal arrives at the input 19 of the device. A start, in which the trigger 9 switches to the unit state 5 and starts the generator 10 pulses. Since the inputs of majorization block 5 i do not receive zero signals from outputs 25-27 of register 7, block 5 implements the output majorization function JO signals of redundant blocks 1-3. . Thus, the function of the device begins with the control of the correct functioning of the redundant system in the majority ) 5 configurations. This is the first operating mode. you devices. The first clock pulse from the output 30 of the generator 10 is fed to the input of the 4 test tests and, at its trailing edge, the first test command is written to the register 33 (Fig. 2), which is stored in the memory block 32 at the zero address. As a result, the inputs of the redundant blocks 1-3 from the output 23 of the former 4 receive a test, and the reaction of the reserved units 1-3 after majorization in block 5 is fed to the input of the comparison unit 8. At the same time, from the output 22 of the former 4 to the other input of the unit 8 : reference reakits. If the standard signals generated by block 5 coincide, then the inverse output 8 produces a zero signal (otherwise, a single signal), which is fed through the open element 11 to the input S1 of register 6. After that, at output 29 of generator 10, a first clock pulse is generated, shifted relative to the pulse at output 30 by the time required to form a response to the first test and the signal from the output of block 8 to input S1 of register 6. This clock pulse 5 with its falling edge writes a unit to bit S1 of register 6, if the reaction is incorrect, or zero if the system is operational. At the same time on the falling edge of the same ikhulsa in 50, a counter 31 (FIG. 2) is added, and the next test command is read from the memory block 32. Then, for the next pair of clock pulses from outputs 30 and 29 of generator 55 of torus 10, a test command read from block 32 is written to register 33, and one is written to bit S1 of register 6, if the response is 30 35 40 9 system is incorrect. Otherwise, bit S1 of register 6 remains in the previous state. Further, the device operates in the same way as described until the last test command is read from register 32 of the former 4 to the register 33. - Unlike the previous test commands, it contains the microcontrol End of control, which sets the low-order bit of the register 33 to one state and outputs 28 of the former 4. to a single signal that goes to the inputs of elements 16 and 17. Another A clock pulse from the output 29 of the generator 10 writes to one in bit S1 of register 6, if the response of the system to the last test is not correct, and E returns the zero state to zero. If the monitored system, consisting of redundant blocks 1-3 and majoritarian unit 5, is valid in the majority configuration, then bit 16 of register 6 registers the zero, and the output signal of this bit will close the element 16 and the element 17 will open. Then the next impulse from output 30 of generator 10 passes through element I 17 to output 21 of the device, signaling the end of the control and equating the system in the majority configuration, and the ca-input of the R-flip-flop 9, having saved the device. . If the system is faulty, a unit is recorded in one of the test checks in bit S1 of register 6, and a single signal from the output of this bit closes AND 21 and opens AND 16. Then the pulse from generator 30 output 30 passes through AND 16 at the input of C 2 register 7 and shifts the unit from the first bit to the second. At the same time, he writes the first test command to the register 33. At the output 25 of register 7, a single signal appears, which opens the element I 12 and switches the majorizing unit 5 to the mode in which the output of the redundant unit 1 is connected to the input of the comparison unit 8. Thus, the device goes into 13554 O second mode - control mode of the reserved block 1.. The operation of the device in this mode is similar to that described with the difference 5 that the result of the control is recorded in bit S2 of register 6. In the last test command, the end of control signal is issued, which opens element AND 16 (AND element 17 is closed 10 by a single signal from the output of the S1 register of the register 6), the next clock pulse from the output 30 of the generator 10 passes through the element 16 to the input C 2 of the register 7 and shifts the unit 15 located in it into the third one. At the output 26 of register 7, a single signal appears, which puts the device in the third mode - the mode of control of the reserved block 20 ka 2. After checking the operability of block 2, the device switches to the control mode of block 3 (fourth mode). At the end of this mode 25 in register 6 (bits S2 - S4) contains information about the health of all three reserved blocks. After the end of the control signal appears, the output 28 of the former 4 of the JQ pulse from the output 30 of the generator 10 passes through the element 16 and shifts the unit to the last five bits of the register 7. From its output the single signal arrives at the output 20 of the device, signaling about the end of control and system exit from the majority configuration. At the same time, this signal opens element 15 and the next pulse from output 29 of generator 10 passes through element 15 at input C1 of register 7 and input r of flip-flop 9. As a result, register 7 registers from the register 6 an inverse code that determines the setting of the block 5, which  ensures the operational state of the redundant system, and the trigger 9 returns to the initial state and stops the operation of the device. 50 The use of the invention allows to increase the speed of control and cost-effectiveness of devices that verify and control configuration of redundant devices. 55 systems. 35 40 27ZS25 Compiled by V.Maksimov Editor O.Golovach Tekhred O.Vashchishina Proofreader M.Samborska Order 787/62 Circulation 767.Subscription VNIIPI USSR State Committee for inventions and discoveries -. 113035, Moscow, Zh-35, Raushsk nab. 4/5 Branch PC Patent, Uzhgorod, st. Project, 4 -to