SU1704147A1 - Multimicroprocessor checkable and restorable controlling system - Google Patents

Abstract

The invention relates to computing and can be used as a control subsystem in high-impedance systems for monitoring and controlling the collection and processing of information. The purpose of the invention is to increase the fault tolerance of the system by restoring the performance of the firmware control units in case of failure and failure. The system contains fixed memories of micro-commands and microprograms, a group of microprogram control blocks, an address generation block, a synchronization block, a first address register, a micro-commands register, a second address register, a micro-commands buffer register, a group of micro-initial buffer addresses, a third address register, a control register write, read control register, lock register, error register, first and second counters, first and second triggers, first and second multiplexers, g encoder, decoder unit, adder, comparison node, first, second and fourth switch blocks, micro-operations switch blocks, second switch block, first to ninth groups of AND elements, two groups of OR elements, modulo two, first to third, elements AND from the first to the sixth elements OR, the element OR NOT, the element is NOT. one-shot Increased fault tolerance of the system occurs due to the possibility of restoring the functionality of lower-level microprogram control units in case of failures and malfunctions due to the use of natural structural and temporal redundancy due to the presence of copies of all lower-level microprograms and simple memory of the microprogram control units . 9 il. Ј 1 About N Ј vj

Description

The invention relates to computing and can be used as a control subsystem in high-impedance systems for monitoring and controlling the collection and processing of information.

The aim of the invention is to increase the resiliency of the system, due to

recovery of the microprocessor control units in case of failures and failures.

FIG. 1 and 2 shows a functional diagram of the proposed system; in fig. 3 is a functional diagram of the Mth microprogram control unit; Fig.4 is a functional block diagram synchronization; in fig. 5 is a functional diagram of an address generation unit; in fig. 6 shows the formats of microinstructions used in the system; in fig. 7-9 - time diagram of the system.

The multi-microprogrammed control system with control and recovery (Figs. 1 and 2) contains a permanent memory of 1 micro-instructions (MK ROM). ROM 2 firmware (MP), a group of blocks 3.1-3. To firmware control (MPU), block 4 forming the address MK, block 5 synchronization, first register 6 addresses, register 7 MK with field 7.1 addresses, field 7.2 code logical conditions, operational field 7.3 and field 7.4 tags, second address register 8, buffer register 9 MK, buffer register group 10.1-10. To the start addresses of the MP, third address register 11, write control register 12, read control register 13, lock register 14, register 154 errors, two counters 16 and 17, the first and second trigger 18 and 19, the first and second swarm multiplexers 20 and 21, decoder 22. block 23 decoders, adder 24. comparison node 25, first, third and fourth switch blocks 27 and 28, blocks 29.1-29.K corpse, micro-operations switches, second switch block 30, from first to nine thuyu groups 31-29 elements And, the first and second groups; 40 and 41 elements OR, the adder 42 modulo two. the first to the third elements are AND 43-45, the first to the sixth elements are OR 45-51, the element is OR NOT HE 52, the element B B 5C is one-shot 54.

Chrome: In addition, the system contains an input 55 of the operation code, an input 56 of the start, an input 57 of logical upper-level logic devices, 58.1-58.K of the common low-level conditions, an output of 59 micro-operations, and an input of 59. operations, outputs 60.1-60. To low-level micro-operations, output 61 of failure, outputs 62.1-62. To errors, outputs 63.1-63. To signal control of the recording of a group of 36 And elements, outputs 64.1-64, K s: of a group of read control of a group 35 elements I. output 65 signaling of the initial address of a group of 36 elements And, outputs 66.1-66. To the blocking signals of group 36 ale ntov And, direct outputs 67.1-67, to the register of control of record, direct exits 68.1-69. To the register of control of reading, exits 69.1-69. To group of 34 elements, exits 70.1-70. To group of 39 elements I. output 71 the end of the operation of the group of 35 elements And, the output 72 of the end of the recording of the group of operational outputs of the ROM 2 MP, the outputs of the 73 bits of the address

information outputs of register 9, outputs 74.1-74. To micro-operations of the end of the operation of a group of blocks 29.1-29.K of switches, outputs 75 bits of the address of block 30 of switches.

The Z.M block (Fig. 3) of the MPU contains the operational memory 76.M (RAM MK) register 77.M, counter 78.M, multiplexer 79.M, switch 80.M. two elements And 81.M, 82.M. Element OR 83.M, Element 84.M Delay.

Block 5 (figure 4) synchronization contains the generator 85, the trigger 86. three elements And 87-89, element OR 30.

Unit 4 (FIG. 5) of the formation of the address co5 holds the switch 91 and the element OR 92.

FIG. 6 shows the formats of microinstructions of the system. The formats A and B define the microcommands of the master firmware. The identification of formats (A or B) is carried out according to the value of the microcommand label field: in format A, the last digit is one, in format B, zero. A format microcommands contain an address field (Asl), after logical

5 conditions (LU), the field of micro-operations (MO) and the label field (sign of the micro-command format). The format B microcommands contain the Asl field, the LU field, the address field of the first microcommand1 of the microprogram rewritable from the 2 MP ROM (intermediate level) in block 3. The lower-order MPU. (An. At.) K-field control of operation of blocks 3.1-3. To a lower level MPU (Mzp, M3p, Mb, -) and a label field.

5 Three types of labels are addressed to the lower level MPUs: M3apm — label of the firmware record E block Z. M MPU; M3pm- start mark of the Z.M MPU unit of the lower level; MBLM - lock label leading micro0 prgr s

. Mandates of Format C are stored in a 2 MP ROM and contain an APL field. the field of microinstructions (MK), rewritten from the 2 MP ROM into the Z.M MPU blocks, as well as the label of the end of the microprogramme (M.oi-). D format microcommands are formed in the Z.M block of the lower level v block and contain the Asl field, the LU field. MO field and Mkon tag.

The multi-edged software control system (Figs. 1 and 2) has three levels of control. The external layer is intended to implement the master firmware. The means of the highest level are ROM 1 MK, block 4 of the formation

5 addresses MK, the first register 6 addresses, register 7 MK, multiplexer 20 and block 23 decoders. ROM 1 MK is intended for storing micro-commands of the leading microprogram. Block 4 of the address formation MK forms the executive address by a series of microcommands. At the input 55 of the address address block MK, an operation code is received, which sets the address of the first microcommand of the leading microprogram. The operation code, as well as the address of the next microcommand, passes through the switch 91. The OR 92 element modifies the address of the next microcommand according to the value of the logical condition being checked. The first address register 6 is designed to record the generated address on the leading edge of the first pulse of the sync pulse. Register 7 MK is used to record read from the ROM 1 MK microcommand. The decoder unit 23 generates control signals in accordance with the input codes of microoperations. The number of decoders in block 23 is equal to the number of fields of incompatible micro-operations. The inputs of each decoder are connected to the outputs of the corresponding gender of incompatible microoperations of the outputs of a group of 35 elements I.

The middle control level is intended for the non-return storage of all microprograms for controlling parallel operating devices, which is implemented at the lower level, as well as for generating the microcommand address when reading the microprograms in the Z.MPS units. The means of the average level include the group of 40 elements OR, the register of the 8 address and the ROM of 2 MP.

The lower control level serves to implement parallel control of the same type of operating devices. The means of the lower level are blocks 3.1-Z.K MPU.

The control and synchronization means of the system are intended for the synchronous operation of all its nodes and for organizing the correct functioning of the entire system. The control and synchronization tools include the synchronization unit 5, the upper level firmware control register 12 in the Z.M LPA lower level blocks, the microinstruction read control register 13 from blocks 3.1-3. The lower level MPU, the master firmware lock register 14 and the element OR NOT 52.

The synchronization unit (figure 4) ensures the synchronism of the work of all nodes and units of the system. The generator 85 generates pulses of the first-nth sequences - sync pulses. The trigger 86 provides for the inclusion of a generator 85 sync pulses. In the initial state, the trigger 86 is in the zero state, a zero signal is applied to the control input of the generator 85 and the generator does not function. When the start signal arrives at the system input 56, the trigger 86 goes into one state, thereby turning on the generator 85. Elements 87-89 control the output of clock pulses to various nodes and blocks of the multi-microprogramming control system, depending on the modes of its operation. Z.M MPU blocks work

in two modes: in the mode of recording firmware from the 2 MP ROM and in the mode of implementing parallel firmware.

In the recording mode of the firmware control signals for the Z.M MPU unit

are the fourth sequence of G4 pulses from the outputs 5.6 of the generator 85 and the write signal coming from the outputs 67.M of the register 12 to the control inputs of the switch 80.M and the element 81.M. The counter 78.M serves to set the addresses at which the microcommands are written. In the initial state, the counter 78.M is in the zero state. With the arrival of the clock and signal, the pulses from the output

element And 81.M are fed to the input of the counter 78.M and to the input of the RAM entry MK 76.M. The first microcommand is written to the RAM MK 76.M at the zero address. From the output of the counter 78.M through the switch

80.M when writing, the addresses are received, which are used to record micro-instructions into RAM MK 76.M. With the arrival of each new microcommand, the contents of the counter 78.M increase by one. After coming

to the zero input of the counter 78.M. mark of the end of the recording cycle, it is reset and the supply of recording pulses to the OMCM76.M stops.

In the implementation mode of parallel

The firmware of the Z.M MPU unit works logically at the highest level when implementing the master firmware. The transfer signal to this mode of operation is a single start signal, which comes from the corresponding output 68.M of the register 13. After the signal arrives at the zero address recorded in the 13M register, RAM MK 76.M is read in the first D format micro-command (FIG. . 6).

The reading occurs on the leading edge of the pulse from the output of the I 82.M element, which is fed to the readout input of the RAM MK76.M. The same impulse, a delayed element 84.M delay, controls the writing of the address of the next microcommand in the register 77.M.

The means of monitoring and restoring the multi-microprogramming control system provide periodic monitoring of the operation of the 3.1-3 blocks. To the lower level MPU in the read mode of microcommands, parity of the contents of the 2 MP ROM and recovery from failures and synchronization failures read from the 3.1-3 blocks .K MPU.

The means of control and recovery include buffer registers 10.1-10Zh of the initial addresses of the MP, the third register 11 addresses, error register 15, two counters 16 and 17, the first and second trigger 18 and 19, the second multiplexer 21, the decoder 22, the adder 24, node 25 comparisons, the third and fourth blocks 27 and 28 of switches, a group of blocks 29.1-29.K of switches of micro-operations, the second block 30 of switches, groups 33 + 37, 39 elements, the second group of 41 elements OR, modulo two 42, elements AND 43 -45, elements OR 46-51, element NOT 53, one-shot 54. Buffer registers 10.1-10. The storage of addresses of the first microinstructions of microprograms implemented by blocks 3.1-3.K to the MPU is treated. Register 15 is used to store information about the state of each Z.M block of the lower level. Counter 16 participates in organizing the selection of the Z.M. MPU unit for control. Elements 34.1-34. Carry out the same function. To the group, the element OR 49 and the decoder 22. Counter 17 sets the monitoring time (the zero code is written in the initial state). The monitoring time of each block of the MPU is determined by the frequency of the sync pulses t-v, v-zem overflow of counter 17. When the contents of the counters 17 of this code reach, an overflow signal appears at its output. When, this is the CC TRS /. . S L SM. from Z.G,: 1 pt K pЈ - i 6TSЯ AND

go to the control unit 3. (MPU. Rub: 1 serves as DLR uplle:.

,

IL AND 5. NOT 53 and odBi6. with. five-. cf -: / type trigger trigger switching 18.

The switch unit 26 serves for the switch: ;;;: e 3ЈE O bridge1. Art. rtmz emento E1 intermediate level addresses of micro-instructions read from the 2 MP ROM. B / K.- M - UT-o-rf.-c-ne:,: - ..;, t the commutation of addresses of microprogram microprograms read from blocks 3.1–3. To the MPU, to the second adder 24. Block 30 of co-mutators ensures the switching of the output of blocks 3.1–3. To the MPU at the first information input of the comparison node 25. Modulator 42 modulo two and the trigger trigger 19 are used to control the parity of the information counted from the 2 MP ROM. The group of blocks 29.1-29.K switches is designed for quick disconnect

no outputs of faulty blocks 3.1-3.K MPU.

The buffer register 9 MK, the third address register 11, the second multiplexer 21, the fourth switch block 28, the third element AND 45, the fourth element OR 50. and the second group 41 elements OR form the path of formation and output of addresses of microinstructions when one of the blocks 3.1- fails 3.K

10 MPU for ROM 2 MP. The sixth element OR 51 is intended to block the circuit elements of the set of the monitored block 3.1-З.К. MPU when implementing the restoration of the operation of one of the latter, as well as for

15 start the work of the backup path of the formation of addresses of microinstructions. The sixth group of 39 AND elements and the fifth element OR 47 are used to synchronize the reset of the memory elements of the system.

20 Multi-microprogramming control system with control and recovery works in the following modes: the implementation mode of the leading firmware (mode 1), the simultaneous implementation mode

25 master firmware and firmware recordings from a 2 MP ROM into MPU units of the lower level (mode 2), simultaneous implementation of the master microprogram and operation of MPU units of the lower level (mode 3),

30 mode of simultaneous implementation of the leading firmware, recording firmware in the MPU blocks of the lower level and operation of the MPU blocks of the lower level (mode 4), the mode of simultaneous blocking of the master

35 firmware and operation of the MPU (mode 5).

Mode 1. In the initial state, all trg.gger, register-; and the counters, in addition to trigger 18 and two triggers in register 7, provide the presence of a single signal at the output 71 of the group 35 of the elements I. They are in the zero state. The microcomponents of the microprogram were recorded in the 1 MK ROM unit; microprograms for the units 3–3.4.4 MPU were recorded in the 2 MP ROM block; With a signal applied, the start to the system input 56 in the flea 5 is synchronization Еg., R; a generator 85 is formed, which forms the sequences of sync impulses sovG1, G2, gz, t,. is, Counter 16 starts reading T5 clock pulses. The operation code, which sets the starting address of the master microprogram, comes from the input 55 to the block 4 forming the MC address, signals

55 logical conditions - from the input 57 to the multiplexer 20.

On the first clock pulse ri. coming from the output 5.1 of the synchronization unit 5 to the register synchronization input 6

address, the address of the first microcommand of the microprogram is written into it, which passes through a single signal on the output 71 through the block 4 forming the address of the MC (figure 5) from the input 55 of the system to the inputs of the register b of the address. According to the sync pulse T2 from the output 5.4 of the synchronization unit 5, the first microcommand of the master firmware is read from the ROM 1 MK. In this mode of operation, microcommands of format A are read from ROM 1 MK (Fig. B). In this case, the register 7 of the MK is written in field 7.1 of the address code of the next microcommand, in field 7.2 the code of the logical condition being checked, in field 7.3 the operational part of the microcommand, in field 7.4 one. The address code of the next microcommand from register 7 is fed to block 4 of the formation of the address MK. The code of the checked logical condition from register 7 goes to the address input of the multiplexer 20, which allocates the value of the checked logical condition. The selected logical condition signal from the output of the multiplexer 20 enters the block 4 forming the address of the MC. From the output 71 of the end of the operation of the group of 35 elements AND to the block 4 of the formation of the address M K, a zero signal is applied. The address of the next microcommand from the output of the MK address shaping unit 4 is fed to the information input of the register 6 and is recorded therein on the trailing edge of the clock pulse ri. The operational part of the microcommand from register 7 through a group of 35 elements And enters the input of the block 23 of the decoders of the microoperations. From the outputs of block 23, the decoders of the microoperation come through the output 59 of the system to the operating devices. Further, the functioning of the system for the implementation of microcommands of the format A is similar to the described algorithm. At the output 71 of a single value of the control signal at the end of the operation, the system starts working with a new operation code, which passes from the system inputs 55 through the MK address generation unit 4 to the information inputs of the register 6. The system stops when a single signal appears on output 59. To the end of the operation of block 23 decoders. This signal causes zeroing of flip-flop 86 in block 5 of synchronization (Fig. 4) and the output of the clock pulses n-z by the generator 85 stops.

Mode 2. The operation of the multimicroprogram control system with control and recovery in this mode starts from the moment it is read from the unit.

ROM 1 MK microcommands of format B (fig.b). The microcommand in this case contains the code of the address of the next microcommand, the code of the logical condition being verified, the initial address of An. the firmware to be written into the Z.M MPU blocks, the signal Mzpz and the signal in the sign of the format of microcommands. If the recording is to be made in several blocks of the Z.M MPU,

then the mark signals Mzp are in the field reserved for each block of the Z.M MPU.

When a microcommand of this format on the trailing edge of the clock pulse Tr is written to register 7, the following occurs: a group of 36 AND elements is opened and the starting address An.a. firmware from output 65 of the group of 36 elements AND through a group of 40 elements OR is fed to the information input of the register 8 and to the information inputs of the buffer registers 10.1-10.К. Mzap tags - to the outputs of groups 31 and -33 elements I from outputs 63.1-63. To group 36 elements I. On the falling edge of the sync pulse from output 5.5 of synchronization unit 5, the initial address is An.a. microprograms are entered into register 8: groups of 31 and 33 elements are opened AND by inputs 63.1, on which there are single signals of the mark Mzap. The corresponding triggers of register 12 are set to one and the starting address Am is recorded. in registers 10.1-10. At the output of the element OR 46, a single signal is generated which commutes

register output 8 with ROM input 2 MP.

On the falling edge of the sync pulse TA from the output 5.6 of the synchronization unit 5 through a group of 37 elements, I read from the 2 MP ROM and write to the RAM MK 76.M

the first microcommand recordable firmware format C (fig.b). From the output, field 2.2 of the 2 MP ROM block, the address of the following microcommand is fed through a group of 40 elements OR to the information input

register 8. Then on the next sync pulse G | the address of the next microcommand from the output of block 4 of the formation of the address MK is written into register 6. Next, the operation of the top-level nodes is similar to

mode 1. On the falling edge of the clock pulse gz, the address of the next microcommand of the readable microprogram is entered in register 8 and the back edge of the clock pulse Gz is written to the RAM MK

76.M new micro-command. Further, the operation of nodes and blocks of the middle and lower levels is similar to that described and continues until output signal 72, ROM 2 MP does not receive a single signal. End of recording.

On this signal, the counter 78.M is reset in the Z.M MPU block, and the sync pulse T from the output 5.6 of the synchronization block 5 through the block 31 of the AND blocks is triggered to the register 12 triggers.

Mode 3. This mode starts after the recording of firmware in blocks 3.1-3. To the MPU and at output 64.M of the group of 36 elements And the single signal of the label Mp appears. The signal from the 64.M output of the I group of 36 elements, on a clock pulse Gz from the output 5.5 of the synchronization unit 5, passes through the 32 I input group and translates the triggers of the 13.M register 13 into one state. A single signal of the outputs 68.M of these triggers goes to the control inputs of the switch 80.M of the 3.I MPU block (fig.Z) and to the control input of the And 82.M element, thereby permitting the passage of the microinstructions addresses from the register 77.M The address input and sync pulses TZ to the read input of the RAM MK 76.M. The output of the RAM MK 76.M receives microcommands of the format O (Fig.6). From the output of the unit Z.M, the microoperations pass through the unit 29.M switches to the outputs 60.M of the system. The code of the checked logical condition from the RAM output of the MK 76.M is fed to the input of multiplexer 79.1, the information input of which receives the signals of the logical conditions from the input 58.M of the system. The signal from the output of multiplexer 79.M is fed to the input of the element ILI 83.M, at which the address of the following microcommand is modified. The modified address is written on the back front of the delayed TVJ clock pulse to the register 77. Next, the BPSM MPU continues as before described at the output 74.M of the 2S.M flea of the K1–: snow switches J-, V :.

Control v & o: -t 1 h; i C. -KOB f / PU in this mode are as follows.

At the moment of switching the triggers 13.M of the register 13 in one, the search of the controlled unit 3.1-3 begins. To the MPU, since after the recording is verified at the output of the element - -Ј 46 there is -: - - -th signal. The signal for the end of the search for a controlled block 3.1-3. K is the appearance of a single signal at one of the outputs 60.1-69. To a group of 34 elements I. At this; at the output of the OR 49 element, a single signal appears and the one-shot 54 is excited. The signal from the output of the one-shot sets the trigger 18 to the zero state 18. The zero signal from the single output of the trigger 18 closes the key 43 and sets the zero state to the zero state. Output 5.7 of synchronization block 5 does not pass to the counting input of counter 16. In this counter, the code of the number of the block being checked is recorded. З.М

MPU, and the counter 17 begins to count the number of clock pulses g. In addition, a single signal from the output 69.M group 34 elements And allows the passage of the address code of the first microcommand microprogram implemented by the block Z.M MPU, from the register output 10.M to the first input of the adder 24. To the second input of the adder 24 comes from the output 75 block of 30 switches through a group of 41 elements OR address

the following microcommand block Z.M MPU. The adder 24 determines the address of the microcommand in the 2 MP ROM, which from the output of the latter through the block 26 of the switches enters the input of the ROM of 2 MP. Microcommand. read from ROM 2 MP on a clock pulse from output 5.6 of synchronization unit 5, is entered into register 9, since its control input contains zero potential from the output of the OR 46 element. From output

register 9 micro-command ROM 2 MP is fed to the first input of the comparison node 25, to the second input of which micro-command is received, read from the RAM MK 76.M, through the block 30 of switches according to the resolution

a single signal at the output 69.M of the group 34 of the elements I., The permissive signal for the operation of the comparison node 25 is the presence of a unit at the output of the element OR 49. If the codes of the microinstructions are unequal, a single signal appears at the output of the comparison node 25 This signal goes to the control ENTRANCE of register 15 fritters, permitting their operation. On the next sync pulse from output 5.4 of block 5 synchronization, a single signal from the output of the 6.M group of 34 elements I is entered into the trigger 15.M pen-j: -. Id. EЈ, -.-----; -: OI signal oi-okki with output. P 15.M register 15 enters the control input of the block 29.№

switches. At the same time, the output 60.M of the system is transferred to microoperations from the output of the register 9. The same signal from the output of the trigger 15.M of the register 15 of the switch block 28 switches the presence of the condition that goes to the input 58.M of the Z.M MPU block to the input multiplexer 21. At the same time, a single signal from the trigger output 15.M of the register 15 passes through the element OR 51, blocks the switch unit 30, opens the element And 45, closes the element And 44 and disables the operation of the counter 16. On the next clock pulse from the output 5.5 of the synchronization unit 5 register 11 enters the address alternately th microcommand block Z.M

The MPU from the outputs 73 of the register 9. From the output of the register 11 through a group of 41 elements OR the address of the next microcommand of the microprogram frame enters the second input of the adder 24. Next, the generated address of the microcommand of the 2 MP ROM is passed from the output of the adder 24 through the switch block 26 to the address inputs of the ROM of 2 MP where from the next clock pulse G4 a micro-command of format O is entered into register 9. At the same time, micro-operations pass from the output of register 9 through the block 29.M of switches to outputs 60.M of micro-operations of the system. The address part of the microcommand from the output 73 of the register 9 is fed to the information input of the register 11. The output of the code of the logical conditions of the address output 73 of the register 9 is fed to the control inputs of the multiplexer 21. The modified address bit, together with the result of the branching formed at the output of the multiplexer 21, is fed to the input element OR 50. Since the release of the last modified address bits post. It goes to the information input of register 11. At the next clock pulse Gz, the computed microcommand address is entered into register 11 and the operation cycle repeats. After the implementation of the firmware is completed, output 74.M of the 29.M switch unit produces a single signal. The end of the operation goes to the Mth input of a group of 39 elements I. After the next clock pulse ri from output 5.3 of synchronization unit 5, output 70.M of the group 39 elements And a single signal is generated, by which the trigger 13 M of the register 13, the trigger 15 M of the register 15 and the register 10 M are transferred to the zero state. In addition, this single signal passes through the OR element 47 to the R input of register 9, converting it to the zero state, and to the input of the OR element 48. A single signal from the output of the latter translates the trigger 18 into a single state. A zero signal from the output of the element OR 51 closes the AND 45 element, opens the AND 44 element and enables the operation of the counter 16. At both information inputs of the comparison node 25, there are zero signals that form a zero potential at its output. When a 69.M output group of 34 elements AND a single signal appears, which means the selection of a new monitored unit Z.M MPU, the operation of the system is repeated. At the same time, the microinstructions of the leading firmware are implemented in the same way as the first mode of operation. In addition, the parity of the information read from the 2 MP ROM is monitored by summing the field bits.

2.1 and 2.2 and the control check field 2.3 of the 2 MP ROM on the adder 42 modulo two. The result of the addition from the output of the modulo two adder enters the information

trigger input 19. If a zero signal is generated at the output of the adder 42 modulo two, the system is operational, if one, then no. In the latter case, the sync pulse r from the output 5.6 of the synchronization unit 5 puts the single signal into the trigger 19. At the output 61 of the system, a failure signal is generated and the trigger 86 of the synchronization unit 5 is brought to the zero state. The system terminates its

work

If the error signal does not appear during the monitoring process of the Z.MPU block, then the Z.MPU block selected for monitoring is monitored during the monitoring time,

detected by the overflow code of the counter 17. A signal from the overflow output of the counter 17 transfers the trigger 18 to the one state. Having switched to the single state, the trigger 18 allows the clock pulses from the E 43 element from the output 5.7 of the synchronization unit 5 to the counting input of the counter 16, sets the counter 18 to the zero state and prohibits the passage of the G4 clock pulses through

an element AND 44 to the input of the counter 17. Next, the operation of the system continues as described.

After the appearance on output 74.M of the unit 29.M of switches of a single signal, the end of the operation of the Mth block of the MPU on the next sync pulse from output 5.3 of block 5 of synchronization on output 70.M of the group 39 of elements I produces a single impulse that returns to the initial state trigger 13.M register 13, register 10, M, passes through the OR element 47, and a single signal is generated at its output. A single signal from the output of the element OR 47 brings the register to the zero state

9, passes through the OR element 48, and places the trigger 18 into one state. The search for a new unit 3.1–3 begins. To the MPU for control.

Mode 4. This mode is

a special case of the previous mode. Let the system operate in mode 3. The beginning of mode 4 is the appearance of a single signal at one of the outputs 63.1-63. To the group of 36 elements I. The following happens. The corresponding trigger 12.M of the register 12 goes into one state, a single signal appears at the output of the element OR 46, at all outputs of the group 34 of the elements I is set

zero. This leads to the recording of firmware in the lower level MPUs in the same way as the algorithm described. The occurrence of a zero signal on the output of an OR 49 element causes the trigger 18 to be set to a single state. The counter 16 starts counting the input T5 clock pulses. counter 17 is set to zero. At the same time, control of blocks 3.1-3. To the MPU is stopped. The operation of blocks 3.1-3. To the MPU does not change. If during the transition to the recording mode, the recovery mode was implemented in the system, then the counter 16 remains in the same state. This is due to the presence of a single inhibit signal at the output of the element OR 51, which is fed to the inverted control input of the counter 16 and the inhibit input of the element AND 44. The end of operation in this mode is the appearance at the output 72 of the single signal. By this signal, the triggers 12.1-12. By the register 12 are set to the zero state. If at least one of the blocks 3.1-3 continues to work by this time. To the MPU or if the system went into recording mode, interrupting the restoration of operation of one of the blocks 3.1-3. To the MPU, then with the appearance of the zero signal at the output of the OR 46 element and a single signal at the output of the OR 49 element, the system switches to mode 3.

Mode 5. The system switches to this mode when operating in mode 3 or 4. Let the system function in mode 4. The system switches to mode 5 when it appears on one of the outputs 66.1-66. To a group of 36 elements AND a single signal. As a result, the corresponding trigger K.I register 1- goes to the e single state. A zero signal appears at the output of the OR-NOT 52 element. This signal is the "-.atts RG gkog-b / a, o to c with 5 synchronization. Pr; - it is forbidden to pass synchronization pulses ri to the synch pulses ri to the inputs of the synchro pulses ri to the synch pulses of the 87 and 8o elements. It is allowed to pass the clock pulses g / 1 through the element I 88 to the first BHO. G register 7 MK. The operation of the nodes of the upper UROEN system is blocked. The operation of the blocks and nodes of the middle and lower levels does not change. The end of operation E of this mode is the appearance at the corresponding output 70.1-70. To a group of 39 elements AND a single signal The end of the operation of the Z.M MPU block. On this signal, the register 10.M, the trigger 13.M of the register 13 and the trigger 14.M of the register 14 are reset. After the trigger 14.M is zeroed, a single signal appears at the output of the OR-NOT 52 element. This signal is fed through the prohibition input of the synchronization unit 5 to the equalizing inputs of the elements And 87, 86, No.. permitting the passage of clock pulses L to the input of register synchronization 6, prohibiting the passage of clock pulses n Hi to the zero input of register 7, and allowing the passage of clock pulses to the input of register synchronization 7.

On the falling edge of the clock pulse TZ, a readout from the ROM 1 MK micro-block is written to register 7, and on the falling edge of the clock pulse t, the address of the next micro-command is written to register b. Further, the operation of the system continues in mode 4.

The end of the operation of the multi-microprogramming control system is the appearance at output 59. To the unit of single-signal decoder 23 End of operation. Therefore, the signal is reset trigger 86 in block 5 synchronization. The zero signal from the output of the trigger 86 prohibits the output of TI and TZ clock pulses by the generator 85, and the operation of the multi-microprogramming control system with monitoring and restoring is stopped.

Claims (1)

Invention Formula Multi-microprogramming control system with control and recovery, containing a persistent micro-command memory, a permanent microprogram memory, a group of microprogram control blocks, a micro-address address generation unit, a synchronization block, a first register address, a micro-register register, a second eAresz register, a buffer group initial firmware address registers, write control register, read control register, block register, error register, first and second counters , first trigger, first multiplexer, decoder, b, g 0k decoders, adder, comparison node, first, second, third unit of switches, first to fourth groups of elements I. first group of elements OR, first and second elements I. first to third elements OR element OR NOT element NO. a one-shot, the first information input of the micro-command address generation unit is an input of the system operation code, the group of outputs of the decoder block is connected to the output of the top-level micro-operations of the system, the information input of the first multiplexer is connected to the code input of the logical conditions of the upper level of the system, the first information inputs of the blocks microprogram control group is connected to the group of inputs of the logic codes of the lower system level, the control input of the synchronization block is connected to the system start input, the output of the microcommand address generation block is connected to the information input of the first address register, the output of which is connected to the microcommand constant memory address input, output which is connected to the first and second information inputs of the register of microinstructions, the output of the address of which is connected to the second information input of the block Forming the address of microinstructions, the first control input of which is connected to the output of the first element AND of the first group, the outputs of elements AND of the first group are connected to the inputs of the decoder unit, the first output of which is connected to the first input of the synchronization unit, the prohibition input of which is connected to the output of the element OR- The NOT whose inputs are connected to the outputs of the lock register, the output of the logical conditions register of the microinstructions is connected to the control input of the first multiplexer, the output of which is connected to the input of the modifiers The address of the block of the formation of the address of the microinstructions is resolved, the operational output of the microcomad register is connected to the first inputs of the elements of the first and second groups, the output of the flag of the microcommands register is connected to the second inputs of the elements of the first and inverse inputs of the elements of the second group whose outputs are connected to the first the inputs of the elements OR of the first group, the outputs of which are connected to the information inputs of the second address register and the information inputs of the buffer registers of the initial addresses of the microprograms of the groups , the information outputs of the second register of the address are connected to the first information inputs of the first block of switches, the information outputs of which are connected to the address inputs of the permanent storage of microprograms, the group of address outputs of which is connected to the second inputs of the OR elements of the first group, the group of outputs of micro-operations, permanent storage of microprograms connected to the first inputs of the elements of the third group, the outputs of which are connected to the second information inputs of the micr blocks software control group, information outputs of which are connected to information inputs of the second switch unit, the output of which is connected to the first input of the comparison node, information outputs of the buffer registers of the initial microprogram addresses of the group are connected to information inputs 5 of the third switch block, the output of which is connected to the first input of the adder, group whose outputs are connected to the second group of information inputs of the first block of switches, direct outputs 0 of the write control register are connected to the inputs of the first OR element and to the write control inputs of the group's program control blocks, the direct outputs of the control register, read 5 is connected to the first direct inputs of elements AND of the fourth group and with the control inputs of reading the blocks of the firmware of the group, the output of the first element OR is connected with the control input of the first block of switches, with the second inputs of elements AND of the third group, with inverse inputs of the elements AND of the fourth group The outputs of which are connected to the control inputs of the third block. 5 switches, the inputs of the second element. OR, the information inputs of the error register and the control inputs of the second switch block, the output of the second element OR is connected to the control input 0 comparison node, one-shot input, element NO input. the output of which is connected to the first input of the third OR element, the output of which is connected to the installation input of the first trigger in the unit, the 5th output of which is connected to the input of the installation of the first counter to zero and the first input of the first element AND whose output is connected to the counting input of the second counter, the output of which is connected to the input of the de0 encoder, the outputs of the decoder are connected to the second direct inputs of elements AND of the fourth group, the inverse output of the first trigger is connected to the first input of the second element I, the output of which 5 is connected to the counting input of the first counter, the overflow output of which is connected to the second input of the third OR element, the first output of the synchronization unit is connected to the synchronization input of the first 0 address register, the second output of the synchronization unit is connected to the input of the installation in the zero register of micro-commands, the third output of the synchronization unit is connected to the first and second synchronization inputs of the register 5 microinstructions, the fourth output of the synchronization unit is connected to the synchronization input of the second address register, the fifth output of the synchronization unit is connected to the synchronization inputs of the group microprogram control blocks and to the second input of its And element, the sixth output of the synchronization unit is connected to the second input of the first And element, sign output the end of the recording of the permanent memory of the microprogram is connected to the inputs of the signs of the end of the recording of the microprogram control units of the group, characterized in that. in order to increase fault tolerance, a micro-command buffer register, a third address register, a second trigger, a second multiplexer, a fourth block of switches, a group of blocks of micro-operations switches, with the fifth through ninth group of elements I, are entered into it; the modulo two, the third element AND the fourth to the sixth elements OR, and the output of the sign of the end of the record of the permanent memory of the microprogram program is connected to the first inputs of the elements of the fifth group, the output of the microcommands of the permanent memory of the microprogram is connected to the first input of the modulo two and to the information input of the buffer register of microinstructions, the output of which is connected to the second input of the comparison node and to the first input of the switch blocks of the microoperations of the group, the output of the address field of the buffer control the micro-command source is connected to the information inputs of the third address register, the output of the logic conditions of the micro-commands buffer register is connected to the control input of the second multiplexer, the output of which is connected to the first input of the fourth ILM element, the second input of which is connected to the host of the modified address of the address p :; I am addressing the buffer register mirsks; -e the output of the fourth element OR is connected to the information input of the modified bit of the third regis-prog, information; its path is connected to the first input of the OR element of the second group, the outputs of which are connected to the second input of the adder, then the inputs of the OR elements of the second group are connected to the first output of the second switch unit, the input of the logical conditions of the lower sperm level is connected to the information inputs of the fourth switch unit, the output of which is connected to the information r of the second multiplexer, the field output; the res and the test bit of the BIOSHHOR memory of the microprogram memory are connected to the second and third inputs respectively amy modulo two. the output of which is connected to the information input of the second trigger, the direct output of which is the output of the system failure and is connected to the second input stop block sync. the seventh output of which is connected to the first inputs of the elements of the sixth group, the outputs to which are connected to the stop inputs of the read control register zero, the lock hingter pi, the buffer registers of the initial microprogram program addresses, the error register and the inputs of the fifth element IL1 / output of which is connected to the inputs to the zero setting of the buffer micro- register, the third register of the address and the third input of the third OR element, the output of the first OR element is connected to the inverse control input of the micro-command buffer register, the input of the center is connected to the control input of the buffer register of micro-instructions, the output of the comparison node is connected to the control input of the error register, the output of which is the output of the system error and connected to the control input of the fourth switch block, the control inputs of the switch block of microoperations of the group and the sixth element OR, the output of which is connected to the inverse control input of the second switch unit, the first input of the third element AND, the inverse input of the second element AND, and the inverse control input second On the counter, the outputs of the switch blocks of micro-operations of the group are the outputs of the microoperations of the lower level of the system, the outputs of groups of bits of the blocks of switches of the micro-operations of the group are connected to the first inputs of the elements And the sixth group, the outputs of the elements And the second corpses are connected to the re-entrances of the elements And Cers - C group, outputs which are connected to the Blocks of installation in the unit of the register of blocking, the outputs of the elements And the second are connected to the first inputs of even elements And the fifth group, the output of which is connected to the inputs of the installation The control register register, the outputs of the V t elements of the second group are connected to the first inputs of the elements of the eighth and ninth groups, the outputs of the elements of the eighth round are connected to the installation inputs of the read control register unit, the PEDs of the elements and the ninth corpus are connected to the synchronization inputs of the buffer the registers of the initial addresses of the corpse microprograms, the information outputs of the microprogram control units of the group are connected to the second information inputs of the switch blocks of micro-operations of the gurppa. the third output of the synchronization unit is connected to the synchronization inputs of the error register, the fourth output of the synchronization unit is connected to the second inputs of the elements And from the seventh to the ninth groups, with the second inputs of the even-numbered elements of And the fifth group and the second input of the third element And, the output of which is connected to the synchronization input of the third address register, the fifth output of the synchronization unit is connected to the synchronization inputs of the second trigger and buffer register of microinstructions and with the second inputs of odd elements And the fifth group, the outputs of which are connected respectively to the inputs of setting the register of the write control register to zero. r-t "T about gts Che "V Pa sixteen L tj trifb Ј M (D ifrltrOZ.1 u .. & §  355а§ |; s 5 J ig ix j 2 / remmmmmx 3 u mode5 mode ®ig.8 l / ta -four Alll PP PP Tp tp NSPPSHMPSHSH UGUUGUSHUSH 1 mode Fi g. 9