SU1485407A1 - Multi-channel programmed code-phase converter - Google Patents

Description

The invention relates to automation and pulse technology and can be used in automated process control systems. The aim of the invention is to expand the frequency range of the output signals and increase the reliability of the converter by eliminating the possibility of failures at the moments of changing the input information. To achieve this goal, the converter contains a clock pulse generator, a register, a counting trigger, η channels for the formation of a sequence of pulses, each of which

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'contains a register, a comparison block and a counting trigger, entered η elements OR NOT, data register, state bus, state strobe bus, state register, initial state bus, frequency divider, multiplexer, multiplexer address register, dep'ifwriter, trigger, three elements, OR-NOT, two inverters, element 2I-OR-NOT, a period counter, a bus of a logical unit, and element 2I-OR-NOT and an inverter are inserted into each of the η channels of the pulse trainers. Formation of phase-shifted pulses in the device takes place at moments of equality from a linearly decreasing code, automatically recorded in a reversible counter, to the contents of the memory register in each channel. The presence of elements indicating the state of the device allows asynchronous programming from the computer without causing failures. The frequency of the generated signals in the device is controlled by selecting, by means of a multiplexer, corresponding frequencies from the outputs of the divider, the frequency of the generator pulses to the input of the reversible counter. 1 il.

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The invention relates to automation and computing and can be used in automated process control systems for the formation of you. low-frequency pulse sequences over η channels with the possibility of programming in a wide range of the frequency of the pulses and the phase shift between them.

The aim of the invention is to expand the range of frequencies of the output signals and increase the reliability of the transformer 1485407 4

raeovatel due to the elimination of failures in moments of change of input information.

The drawing shows the functional diagram of the multichannel programmable converter code phase.

The converter contains 1 clock pulse generator "register 2, reversible counter 3, first counting trigger 4, η sequence forming channels 5, each of which consists of register 6, comparison unit 7, counting trigger 8, element 2И-ИПИ НЕ НЕ 9 and inverter 10, η 15 elements OR NOT 11, bus 12 data, bus 13 data strobe, data register 14, bus 15 states, bus 16 strobe states, state register 17, bus 18 set the original sos-20 tayniya, frequency divider 19, multiplexer 20, multiplexer address register 21, descrambler 22, trigger 2 3, three elements OR-NOT 24-26, two inverters 27 and 28, the first element 25 2-OR-NOT 29, a counter of 30 periods, a bus 3ί of a logical unit, a bus 32 of the reference signal.

The converter works as follows. thirty

On the bus 18 to set the initial state by an external device, a signal is generated that sets the multiplexer address register 21, trigger 23, reversible counter 3, first counting trigger 4, counter 30 periods, counting triggers 8 ₁ -8 through the elements OR-NOT 24 and 26 _n in each of the channels 5, -5 _η forming pulse sequences. Due to the fact that a zero code is set at the address inputs of the multiplexer 20, and the first input is connected to the bus 31 of the logical unit, the output level of the multiplexer 20 is set to the logical unit level | TSY, prohibiting the subtraction mode of the reversible counter 3. The converter can operate in two initial modes programming and generation of phase-shifted sequences of pulses. In both modes ^! the external device communicates with the converter using two registers: data 14 and states I7. The t-bit code is written to the registers via gates arriving via buses 13 and 16, respectively.

venno. For register 14 data fair expression

t = H + k + 1,

where t is the digit capacity of the data register 14;

L is the bit width * of the register 21 of the address of the multiplexer;

to - the bit width of the decoder 22;

1 - register width 2,

6, -6 ,,.

To provide the initial programming mode, the external device sets a bitwise code on bus 12 of data, b = X (hereafter X means any code), k = 1, 1 ^F X. When this code arrives, the signal from the first output of the decoder 22 sets the trigger 23 In the unit state, and at the output of the first element 2I-OR-NOT 29, a logic zero level appears, allowing 22 write pulses to the register 2 and registers 6, -6 "from each of the η channels 5 to pass from the decoder. The external device sequentially sets the η-bit codes for I write to the specified registers. Upon completion nachalnogo'programmirovaniya mode 2 is written in a register code corresponding to the frequency of the output pulse sequences, registers' 6, -6 _s - codes corresponding to the desired phase shifts for each of the channels. An external device receives a code in which L ^Ш Х, к = 2, 1 "Х, which sets the trigger 23 to the zero state and prohibits the passage of pulses from the decoder 22 to the synchronous inputs of registers 2, 6, -6 ,,. To ensure the formation of phase-shifted sequences, a code is sent across bus 12 in which the multiplexer address code that is different from zero is sent to the L bits, k = 3, 1 and ^I X, and at the output of the multiplexer 20 clocks appear, and sequences to the address inputs is the code corresponding to the connection of the output of the generator 1 clock pulses or the lower bits of the frequency divider 19. With a lower required frequency of the generated sequences and a limitation on, the width of the registers 2, 6, -6 _n can be set code corresponding to the connection of high-order bits divide5

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For 19 frequencies. On the first clock pulse arriving at the subtracting input of the reversible counter 3, a pulse appears at the output of the zero-state indication, which records the contents of the first register 2 into the reversible counter 3 and forms the leading edge of the reference signal and _op on the bus 32. For the next 10 clock reversals counter 3 cycles through the subtraction mode and writing the code corresponding to the frequency upon reaching the zero state, so that

the output of the counting trigger 4 is formed of the reference signal with a frequency corresponding to the set code. When every cycle of a changing code coincides at the outputs of the reversible 20 counter 3 with the codes set in registers 6 ^ -6 ", blocks 7 ₁ -7" of comparison, pulses are generated, indicating the equality of the codes.

On the direct outputs of the counting triggers 25, signals are formed that are shifted relative to the reference signal within ΟΙ 80 °, in order to form a complete phase shift of 0-360 °, depending on. states of the 1st digit are used 30 elements 2I-OR-NOT 9, -9 _n and inverters 10, -10 ,,. Counting the number of periods of the reference signal is carried out by a counter of 30 periods. The external device; can analyze its state 35 by polling the contents of the 17 state register and decide to write new information to memory registers 2, 6, -6 _b , and by using elements 28 and 29, the recording time is 40 records synchronized with the beginning the period of the reference signal. Recording new information can be done cyclically from one period of the reference signal to hundreds of 45 periods (determined by the capacity of the counter 301, depending on the required cyclicity, the frequency of the output signals and the speed of the external device. Exit from the mode of forming phase-shifted pulses by external device u-bit code in which b = x, k = 4, 1 = x,

At the same time, the register 21 of the address of the multi-55 plexer is set to the zero state and the closure of the clock pulses to the subtracting input of the reversing counter 3 stops.

Thus, a multichannel code-phase converter is implemented, oriented for use with an external microcomputer, for which data converter 14 and states 17 are entered into the converter. Synchronization of information recording moments in multichannel converter registers with the operation of sequence generation channels allows you to record information at certain points time dependent on the contents of the status register and falling on the beginning of the formation of the next period of pulsed sequences Tey, which eliminates the possibility of failures. The transformer allows the frequency range to be expanded without increasing the digit capacity of the registers, that is, without significant hardware costs. For example, with a clock frequency of 20 KHz, eight-bit memory registers and a four-digit frequency divider, the output signals can vary from 2.5 kHz with maximum codes to 1 MHz with a frequency code of 10 and a code fed to the address inputs of the multiplexer equal to 1.

Claims (1)

Claim Multichannel programmable converter code - phase, containing a clock pulse generator, register, reversible counter, counting trigger, η pulse sequence generation channels, each of which contains a register, whose outputs are connected to the first group of inputs of the comparator, counting trigger, whose input is connected to the output the comparison unit, the outputs of the reversible counter are connected to the second groups of inputs of the comparison units of each of the channels for forming a sequence of pulses, the data bus, the bus page database, characterized in that, in order to expand the frequency range of the output signals and improve the reliability of the converter by eliminating failures at the moments of changing the input information of the converter, n + 3 ILY-NE elements, a data register, a state bus, a state strobe bus are entered into it , state register, initial state bus, divider 7 1485407 eight frequencies, multiplexer, multiplexer address register, descrambler, trigger, two inverters, element 2И-OR-NOT, period counter, bus of logical unit, and element 2И-OR-NOT and inverter, logical bus are entered into each of the η channels of the formation of pulse sequences. units connected to the first input of the multiplexer, the output of the clock pulse generator is connected to the second input of the multiplexer and the input of the frequency divider, the outputs of which are connected to the first group of inputs of the multiplexer, data bus 15 and Data strobe are connected with the data input register groups, the first output group of which is connected to the address register input group, the outputs of which are connected to the second multiplexer input group, the output of which is connected to the subtracting input of the reversible counter, the second output register group of information registers and information inputs of the registers of the channels of formation of the pulse sequences, the third group of outputs of the data register is connected to the inputs of the decoder, the first and second outputs of which are connected They are not connected with the first and second inputs of the trigger setup, respectively, the third output of the decoder is connected to the synchronization input of the register of the address of the multi- 35 plexer ,. the fourth output of the decoder is connected to the first input of the first element OR NOT, the fifth output to the first input of the second element OR NOT, the output of the first element OR NOT connected to 40 the first input of the third element ORINE, and the outputs from the sixth to (n + 5) - d is connected to the first inputs of the elements OR NOT from the fourth to (n + 3) -th. the outputs of which are connected to the control inputs of the registers of the formation channels of pulse sequences, the state strobe bus is connected to the control input of the state register, the outputs of which are connected to the state bus, the installation bus of the initial state is connected to the installation inputs of the trigger, counting trigger and trigger channels pulse sequences and through the inverter with the installation inputs of the reversible counter, period counter and the second input of the third element OR NOT, the output of which is Dinen with the installation of the register of the address of the multiplexer, the trigger output is connected to the first and second inputs of the first group of inputs of the element 2И-OR-NOT ₄ whose output is connected to the second inputs of the first and second elements OR-NOT and the second inputs of the elements ILY-NOT from the fourth to ( n + 3) -th, the output of the second element OR is NOT connected to the control input of the register, the outputs of which are connected to the discharge inputs of the reversible counter, the output of the zero state indication of which is connected to the recording input of the reversible counter and the counting input of the counter about the trigger, and through the second inverter - with the first input of the second group of inputs of the element 2И-OR-NOT, the inverse output of the counting trigger is connected to the second input of the second group of inputs of the element 2И-OR-NOT, and the direct output is the output of the converter reference signal and is connected to the counting input of the period counter, the outputs of which are connected to the inputs of the state register, the direct and inverse outputs of the counting trigger of each of the channels. The formation of sequences of pulses is connected to the first inputs of the first and second groups of inputs of element 2I-YLI- E of its channel of forming pulse sequences, and the high-order output of the register of each channel of forming pulse sequences is connected to the second input of the first group of inputs and through an inverter to the second input of the second group of inputs of the element 2И-OR-NOT of its channel of formation of the sequence of pulses, the outputs of all elements 2И- ORIN channels of pulse sequence formation are the signal outputs of the converter. 1485407