SU1228107A1 - Device for checking comparison circuits - Google Patents

Abstract

The invention Refers to the field of automation and computer technology and can be used in the implementation of a test diagnostic tool for blocks of discrete technology. The aim of the invention is to increase the reliability of control by ensuring that the low-order blocking circuits are checked. The device contains a permanent storage unit, a counter, registers, decoders, a trigger, a pulse generator, an error signal generating unit. The goal is achieved through the use of microprogram formation of input actions and device control. 1 hp f-ly, 2 ill., 2 tab.

Description

The invention relates to automatics and computer technology and can be used in the implementation of a test diagnostic tool for blocks of discrete technology.

The purpose of the invention is to increase the reliability of control by providing verification of the low-order blocking circuits of the older bits.

A device for controlling comparison circuits (FIG. 1) contains a comparison circuit 1, a permanent storage unit

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FIG. 1 shows a functional diagram of the proposed device for controlling comparison circuits; in fig. 2 - timing diagram of the pulses generated by the generator.

In tab. 1 shows the inputs to the controlled four-input comparison circuit and the corresponding firmware ROM 2.

T a b l and c a I

(PSB) 2, counter 3 (addresses), first 4, second 5 and third 6 registers, first 7 and second 8 decoders, trigger 9,

a pulse generator 10, an error signal generating unit comprising a comparison element 11 and an AND 12 element, first 13 and a second 14 AND element, an OR 15 element. In addition, the device contains inputs 16 and 17 for starting and resetting the device, output 18 for a device error, outputs 19-21 Less Equal and More circuit 1 compare the second, third, first outputs 22-24 of ROM 2, outputs 25-28 of the decoder 7, the second and first outputs of the pulse generator 10, block 31 of forming the error signal.

Consider the purpose of the elements of the proposed device to control the comparison circuits.

Scheme I comparison is subject to control. It is intended for comparing n-bit binary numbers, and forming rto to the results of comparing one of three possible signals: A B –at output 19, A 6 –– at output 20 or A B –– at output 2I. With proper operation of the comparison circuit 1, one and only one single signal should be present in its outputs.

 The permanent storage unit (SDB) 2 is intended for storing codes of micro-instructions that provide verification of the circuit. 1 of the comparison, the TZB information 2 is of a static type of TZB, i.e. the information on its outputs corresponds to that memory cell whose address is present at the entrance of the PZB 2, and is held at the output until the corresponding address is fed to the entrance of the PZB 2. The microcommands stored in the fire alarm 2 each contain a single bit number of code A and B (found at exit 22 of fire alarm 2), discharge control recording of information in registers 4 or 5 (read at exit 23 of fire safety 2) and the output number comparison circuit 1, on which a single signal must be present at a given monitoring cycle, or the device operation end code (read at output 24 of the PZB 2). For microinstructions stored in an OZB 2, it is received via the following coding. The zero code at the output of the security block 2 corresponds to the zero code of register A (6), code 00 .... 01-code 00 .... 01 register A

(B), code 00010 - P. code ... 010,

code 00011 - code 000100 and

etc. Dp codes at the output of 24 PZB 2 the following correspondence is accepted:

Code 00 Output PZB 2, A B Code 01, A B Code 10, A B

Code 11 End of device operation

Counter 3 of the address is used to form, store and address the address of the next microcommand read from the PZB 2. It is a binary summation counter, the state changes of which occur along the falling edge of the clock pulses received at its counting input. The installation of the counter 3 in the initial state occurs when

at its input R is a reset pulse, which is fed to the input 17 of the reset device.

Registers 4 and 5 are used to receive, store and read codes A and B respectively.

appropriately fed to the inputs of the comparison circuit 1 under control. The recording of information in registers 4 and 5 is carried out on the falling edge of clock pulses arriving at the inputs of C.

The registers 4 and 5 are reset to zero by the signal applied to input R.

Register 6 is for receiving, storing and recording the output number.

schemes 1 compare J for which there must be a single signal in a given control cycle, or a code for the end of the device operation. The recording is made on the falling edge of the impulse.

C at input, and reset of register 6 - when KMnyjjbca is checked at input R.

The decoder 7 is designed to decrypt the output number codes of the comparison circuit 1, in which

the control cycle must contain a single signal, or a code for the end of the device operation. The input of the decoder 7 is supplied with a two-digit binary code from the output of 21 PZB 2. When

code 00, the unit is present at output 24, with code 01 - at output 25, with code 10 - at output 26 and at code II - at output 27 of the decoder 7. Decoder 8. serves to decipher the number of digits of the code A or B which should be equal to one. The first - n-th outputs of the decoder 8 are connected respectively to the first n-th inputs of the registers 4 and 5. The zero output of the decoder 8 is free.

The trigger 9 start is used to start and stop the device.

It switches to one when the Start signal is applied to the device input 16 and returns to its original state when a failure of the monitored comparison circuit 1 is detected, at the end of the control of the comparison circuit 1, or when the Reset signal is input to the device 17. The element OR 15 implements the disjunction of these signals and forms. In accordance with the table. 2, the control unit 31 is built on a comparison element 11 and an element 12. The inputs of the comparison element 11 are supplied from the outputs of the comparison circuit 1 and the outputs 25-27 of the decoder 7. At the output of element II, the signal is equal to one if the binary codes received , with 45 outputs of the comparison circuit 1 and the decoder 7 coincide, and is equal to zero in the remaining cases. The output of the comparison element 11 is connected to the inverted input of the And 12 element, to the direct input of which 50 clock pulses are output from the output 29 of the generator 10. Due to this, the output of the 3J control unit forms the error signal if, upon receipt of the clock pulse There is no single signal at the output 55 of the comparison element 11, i.e. Comparison circuit 1 does not function correctly.

The reset signal to the input of the R-flip-flop 9.

The pulse generator 10 serves to form sequences of pulses that are shifted relative to each other, ensuring synchronization of the operation of the device. The timing diagram of the operation of the generator 5 is shown in FIG.

Block 31 Control serves to generate an error signal if the comparison circuit 1 does not work correctly (see Table 2).

table 2

Elements And 13 and 14 control the recording of information in registers 4 and 5, respectively.

The device for controlling the comparison circuits works as follows.

Before starting, all the memory elements of the device are set to the initial (zero) state by applying a Reset signal to the device input 17. When a signal arrives. Starting at input 16 of the device, trigger 9 is set to one and starts generator 10.

The first pulse from the output 29 of the generator 10 is fed to the control unit 31, as a result of which the correctness of the operation of the comparison circuit 1 on the Zero Au codes 8 is checked. On an alternating front of this pulse, the code of the number K, containing one in the first position, is written into register 4. This

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The odor is stored in the zero cell of the PZB 2. The code entry in the D register determines in this case the presence of a single signal at the output of 23 PZB 2. From the 24 Pb output, 2 simultaneously write to the registrar 6 code 10, corresponding to the output of the A B PZB 2 (figure 2). The clock pulse from output 30 of the 10 moderator in counter 3 is set to the address of the next (first) cell of 10 PZ 2.

A pulse from the output 29 of the generator 10 is fed to the input of the control unit 31, as a result of which the validation of the 15 operation of the comparison circuit 1 on the codes recorded in registers 4 and 5 is checked. On the falling edge of this pulse, another code is recorded in register 4 (FIG. 2). The next pulse from the output 30 of the generator IO in counter 3 is used to determine the address of the next memory cell of the PZB 2,

Further, the device operates similarly to that described.

In each operation cycle of the device, the code is updated only in one of the registers 4 and 5 and the correctness of the operation of the comparison circuit 1 on these codes is carried out. The verification of the operation of the comparison circuit 1 is carried out with all combinations of codes A and B containing no more than one unit. This ensures high reliability of the control and at the same time high speed of the device (short control time). The high reliability of the control is achieved by the fact that for each input of the comparison circuit I it is triggered by the outputs A-B, A & A & with both single and zero signals, i.e. both the chains of formation of single signals at the outputs 19-21 of circuit 1 and the blocking circuit of the lower bits of codes A (c) are checked by the senior bits of codes B (L).

If, at least in one control cycle, the control unit 31 generates a single signal, it will go to the device output 18, signal an error in the operation of the comparison circuit 1, and also through the OR 15 element to the input of the R flip-flop 9 and stop the operation of the device .55

If the comparison circuit 1 is valid, then in the last clock cycle, in the register 6, the code 11 is written, which will lead

thirty

45

07 °

The appearance at output 28 of the decoder 7 of a single signal (end of operation), which will stop the operation of the device. This is where the monitoring process ends.

Claims (1)

1. A device for controlling comparison circuits containing first and second registers, a trigger, a pulse generator, an error signal generating unit whose output is a device error output, outputs Equals, More, Less than a controlled comparison circuit connected to the first group of inputs of an error signal generating unit , the outputs of the first and second registers are connected respectively with the first and second inputs of the controlled comparison circuit, characterized in that, in order to increase the reliability of the control, it contains a counter, the third a gist, a persistent storage unit, two decoders, two AND elements and an OR element, the device reset input connected to the first, second and third register reset inputs, a counter and the first input of the OR element whose output is connected to the trigger reset input, whose setting input connected to the Start-up device input, and the output to the start input of the pulse generator, the first output of which is connected to the counter input of the counter, and the second output to the first inputs of the first and second And elements and allowing the input of the shaping unit the error signal and the syncro input of the third register, the information input and output of which are connected respectively to the first output of the permanent storage unit and the input of the first decoder, the first, second and third outputs of which are connected to the second group of inputs of the error signal generation unit, and the fourth output - with the second input of the OR element, the third input of which is connected to the output of the error signal generation unit, the output of the counter is connected to the address input of the permanent storage unit, the second output of which is connected ithout second decoder to data inputs of the first and second registers, the clock terminal of which are connected respectively to the outputs the first and second elements And, the second inputs of which are connected to the third output of the permanent storage device. 2, The device according to claim 1, characterized in that the Error signal reinforcement block contains a comparison node and an element, the first and the rpyiftnj inputs of the comparison node being diverted by the first and second groups of block inputs, and the output is connected to the first the input element And, the second input and output of which are connected respectively with permissive input and output of the block. S- gjot.f 29 f n n n n П t  n n n П П .. Vuit.2 editor Y. Sereda Compiled by L. Gorska Tehred I. Popovich 2288/50 Circulation 671 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., d.A / 5 Production and printing company, Uzhgorod, Projecto st., 4. Proofreader A. Obruchar