SU1295528A1 - Device for detecting errors in modular code - Google Patents

Abstract

The invention relates to computing. Its use in information processing and transmission systems in modular code (code in residuals) allows to simplify the device, which contains input registers 1, 2, memory block 3, adders 4, code converter 5, comparison block 9 and And 11 element. The introduction of a pulse counter 6, an unequalness block 8, an element OR 10, and a control block 7 provides the possibility of detecting an error using the number rank function, thereby simplifying the execution of the device. 1 hp f-ly, 2 ill. i (L

Description

The invention relates to computing and can be used in information processing and transmission systems in a modular code (system code of residual classes),

The purpose of the invention is to simplify the device.

Fig, 1 shows a block diagram of the device; in fig. 2 - functional block diagram.

The device for detecting errors in the modular code contains the first and second input registers 1 and 2, memory block 3, adders 4, code converter 5, counter 6, control block 7, remap blocks 8, comparison block 9, OR element 10 and element And 11, has the first and second information inputs 12 and 13, control inputs 14, input 15 start, clock input 16 and output 17,

Input register 1 is the shift register, in which

P

remnants of x ,, x,. the numbers X on the base of m p,, p, ..., p. Moreover, one clock pulse shifts the sequence of residues in such a way that at the outputs of register 1 the code of the next residue appears.

Input register 2 is a static parallel register in which the residuals x.,,, .., are written, where m is the number of redundant bases, on control bases PJ ,,, ..., RK, ".

The preset buses of registers 1 and 2 are not shown, since it is assumed that by the time the device starts operating, the residuals x ,, ,,., X, k, t .., Kt are registered in registers 1 and 2.

The adders 4 from the first to the t-th are modulo-0 adders, respectively, and are accumulative-type adders with the ability to pre-record the initial value.

The control unit 7 (FIG. 2) contains a delay element 18, a trigger 19, an AND element 20, a pulse distributor 2, a pulse counter 22 and a threshold unit 23, has first and second inputs 24 and 25 and first to fourth outputs 26 -29.

- Comparison block 9 generates a signal if the code on its first inputs is larger than the second.

95528; 2

The threshold unit 23 (Fig. 2) issues a signal if its input code is not less than 2n-1.

In its operation, a device for detecting errors in a modular code uses the following.

For the range of P, we determine the number Xel l ,, .., which is represented by the comb

fo

15

20

Ipn kupnitsugo residues x ,, l, ...,

 on a mutually simple basis m p ,, pg,

1 P

..., p „, It is obvious that R., P is n-obra-) 1 1 g

This sets zero code space.

For such a non-positional representation of the number X, the positional characteristic can be determined. The normalized rank of the number

-MX) r (X) -i: (i) i- - J 1 J

where r (x) is the function of the rank of a number;

W JL fl, 1 l

- - l (mod Р;) - basic numbers.

C; P g (X) can be found from

X

, p ZlxjB - r (X) P (2)

n i-1

From equations (1) and (2) express (X) as follows:

35

:) (x) (

; t-Gh; tL-. | x | p „,,.

-RG L-pyj

An excess base p is introduced, according to which the transformation from the extrusion | p; -

 TO

one

)

If there are several redundant bases, pit ;,, .. ,, ri, then,

t ™

represented Ru.-Pr as p., out of 1-1 I

razheni (5) are (X), taking into account.

50

that in this case m x; L,

(6)

five

where L is the base number for the system

RK grounds,)

Substituted the expression (6) and (5) have. - | :(,. p. |,

(X)

 X to L;

(7)

3 1295528 Calculate (X) with the help of expression (7) is difficult and therefore, using the fact that P is composite, calculating

l am i

Chh)

Chh)

4x); t (X); j l, m

P "1,

V- f g. jiiHJ-1 fc P L RI,

) +

+ X

PK;

ten

}

To compare (X) with ,, taking into account the expression (11), it is enough to compare the FW) among themselves and one of them with the value I 1 1- If (X) is not equal to each other,

 J) p; (° 5 „always. (X)„. Set (X), ... / (X)) are equal, one of them

Expression (9) is valid because

; 1L 0,

Consequently

more, then (X) - T1 is nothing but residues from d) (X) modulo m p, ..., p.

Known

max

. VI

Therefore, for an ordered system of bases

.- (Yu 25

J20

  Rkg 3 ..

Let X, 241 4- (1,3,, 3) be great. number. If an error occurs in two numbers, then - 55 residues, for example,

(X) And 1 + 8 + 4-1-7 8 Кз 1;

(X) {4 + 3 + 2 + 3-31.7

 one,

Thus, calculating (X) and) (X), we conclude that X, is correct;

then

X, (1,5,10,7 4),

54x) ln + 4 + 4 + 7-8l, 10; (X) | 4 + 10 + 2 + 4-31 7 11.

528

If any error of multiplicity m and less occurs, then always wrong X is out of range P,

 It can be shown that when implementing algorithm (9) for () P „numbers that do not belong to Gr (X), i.e. these wrong numbers vyrti

are the calculation (9).

ten

" is always. (X) “. ) are equal, one of them

more, then (X) - T1. In this way, the preceded algorithm allows one of the wrong

numbers recognize the overwhelming number of them for the number of ticks not more (n + 1) for any number of redundant bases.

Example

number. If an error occurs in the residuals, for example,

then

X, (1,5,10,7 4),

54x) ln + 4 + 4 + 7-8l, 10; (X) | 4 + 10 + 2 + 4-31 7 11.

 As a result, it is concluded that X is an incorrect number.

The device for detecting errors in the modular code works as follows.

In the initial state, the remains of x ,, x,.,., K are entered in register I.

The register 2 contains the residuals k, x, .... At the outputs of the converter 5 of the code, the values of the codes Ix, f, jJ,, ..., | x, p / are formed, respectively.

The input 16 receives clock pulses, the trigger 19 is set to zero Ipvcm

Added value codes 0p

 d. By the last clock, 2p-2 clock pulses 5 cs ,, arrive at the input of the counter 22, and the arrival of the (2p-1) -th clock pulse at the start of the threshold unit 23 appears a logical unit, which sets the trigger 19 in ° zero state, thereby prohibiting further input of clock pulses.

At this time, the contents of adders 4 correspond to Ai (X), ...)

If cho) (x) ..,) (x)

The new state, and, respectively, at f5n, 8, then at the outputs of blocks 8 and 9 of the outputs, the distributor 21 has no pulses.

A start impulse arriving at input 15 sets the counter 6 to the initial zero state and, having passed through the control block 7 to output 28, writes to the adders 4 from the first

 x ,, fi

logical zeros do not change the value of the logic level at the output of the element OR 10 and, accordingly, the element AND P, thereby establishing, 20 seconds, the correctness of the number X,

If (X) 5 - 3-FH), i, j6 i, n, or (X) v 5, then the logical unit at the output of the element OR 10 leads to the appearance of a logical unit and also sets the initial state, the output of the element AND P, since on his

on t and value codes 11

. fpk,

I.4.I -1 (I GK5 Xi-ft n respectively, a

I Km P I pKm

distributor 21 pulses and a counter-22. After a time determined by the end of the transients in the adders 4 and the memory block 3, the trigger 19 is set to the one state through the delay element 18. the Received at the input of the 16 clock pulse leads to the appearance of a pulse at the output 27.

By this time, at the outputs of the block of the 35th day, the proposed device, 3 memory codes Op, (x,), are formed easier to perform than .... 0p | j (x), which, when an output pulse appears, is 27 the values of these codes are added to the contents of adders 4 from the first to the t-th, respectively.

The next clock pulse at input 25 results in a pulse at the output of control unit 7, as a result of which the content K is shifted 45 are connected to the right and to the inputs of memory block 3, the inputs of the code converter, the residual code Xj is output , The contents of the counter whose number is connected to the first inputs

the second input is a logical unit from the output of the threshold unit 23.

Thus, the unit at output 30 of the element I 1 indicates that the number X is wrong and that is, i.e. distorted (error reaches multiplicity t)

Thanks to the use of functions

known-;

Claims (2)

Formula isob-retenn 1, A device for detecting an error in a modular code containing a first input register, a memory block, a second input register, the outputs of which are 6 is increased by one. At the outputs of memory block 3, a code is formed. The dam of the corresponding adders, the comparison unit and the AND element, the inputs 9р (х), ..., 0р (х), which with 50 first and second input registers   Tf CJli GTPGG GT GG / G /.GPPtgee/: TG grti1GTG T11-GTLLTL TjrTJr r4-nT; A TTT; r the arrival of the next clock pulse is added to the contents of the adders 4 from the first to the tth, respectively. are appropriate; thin: by them informational inputs of the device, the output of the element I is the output of the device, characterized in that, in order to simplify the device, a pulse counter, an inequality block, an OR element and a control unit, the first output of which is connected to the counter input, are entered into it Similarly, the operation of the device continues until the contents of the adders 4 are Added value codes 0p  r, the last clock to the input of the counter 22 receives a 2n-2 clock pulse, and upon the arrival of the (2n-1) -th clock pulse on the 1st input of the threshold unit 23 a logical unit appears, which sets the trigger 19 in ° the zero state, thereby prohibiting the further arrival of clock pulses. In this cycle, the contents of adders 4 correspond to Ai (X), ...). If cho) (x) ..,) (x) the second input is a logical unit from the output of the threshold unit 23. Thus, the unit at the output of the element And 1 indicates that the number X is wrong and that is, i.e. distorted (error reaches multiplicity t). Thanks to the use of functions    the numbers proposed by the device, your simpler to perform than connected to the respective inputs of the code converter, the output of which is connected to the first inputs known-; Formula isob-retenn 1, A device for detecting errors in a modular code comprising a first input register, a memory unit, a second input register, the outputs of which connected to the corresponding inputs of the code converter, the output of which number is connected to the first The dam of the corresponding adders, the comparison unit and the AND element, the inputs 50 first and second input registers CJli GTPGG GT GG / G /.GCHPtgge/: TG grti1GTG T11-GTLLTL TjrTJr r4-nT; A TTT; r are appropriate; thin: by them informational inputs of the device, the output of the element I is the output of the device, characterized in that, in order to simplify the device, a pulse counter, an inequality block, an OR element and a control unit, the first output of which is connected to the counter input, are entered into it of the pulses and the control input of the first input register, the outputs of which are connected to the corresponding information inputs of the memory block, the outputs of the counter are connected to the corresponding address inputs of the memory block, the first —thir outputs of which are connected to the second inputs of the corresponding adders, where m is the number of redundant bases, the outputs of the first adder are connected to. the corresponding first inputs of the first block of inequality, the outputs of the i-ro adder, is L2} m-lj are connected to the corresponding first inputs of i-ro and the second inputs (il) -ro imbalances, the outputs of the t-th adder are connected to the corresponding second inputs (ni-l) -ro of the inequality block and the nepBFjiM inputs of the comparison block, the outputs of the unequality block and the comparison block are connected to the corresponding inputs of the OR element whose output is connected to the first input of the element I, the second and third outputs of the control unit are connected to the corresponding third and fourth inputs of the adders, the fourth output of the control unit is connected to the second input of the element I, the first and the second inputs of the control unit are 25 Compiled by Revinsky Editor O..Yurkovetska Tehred-L, Serdyukov Proofreader O, Lugov Order 628/62 Circulation 902 Subscription VNIRSHI State Committee of the USSR for inventions and discoveries P3035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, st. Project, 4 respectively, the Start input and the clock input of the device, the second inputs of the comparator unit are the control inputs of the device. 2. The device according to claim 1, characterized in that the control unit is executed on a trigger, pulse distributor, pulse counter, threshold unit, AND element and delay element, the output of which is connected to the first input of the trigger, whose output is connected to the first input of the AND element, the output of which is connected to the clock input of the pulse distributor and the counting input of the pulse counter, the outputs of which are connected to the corresponding inputs of the threshold element, the output of which is connected to the second trigger input, the first and second outputs are distributed The pulses are the first and second outputs of the control unit, the input of the delay element and the inputs of the pulse distributor and the pulse counter are combined and connected to the first input and the third the output of the control unit, the second input of the element I is the second input of the control unit, the output of the threshold element is connected to the fourth output of the control unit.