SU1594702A1 - Positional code encoder - Google Patents

Abstract

The invention relates to computing and can be used in information exchange systems. The invention provides for the scrambling of the output sequence of position codes, which leads to the expansion of the functionality of the encoder. The position code encoder contains 1 clock pulse generator, AND 2.3 and 9 elements, summing up 4 and subtracting 5 pulse counters, comparison block 6, AND block 7, switches 8 and 11, information input block 10, registers 12 and 13, and block 14 memories. 1 il.

Description

The invention relates to computing and can be used in information exchange systems.

The aim of the invention is to enhance the functionality of the encoder by ensuring that the position codes are consistent with scars.

The drawing shows the functional scheme of the encoder,

The encoder contains a clock pulse generator 1, the first and second elements AND 2 and 3, summing and subtracting counters 4 and 3 pulses, a comparison block 6, a block of 7 elements AND the first switch 8, a third element AND 9, a block 10 for entering information, the second switch 11, first and second registers 12 and 13, and memory block 14. Position 15 denotes the outputs of the encoder

The generator 1 is running continuously, while the input to the counter 4 through the element And 2 and to the input of the counter 5 through the element And 3 do so. marketing pulses, In the initial state, to all information inputs1; the switches 8 and 11 receives signals about from the block 10, At the outputs of the switches 8 and 11 there are logical signals that, -access respectively to the inputs of the elements - Tov And 2 And 3, allow the passage of pulses of the clock frequency to the inputs of counters 4 and 5, Number the possible states of the latter are equal to the number of information inputs by the switchboard 8 and 11. Each current state of the counters 4 and 5 causes the broadcast to the outputs of the switches 8 and 11 of the signal corresponding to this state of the information input. Moreover, the order of the following: The status of counters 4 and 5 is reciprocal, t, e, if the arrival of pulses at counters 4 and 5 began when they were in the same state, then these states are repeated periodically and simultaneously. In addition, the content of block 14 is such that at a certain initial state of register 13 and the uniformity of the co-f of register 12 and counter 5, the continuous generation of pulses by generator 1 causes the block 6 to periodically form a comparison

logical, However, this signal of logical 1 from block 6 does not pass

five

through the element AND 9 to the block 7 of the elements AND, since the input of the element AND 9 is connected to the output of the switch 8, which has a logical O signal at this moment, Therefore, through the block 7 the position code from the counter 5 to the inputs of the encoder is not read,

10Discharge of registers 13 and 12 is the same with counters 4 and 5. The number of code combinations, each of which corresponds to one of the possible states of the counter 4 15 or 5, is pre-recorded for storage in block 14, If you conditionally represent these code points combinations in the form of a square matrix, the row address and column of which is set when each combination is read, respectively, by means of counter 4 and register 13, then in each row and each column of this matrix any code combination should not be repeated bs twice. With a given content of block 14 and with a constant state of register 13, the arrival of clock pulses at counter 4 and the control input of register 12 ensures a sequential and line-by-line interrogation of the content of the corresponding column stored in block 14 of the matrix. Neither counter 4 and register 12, as a rule, are not the same, although they unambiguously relate: to each other through the matrix of block 14, This means that, having information about the states of counter 4 and register 13, it is always possible to unambiguously determine the state of register 12, Cipher The position code torus works in the following way.

When a signal is received logic 1 from block 10 input information to 5 one of the information inputs of the switch 11 and the coincidence of the code combination removed; from register 12, with a code combination that permits the passage of a logical 1 Q signal from this particular information

the input of the switch 11 to its output, at the last the signal appears logical 1, This signal prevents the passage of pulses of the clock frequency J from the generator 1 to the input of the counter 4, to the inputs of the block 14 and the register 12, As a result, the counter 4, block 14 and the register 12 stop. By analogy, a logical 1 signal appears at the output of the switch 8, which also prohibits the pulse through the element I 3 of the clock frequency to the counter 5, and it stops in the same state as the register 12 And the counter 5 stops in time can both get ahead and be late f relative to the stop of the counter, block 14 and register 12,

As soon as the states of counter 5 and register 12 coincide, the logical O signal at the output of comparison block 6 changes to logical 1 signal, which passes through AND 9 to block 7, and the position code of counter 4 status is read out to encoder outputs 15. At the same time, under the influence of the same signal of logical 1, the same position code is read into register 13, erasing the same code in the latter. Element And 9 in this case is unlocked by a logical signal 1 from the output of the switch. 8,

When the logical 1 signal is removed, the prohibition signals on the outputs of the switches 8 and 11 are removed from the selected initial information input of switch II and the corresponding information input of switch 8, the clock pulses are again fed to the inputs of counters 4 and 5, which continue to work in reciprocal cycles stopping points due to a logical 1 signal being applied to the information inputs of switches 8 and 11,

If logical 1 signals are randomly sent simultaneously to two information inputs of switch 11 and to two corresponding information inputs of switch 8, then counter 5 and register 12 are stopped in unequal states, i.e. in different. Comparison unit 6, respectively, does not generate a logical 1 signal, which means that the position code from counter 4 is not read by block 7, although AND 9 is unlocked at this moment. The error in the operation of the position code encoder can be corrected by eliminating the false signal of logical 1 on

relevant information inputs 5 elements And,

The encoder is a generator that generates outputs with inputs I, outputs with inputs of inputs and calculations, outputs of impulses with a block of units of a block of electrical inputs with feathers from the second elect of the third electric connected with cops And, with an output of encryption, output of the second com the second by the second input of the third commutator's input is the input of the first e) the scrambled scrambled positioning positions of the positioning were entered by the registers whose inputs were given to the block of the counting unit by the first input formations, the outputs to the left input inputs of the first connected

switches 8 and 11 / by releasing the wrong button KEYPAD of the block 10) and. preserving the true signal of the logical 1 at the other information inputs of the switches 8 and II,

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Claims (1)

Invention Formula A position code encoder containing a clock pulse generator, the output of which is connected to the perimeter inputs of the first and second electrical elements I, whose outputs are connected to the inputs of the summing and subtracting pulse counters, respectively, the outputs of the readout pulse counter are connected to the inputs of the comparison unit, with the first inputs of the block of elements And with the address inputs of the first switch, the output of which is connected to the second input of the second element And and the first input of the third element And, the output of which is connected to the second input of the block And, whose outputs are the output of the encoder, the information input unit, the outputs of which are connected to the information inputs of the first and second switches, the address inputs of the second switch are combined with the second inputs of the comparison unit, the output of which is connected to the second input of the third element And, the output of the second switch is connected to the second input of the first element AND, which is connected. In order to broaden the functionality of the encoder by scrambling a sequence of position codes, the encoder has entered registers and a memory block whose outputs are connected to the information inputs of the first register whose outputs are connected to the second inputs of the comparator, outputs the summing pulse counter is connected to the first inputs of the memory block and to the information inputs of the second register, the outputs of which are connected to the second inputs of the memory block, the control inputs of the first and second registers are connected to the outputs of the first element AND and the third, respectively.