SU1181156A2 - Position coder - Google Patents

Abstract

ENCRYPTION POSITION CODE on auth.St. No. 875625, characterized in that, in order to improve the reliability and reliability of the position code, a subtractive counter, an additional switch, the second and third And elements, the comparison unit and the And elements block, the first inputs of the second and third And elements are included in it to the output of the additional switch, the second inputs are connected to the outputs of the clock pulse generator and the comparison unit, respectively, and the outputs are connected respectively to the input of the subtracting counter and the control input of the AND block The inputs of which are combined with the first inputs of the comparison unit and the address inputs of the additional switch and connected to the outputs of the readout counter, the information inputs of the additional switch are connected to the outputs of the information input unit, the second inputs (L of the comparison unit are connected to the outputs of the counter, and the outputs of the element block And device outputs.

Description

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The invention relates to computing technology, can be used in automated systems for the exchange of information between objects and is an improvement of the invention according to the author. No. 875625.

The purpose of the invention is to improve the reliability of the device and the reliability of the position code.

The drawing shows the functionality of the device;

. The encoder contains a generator 1 of such pulses, an element 2, a counter 3, an information input block 4, a switch 5, a block of 6 elements AND, an element of AND 7, a subtractive counter 8, an additional switch 9, a block of comparison 10 and a third element 11 .

The encoder positional code works as follows.

The generator 1 operates continuously, while the input of the counter 3 through the element 2 and the input of the subtracting counter 8 through the element 7 receives the clock pulses. In the initial state, all information inputs of the switches 5 and 9 receive signals of the logical O from the block .4. At the outputs of switches 5 and 9 there are logical O signals, which, arriving at the second inputs of elements 2 and 7, respectively, allow the passage of clock pulses to the inputs of counters 3 and 8. The number of possible states of the latter is equal to the number of information inputs of switches 5 and 9 Each current state of the counters 3 and 8 causes the translation to the outputs of the switches 5 and 9 of the signal from the information inputs of the switches corresponding to this state. Moreover, the order of the following states of the counters 3. and 8 is reciprocal, i.e. . If the arrival of pulses to counters 3 and 8 began when they were in the same state, then these states repeat periodically and simultaneously. This ensures periodic generation by the comparison unit 10 of the logical 1 signal. However, this logical signal from the block 10 does not pass through the element 11 to the block 6 of the elements AND, since the input of the element 11 is connected to the output of the switch 9, which at this moment

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the signal of logical O. Consequently, through block 6, the position code from counter 8 to the outputs of the encoder is not read.

When a signal is received logical 1 block 4 input information to one of. information inputs of the switch 5 and when the code combination taken from counter 3 coincides with the code combination allowing the logical 1 signal to pass from this information input of the switch 5 to its output, the logical signal appears at the last one. 1, - This signal prohibits the passage of pulses of the clock frequency from generator 1 to the input of counter 3 and the latter stops. By analogy, at the output of switch 9, a signal of logical 1 appears, which also prohibits the passage through the element AND 7 pulses of the clock frequency to the counter 8 and it stops in the same condition as

counter 3. Moreover, the stop of the counter 8 in time may be ahead, late in relation to the stop of the counter 3.

 As soon as the states of the counters 3 to 8 match, the signal of the logic at the output of the comparison unit 10 changes to a signal of the logical 1, which passes through the AND 11 element. The block 6 and the positive code (the state of the counter 8) are read into the outputs of the encoder. Element 11 in this case is broken. Blocked by a logical signal 1 from the output of switch 9.

When the logical 1 signal is removed, the prohibition signals on the outputs of the switches 5 and 9 are removed from the initially selected information input of the switch 5 and the corresponding information input of the switch 9. The pulses of the clock frequency again arrive at the inputs of counters 3 and 8, which continue to operate in mutually similar cycles until -. wok due to the signal of logical 1 to the information inputs of the switches 5 and 9.

If the signals of logical 1 are randomly given simultaneously to two information inputs of switch 5 and to two corresponding information inputs of switch 9, then counters 3 and 8 stop in unequal states.

those. in equal. Comparison unit 10, respectively, does not understand the signal of logical 1, which means positional, the code from counter 8 is not read by block 6, although And 11 is unlocked at this moment. Information about erroneous encryption can be output as an Opshbk signal — in operation, on a special indicator. The error in the operation of the position code encoder can be corrected by eliminating the false signal of logic 1 on the corresponding information inputs of switches 5 and 9 (by releasing an incorrectly pressed key of block 4) and storing the true signal of logical I on other information inputs of switches 5 and 9. Then the error signal is in operation the encoder disappears and an accurate position code is generated.

Claims (1)

POSITION CODE ENCRYPTOR for autosv., No. 875625, characterized in that, in order to increase the reliability and reliability of the positional code, a subtracting counter, an additional switch, the second and third I elements, a comparison unit and an I element block, the first inputs are introduced into it the second and third elements And are combined and connected to the output of the additional switch, the second inputs are connected to the outputs of the clock and block, respectively. for comparison, and the outputs are connected respectively to the input of the subtracting counter and the control input of the AND block, the inputs of which are combined with the first inputs of the comparison unit and the address inputs of the additional switch and are connected to the outputs of the subtracting counter, the information inputs of the additional switch are connected to the outputs of the input block information, the second inputs of the comparison unit are connected to the outputs of the counter, and the outputs of the block of elements And are the outputs of the device. SU, „, 1181156 j 1181