SU1734095A1 - Signal sequence tester - Google Patents

Abstract

The invention relates to automation and computing and can be used in control systems for monitoring commands and signals. The purpose of the invention is to expand the functionality by controlling the intervals between signals. The device contains a register, a block for determining the sequence of selecting signals with elements, a multiplexer, a counter, a decoder, NOT, AND elements, a counter, a register, a trigger, an OR element, a permanent memory block, a trigger, a register, a counter, an OR element, a comparison block, element And, the pulse generator. In the proposed device, by introducing two registers, a signal extractor, a decoder, a counter, AND, OR elements, is NOT provided, along with control of the sequence, control of the signal arrival intervals, which expands the functionality of the device, improves the quality, depth and reliability of the systems with cyclic sequences of commands and signals. 2 Il. ate with

Description

The invention relates to automation and computing and can be used in control systems for monitoring commands and signals.

The purpose of the invention is to expand the functionality of the device in the process of monitoring cyclic sequences of potential signals by controlling the time intervals between them.

FIG. 1 shows a functional diagram of the device; in fig. 2 is a time diagram of the operation of the device for two input signals.

The device contains inputs 1 controlled sequence signals, register 2 CO-triggers, block 3 determining the sequence of signals, including the elements AND 4, NOT 5, OR 6, multiplexer 7, s. Counter 8, the decoder 9, the element NOT 10, the element 11, counter 12, register 13, trigger 14, element OR 15, fixed memory block 16, trigger 17, register 18, counter 19, element OR 20, comparison block 21, AND element 22, initial setup input 23, pulse generator 24.

The device works as follows.

In the initial position, the initial setup signal supplied via input 23 sets to zero the state of counter 12, registers 13 and 18, via the OR 15 element

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- trigger 14, through the element OR 20 - counting hours /; to 13 /, trigger 17, which resets the error signal from its inverse output, to one state. The trigger 14 of the signal- / -, Oiv, from its inverse output opens the-element 1/1 11. The clock pulses of the generator 1st, go to the clock inputs of the counter-, oa 12 and 19 and, through the element 11, to the clock inputs of the trigger register 2.

The step bars 12 and 19 are turned on in a continuous counting mode over a clock slice. Counter 12, through multiplexer 7, cyclically and sequentially polls the outputs of block 3. In the absence of input signals at inputs 1, the triggers 2 are set to the zero state by the front of the current clock pulse. Therefore, zero inputs are set at the input, ah, and outputs of block 3, as well as at the output of multiplexer 7. The zero signal of multiplexer 7 through the element NOT 10 keeps the counter 8 in the zero position.

The monitored potential signals are cyclically input to inputs 1 as follows: the signal arriving first is fed to input 1-1; the signal arriving second is input 1-2, and m, e., the signal arriving is (n + 1) th, and input 1 is (n + 1). At the same time, the limit value of the time interval between the first and second signals is TI, between the second and third signals - T2, etc., between (n-1) -th and n-th signals Tn-1. When the first signal of the sequence at input 1-1 arrives, the trigger 2-1 of register 2 by the front of the current clock pulse from the output of the element I 11 is set to one. The first signal at input 1-1 is held to the end of the signal sequence. Trigger 2-1 opens element AND 4-1 in block 3, in which all elements AND 4-1, 4-2 ... are prepared for opening, but which are not receiving signals from triggers 2-2, 2-32 - ( n + 1).

When interrogating the output of the AND 4-1 element, a single signal is generated at the output of the multiplexer 7, which blocks the operation of the counter 12 and through the NOT element 10 turns on the counter 8.

In addition, by the front of the multiplexer 7, the trigger 14 is set to one state, since the signal 1 is constantly applied to its D input. At the outputs of the counter 12, the address (number) of the first monitored signal is generated. This address is fed to the first address inputs of the memory 16 and the information inputs of the register 13. The second address inputs of the block 16 receive the zero address from the outputs of the register 13, the latter intended to store the address of the previous monitored signal of the sequence.

Thus, the cumulative address supplied to the memory block 16, with the correct sequence of monitored signals, contains the addresses of the previous and subsequent signals. For each of the correct cumulative addresses in the block

The following information is preliminarily recorded in the 16th memory: the sign of the correct sequence and the sign of the interval in the form of level 1 signals (outputs 3 and 1 of block 16, respectively) and the time interval code (T- |, T2 ... TP, outputs 2 of block 16).

The trigger 14 controls the sampling of the indicated signals from the memory block 16 and closes the AND 11 and 22 elements. The clock pulses no longer arrive at the clock input of the register 2. In addition, the trigger 14 through the OR 20 element keeps the counter 19 of the interval in the zero state. After turning on the counter 8 counts to the front of the fourth clock pulse. A signal is generated at its third output, which blocks further counting at counter 8. Two states of counter 8 (01.10) are decoded by decoder 9, elements 9-1, 9-2, which are gated with inverse clocks from the output of the element five.

The pulse from the first output of the decoder 9 is fed to the clock inputs of the trigger

17 and register 18. A sign of the correct order from output 3 of block 16 confirms the single state of trigger 17 and no error signal is generated. The interval indicator and interval code (for the first signal-Ti) from outputs 1 and 2 of block 16 are recorded in register 18. Moreover, the interval code from the group of outputs of register 18 is fed to the first inputs of comparator 21, and the sign of interval from the output of the corresponding register bit 18 element 22 prepares for opening. The second pulse of the decoder 9 fixes in the register 13 the address of the current first monitored signal from the output of counter 12, through the element OR 15 sends the trigger 14 to the zero, which opens the elements 11 and 22 and through the element OR 20 removes the signal from the reset input of the counter 19.

Counter 19 is included in the TL interval counter mode. In the case that during the time Ti, the second monitored signal does not arrive at the input 1-2 of the device, the counter 19 is filled with clock pulses to a state identical to the code in register 18, and the comparison unit 21 generates an error signal interval, which through the element And 22 blocks the counter 19 and is issued to an external device.

In case the second monitored signal enters input 1-2 within the interval T- |, the front of the current clock pulse of the element 1/111 sets the trigger 2-2 to one state and confirms the single state trigger 2-1, since the first the signal is kept at input 1-2 until the end of the entire sequence of signals. The trigger 2-2 through the elements OR 6-1, NOT 5-1 closes the element AND 4-1 in block 3 and, thus, in block 3, the output signal is generated only at the output of the element AND 4-2,

After the AND 4-1 element is closed, the signal from the output of the multiplexer 7 is removed, which is addressed by the counter 12 to the output of the AND 4-1 element. In this case, the prohibition signal is removed from the control input of the counter 12 and it continues polling the outputs of block 3 from the current address. When interrogating the output of the AND 4-2 element at the output of the multiplexer 7, a signal is again formed and the process is repeated. In this case, the trigger 14, through the element OR 20, resets the counter 19 to zero before producing the interval Tb, and the register 18 writes the code of the interval T2, and so on. In the future, the last signal at input 1 - (n + 1) includes a trigger 2 - (n + 1), which through the elements OR 6 (n-1), 6-2, 6-1 is NOT 5-n, 5 (n- 1), 5-2, 5-1 closes the elements AND 4-p, 4- (p-1), 4-2,4-1 and generates an output signal only at the output n + 1 of the block 3. At the same time, all the triggers of the register 2 included. The last (n + 1) -th signal of the sequence is assigned in time from the first signal of the next sequence to the interval Tn, during which all signals at inputs 1 are reset and then the first signal arrives at input 1-1 and so on.

In case of violation of the order of input signals, for example, (n + 1) -th signal comes second or instead of one second signal several signals simultaneously arrive — the second, third and (n + 1), the signal (n + 1) closes all And 4 elements in block 3, and the output signal is generated only at the (n + 1) -th output of block 3. At the same time, the counter 12 sets the address of the (n + 1) -th signal.

Thus, the address inputs of the memory block 16 are supplied with a cumulative address containing an incorrect combination of source addresses: the address of the (n + 1) -th signal in counter 12 and the address of the first signal in register 13 recorded in the previous processing cycle of the first monitored signal. In block 16, in cells addressed to incorrect cumulative addresses, zero information is recorded. Therefore, the first pulse of the decoder 9 sets to the zero state the trigger 17, from the inverse output of which a priority error signal is output.

The device works similarly for other violations of the sequence and intervals in the monitored sequences of signals.

Claims (1)

Invention Formula A device for controlling a signal flow sequence, comprising a pulse generator, the output of which is connected to the counting inputs of the first and second counters, a group of outputs of the first the counter is connected to the group of address inputs of the multiplexer, the first group of address inputs of the fixed memory unit and the group of information inputs of the first register, the output group of which is connected to the second group of address inputs of the fixed memory unit, the first and second triggers, the first element I, the first element OR , the first input of which is connected to the input of the initial installation of the device and the reset input of the first register, the output of the first element OR is connected to the reset input of the first trigger, a comparison unit, characterized in that, in order to expand the functionality of the device by controlling the time intervals between signals, the second and third registers are entered, the order determining unit, the decoder, the third counter, the second element OR, the second element AND, the element NOT, and the inputs of the controlled sequence of the device are connected to the information inputs of the corresponding bits of the second register pa whose outputs are connected to information inputs of the signal extraction unit, the outputs of which are connected to a group of information inputs of the multiplexer, the output of which is connected to the resolution input of the first counter, input the NOT element and the clock input of the first trigger, the information input of which is connected to the bus of the logical unit, the element output is NOT connected to the reset input of the second counter, the inverse output of the third bit of which is connected to the enable input of the second counter, the outputs of the first and second bits of which are connected to the same the inputs of the decoder, the gate input of which is connected to the output of the pulse generator and the first input of the first element And, the output of which is connected to the clock input of the second register, the first output of the decoder is connected to the clock inputs of the second trigger and the third register, the group of outputs of which connected to the first group of inputs of the comparison unit, the second group of inputs of which is connected to the output group of the third counter, the counting input of which is connected to the output of the pulse generator, and the enable input to the error output of the device interval and the output of the second element I, the first input of which is connected to the output of the third register, the second input of the second element And is connected to the output of the comparison unit, the third input of the second element And is connected to the second input of the first element And and the inverse output of the first trigger, the direct output of which Connected with the first input of the second element OR and the sample input of the block of the permanent memory, the output of the interval feature and the group of outputs of the interval of which are connected to the corresponding information inputs of the third register, the output of the sign of the correct order of the block of the permanent memory is connected to the information input of the second trigger, inverse the output of which is the output of the device queue error, the single input of the second trigger is connected to the reset inputs of the third register, the first counter, the initial setup input and the second input of the second OR element, the output of which is connected to the reset input of the third counter, the second output of the decoder is connected to the clock input of the first register and the second input of the first OR element, the signal queuing unit contains a group of n elements AND, a group of -1) elements OR, a group of n elements NOT, where (n + 1) is the number of inputs of the block for determining the sequence of signals, the first to the nth inputs of the block for determining the sequence of signals are connected to the first inputs of the corresponding elements AND group, and the inputs of the signal queuing unit, from the second to the nth, are connected to the first inputs of the corresponding OR elements of the group, the output of the first OR element of the group is connected through the first element NOT groups with the second input of the first element AND group, the output of each subsequent element OR group, from the second to (n-1) -th, is connected to the second input of the previous element OR group and through the corresponding element of the NOT group is with the second inputs of the second and subsequent elements AND of the group of the up to (n-1) -th element, respectively, (n + 1) -th input of the signal sequencer is connected to with the same output of the signal queuing unit, with the second input of the (n-1) -th element of the OR group and, through the nth element of the NOT group, with the second input of the n-th element AND group, outputs of the elements And the groups are the outputs of the signal queuing unit. and s  x i "NJ